Chapter 6 Conclusions and Future Work
In this thesis, an implementation of 2-tap adaptive decision-feedback equalizer operating at 10 Gb/s of data rate is presented. The data eye at equalizer output can reach ±200 mVpp and has a 31ps peak-to-peak jitter. The total chip area including pads is 510 × 510 μm2 and the total power consumption is 40.63 mW. The proposed circuit is designed in a 65nm CMOS technology.
From the concern of reducing power consumption, we explore a coefficient-update scheme called hopping update scheme to slow down the clock rate in the coefficient adaptation block. Since the channel may vary slowly with temperature and time, it is not necessary to update the coefficients very fast. Moreover, we utilize a 4-bit up/down counter and a charge pump to form a mixed-signal integrator for controlling the coefficient. The 4-bit up/down counter has the advantage of reducing the input offset of the charge pump and better MSE performance. Instead of using DAC, the easy and small charge pump can do the same work and save area.
Since the data rate is over several multi-Gbps, if the impact of ISI induced by channel is very severe, the number of DFE taps needs to increase, or an FFE is required in the transmitter or in the receiver side to alleviate the design of DFE. Most important of all, if there exists a CDR, the clock could sample the data automatically and the equalizer and CDR could cooperate regularly to become a simple receiver.
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