Chapter 3 Equalization Basis
3.2 Discrete-Time Equalization
3.2.3 Decision-Feedback Equalizer
Decision-feedback equalization [22] is a non-linear equalization that employs previous decisions to eliminate the ISI caused by previous symbols on the current symbol. It was first introduced by M. E. Austin in 1967, who introduced a decision-theory approach to solve the problem of digital communication over known dispersive channels. This work was the first to describe a method to utilize the information of past decisions to make corrections to current symbols and thereby cancel post-cursor ISI. Today the DFE is used extensively to combat ISI in different dispersive channels and finds many applications in high-speed communication systems.
A typical decision-feedback equalizer is shown in Fig. 3.8. Here we use one tap of DFE as an example. The signal,ˆy , is the summation of received data and the D previous decision bit multiplied by a constant C1. The slicer is a decision-making circuit that compares yD and a reference Vref and then generates a binary signal. If yD
Chapter 3 Equalization Basis
Figure 3.8 Typical block diagram of DFE with one tap.
≧Vref, the output of slicer is ONE and it is ZERO when yD < Vref.
Now we will explain why the DFE can cancel the post-cursor ISI. We can write the transfer function for the simple one-tap DFE as
ˆD[ ] [ ] 1sgn( [ˆD 1])
y n = y n +C y n− (3.14) where y[n] is the signal level being received, ˆ [ ]y nD is the DFE corrected signal, C1 is the first DFE feedback tap weight, and sgn() produces a 1 for ˆ [y nD − ≧ 0 and -1 1]
otherwise. For the case of zero-error detection, EQ. (3.14) can be analyzed in a linear sense by replacing sgn ( ˆ [y nD − ) with the transmitted data x[n-1] and y[n] with the 1]
convolution of sequence x[n] with the channel response h[n]. The resulting difference equation and corresponding z transform are
1 To illustrate the operation of the DFE, assume a low-pass channel-response function
( ) [0] [1] 1
H z =h +h z− (3.16) with h[0] normalized to 1 and h[1] positive, resulting in reduced gain at high frequencies. In this case
1 1
ˆ ( )D ( )(1 [1] 1 )
Y z =X z +h z− +C z− (3.17) To cancel the post-cursor ISI, C1 is set to the value –h[1], which realizes a fully
Chapter 3 Equalization Basis
equalized channel Yˆ ( )D z =X z( ).
The biggest bottleneck of the simple DFE is its operation speed. Before the next bit comes, the feedback signal must be ready at the input of adder. This implies that the total propagation delay consumed by the slicer, the flip-flop, multiplier, setup time of flip-flop and some operating margin, needs to be less than one symbol period. This loop is a critical path in the DFE. As data rate increases to several multi-Gbps, it seems that the critical path delay can not meet the stringent timing constraint. For example, if the data rate is 10 Gb/s, the total latency of the critical path must be less than 100 ps. Unless the propagation delay of silicon processing elements improves greatly and overcomes this difficulty, high data rates will limit the use of this direct type of DFE.
In order to overcome the feedback loop latency challenge imposed by the limitations of the clocked topology, designers have come up with some novel design techniques to implement multi-Gbps DFEs in standard CMOS. A common approach to reduce the critical path delay is to use a “look-ahead” architecture, also referred to as loop-unrolled DFE or speculative DFE [23]. The architecture is shown in Fig. 3.9.
The basic concept behind this technique is that for a NRZ signal, every symbol is a 1 or a -1. The two threshold value V1 and V0 are the first tap weight, C1, multiplied by 1 and -1, respectively. Instead of feeding back the slicer decision for the first tap, a look-ahead DFE makes two decisions with two slicers where each slicer assumes the previous bit is a -1 and 1. The received data value is selected from these two slicer outputs based on the previous data value with a multiplexer. The nthdecision yD can be expressed as
Chapter 3 Equalization Basis
Figure 3.9 Look-ahead one-tap DFE.
1 0
[ 1] [ 1] [ 2] [ 1] [ 2]
D D D D D
y n− = y n− y n− +y n− y n− (3.19) Substituting EQ. (3.19) in EQ. (3.18), an can be expressed as
( )
implies that the critical timing path has been extended from Tbit to 2Tbit, where Tbit is one bit period. The extra delay available can be used to reduce the clock rate to half the data rate. The half-rate architecture of look-ahead DFE is shown in Fig. 3.10.Obviously, this approach has the advantage of lower clock rate but the hardware and area increase tremendously.
The look-ahead technique is typically limited to only one tap because of an exponential increase in the number of slicers with the number of taps. As a result, the second and higher order taps of the DFE do not apply look-ahead and are often fed back directly. We call this dynamic feedback technique [9][10]. A lot of creative
Chapter 3 Equalization Basis
Figure 3.10 Half-rate look-ahead DFE.
inventions about dealing the timing constraint, higher data rates and lower power consumption, have been proposed [24][25].
The problem of noise enhancement can be completely eliminated by using DFE since the DFE just utilizes the previous decision to do the equalization without boosting the high-frequency noise. There are two design issues with the DFE design.
First, the effectiveness of ISI cancellation is based on the assumption that all previous decisions are correct and therefore if decisions are incorrect, the ISI will be worse.
The problem is referred to as error propagation. However, in the case of serial-links with required BER < 10-12, error propagation does not degrade the performance.
Second, the DFE can cancel only post-cursor ISI. If the channel response is very severe, including pre- and post-cursor ISI, a separate FFE is required.
Chapter 3 Equalization Basis