Behavioral Simulation Results

Section 4.1 and 4.2 have described our DT-ADFE architecture and the “delayed sign-sign LMS with hopping update scheme”. In this section, we will simulate our equalizer by MATLAB under different conditions and investigate the performance from the behavioral results.

In all the simulations, a 10 Gb/s pseudo random binary sequence (PRBS) is generated and passed through the channel presented in Section 2.3. We choose the step size μ as 2^-7 that is small enough to make the sign-sign LMS algorithm converge.

Our simulations take three different conditions into consideration: hopping update scheme, hopping update scheme with 3-bit Up/Down counter, and hopping update scheme with 4-bit Up/Down counter. The hopping update scheme uses the operation frequency of 1, 1/4, 1/8, 1/16 of the data rate. Fig. 4.4 shows the coefficients and the amount of error with time of the equalizer with data rate updating. The error is defined as the value difference between slicer input and slicer output. From the plot of the coefficients, we can observe the convergence situation of equalizer weights. Fig.

4.5 shows the simulation results with quarter of data rate adaptation. The results of hopping with eighth and sixteenth of data rate adaptation are shown in Fig. 4.6 and Fig. 4.7, respectively.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

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Figure 4.4 (a) DFE coefficients and (b) error of hopping update scheme with data rate.

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Figure 4.5 (a) DFE coefficients and (b) error of hopping update scheme with 1/4 data rate.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

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Figure 4.6 (a) DFE coefficients and (b) error of hopping update scheme with 1/8 data rate.

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Figure 4.7 (a) DFE coefficients and (b) error of hopping update scheme with 1/16 data rate.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

From Fig. 4.4 to Fig. 4.7, we can find the convergence time increases with the reduction of the adaptation frequency. This phenomenon is what we expected in section 4.2. Table 4.1 lists the mean square errors (MSE) and convergence times of these four different update frequencies. It is very interesting that MSE increases with lower adaptation frequency as the convergence time does. Therefore, lower power consumption is at the cost of higher MSE and slower convergence time.

Table 4.1 MSE and convergence time for hopping update scheme at four different frequencies.

adaptation frequency (data rate) 1 1/4 1/8 1/16

MSE 0.01232 0.01252 0.01263 0.01268

Convergence time (bit) 300 1450 1850 2230

Fig. 4.8 shows the histogram of error of hopping update scheme with data rate when coefficients converge. If the samples are many enough, the histogram of error will be like Gaussian distribution. The standard deviation of error is 0.111. Hence, the seven times of standard deviation is 0.777. Since 0.777 is less than 1, the BER of the equalizer is less than 10^-12 according to Table 2.1.

Figure 4.8 Histogram of error.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

We have seen the results about the effect of hopping update scheme. Now, we add an Up/Down counter in the adaptation block to observe the performance. In simulation, we simulate the behavior of an Up/Down counter. For example, if the Up/Down counter has 3 bits, the positive full-scale is 3 and the negative full-scale is -3. When the output of counter is 3 and the next product of error sign and decision sign comes a 1, the counter overflows and returns to 0, and the coefficients update.

Also, when the output of counter is -3 and the next product of error sign and decision sign comes a -1, the counter underflows and returns to 0, and the coefficients update.

If the bit counts of the Up/Down counter is 4-bit, then the maximum is 7 and minimum is -7 and the behavior is the same as a 3-bit counter. From Fig. 4.9 to Fig.

4.12, the simulation results of 3-bit Up/Down counter with hopping update scheme at 1, 1/4, 1/8, 1/16 date rate are shown, respectively. We list the MSE and convergence time of these four cases in Table 4.2.

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Figure 4.9 (a) DFE coefficients and (b) error of hopping update scheme with data rate and 3-bit up/down counter.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

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Figure 4.10 (a) DFE coefficients and (b) error of hopping update scheme with 1/4 data rate and 3-bit up/down counter.

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Figure 4.11 (a) DFE coefficients and (b) error of hopping update scheme with 1/8 data rate and 3-bit up/down counter.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

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Figure 4.12 (a) DFE coefficients and (b) error of hopping update scheme with 1/16 data rate and 3-bit up/down counter.

Table 4.2 MSE and convergence time for 3-bit Up/Down counter with hopping update scheme at four different frequencies.

adaptation frequency (data rate) 1 1/4 1/8 1/16

MSE 0.01143 0.01140 0.01121 0.01132

Convergence time (bit) 650 2300 4130 8200

We can find that the convergence times are longer than those of only hopping update scheme. This is easy to be anticipated. Moreover, the MSE is lower as compared with that of only hopping update scheme. Because when the coefficients converge, they will be stable with the same value at most of the time, the variance of error changes steadily and the MSE reduces. However, with Up/Down counter the MSE does not increase as adaptation frequency decreases. Since the coefficients converge, the Up/Down counter is like a barrier to keep the coefficients stable, and the adaptation frequency becomes less impact to influence the change of coefficients.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

In other words, Up/Down counter dominates the magnitude of MSE. Lower MSE implies bigger eye diagram and lower BER. From this point of view, the addition of Up/Down counter is beneficial to coefficient adaptation circuit design.

The coefficients and error results of equalizer with 4-bit Up/Down counter and hopping update scheme at four different updating frequencies are shown in Fig. 4.13 to Fig. 4.16. MSE and convergence time of these four cases are listed in Table 4.3.

Again, we can find the convergence times are longer than those in Table 4.2, but the MSE is lower than that of with 3-bit Up/Down counter. The convergence times are all smaller than 65536 bits time of USB 3.0 specification. The information provides a good guideline for us to choose the suitable type of adaptation algorithms when doing performance trade-off. For the hopping coefficients update scheme, we can reduce the power consumption of coefficients update block. For Up/Down counter, we can obtain the advantage of lower MSE and alleviate the difficult design of charge pump.

On this basis, we will implement our DT-ADFE in the next chapter.

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Figure 4.13 (a) DFE coefficients and (b) error of hopping update scheme with data rate and 4-bit up/down counter.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

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Figure 4.14 (a) DFE coefficients and (b) error of hopping update scheme with 1/4 data rate and 4-bit up/down counter.

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Figure 4.15 (a) DFE coefficients and (b) error of hopping update scheme with 1/8 data rate and 4-bit up/down counter.

Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer

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Figure 4.16 (a) DFE coefficients and (b) error of hopping update scheme with 1/16 data rate and 4-bit up/down counter.

Table 4.3 MSE and convergence time for 4-bit Up/Down counter with hopping update scheme at four different frequencies.

adaptation frequency (data rate) 1 1/4 1/8 1/16

MSE 0.01115 0.01112 0.01097 0.01100

Convergence time (bit) 1300 5100 9720 18100