Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer
4.2 Mixed-Signal Integrator with Hopping Update Scheme
4.2.1 Hopping Coefficients Update Scheme
Section 4.1 has introduced overall blocks in our DT-ADFE architecture. Among these blocks, the performance of sign-sign LMS engine has the dominant effect to the quality of the DT-ADFE. Thus, if we can come up with some novel methods to improve one aspect of the performance metrics, it will make a difference in our equalizer design.
The equation of power consumed by a digital circuit can be expressed as:
2
P= ⋅C VDD ⋅ ⋅ (4.1) f pt
where C is the output loading capacitance, VDD is the voltage of power supply, f is the circuit operation frequency, pt is the probability of switching activity.
Typical adaptive mechanism for adaptive equalizer is to update the weights of coefficients per bit of data. This method takes each information into consideration and the coefficients of equalizer converge to stable state in a very short time. However, this means the adaptation circuit in the equalizer needs to operate at a frequency as high as the data rate. With the increasing of data rate, this mechanism will produce a large power consumption for adaptation circuit.
Obviously, we can save power consumption by slowing down the clock rate in
Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer
the adaptation circuit. In fact, the transmitted data are often independent between each other and we do not need to worry about losing the correlation information if we ignore some bits. From the theory of sign-sign LMS algorithm, we know that the convergence is only dependent on the step size μ. Therefore, we can choose some bits from the received data as a new received sequence for finding the characteristics of the channel. For example, we can choose the bits with time indexes that are equal to a multiple of eight as a new sequence to update the coefficients of DFE. This method is called “hopping” [28].
Although the convergence time of coefficients will increase when we use the hopping scheme, this is not a problem in high-speed transmission. In the specification of USB 3.0, there are 65536 bits required for the training sequence. Thus, we can use hopping update scheme with the convergence time less than the required condition.
Since hopping scheme can save power in the adaptation circuit, it is worth to do in our equalizer design.
4.2.2 Mixed-Signal Integrator
Section 3.3 has talked about sign-sign LMS algorithm. The sign-sign LMS coefficient updating algorithm is given by:
( ) ( )
[ 1] [ ] [ ] [ ]
k k D
C n+ =C n + ⋅μ sign e n ⋅sign y n−k (4.2) where Ck [n+1] represents kth coefficient at (n+1) update, μ is the step size, e[n] is the error in the equalizer output, and yD is the decision of ADFE slicer output. Since the product of sign e n
(
[ ])
×sign y n k(
D[ − ])
is always a logical value 1 or -1, the coefficients always add a “μ” or subtract a “μ”. From the view of circuit design, the operation is like to count up or count down and sends the information to a mechanismChapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer
for transferring it into a relative analog value which is corresponding to the step size μ.
Obviously, we need a counter that could count up and count down. We also need a circuit that could receive the information from the counter and then generate a voltage (or current) represents the coefficient. In fact, the implementation of sign-sign LMS algorithm is equivalent to a discrete-time integrator. Fig. 4.2 shows the equivalent discrete-time integrators [29]. In a traditional mixed-signal DFE implementation, a
Figure 4.2 Discrete-time integrators, (a) n-bit counter and m-bit DAC. (b) cascaded counters and m-bit DAC. (c) k-bit counter and analog integrator.
n-bit Up/Down counter followed by a m-bit DAC is used to build the integrator, where n>m, as shown in Fig. 4.2(a). The number of n is usually large such as 10 and the number of m is the most significant bits of n. This arrangement is set to realize the small value of step size μ while ease the difficulty of DAC design. The integer input is a binary signal with value ±1. This signal determines whether the counter should increment or decrement its current value according to EQ. (4.2). The m-bit DAC generates an output voltage (or current) based on the m most significant bits of the n-bit counter. This output voltage is the analog coefficient Ck[n+1]. The n-bit counter can be realized as a cascade of two smaller counters: a k-bit Up/Down counter followed a m-bit Up/Down counter, where k+m=n, as shown in Fig. 4.2(b). For example, n is equal to 10, k is equal to 4 and m is equal to 6. When the 4-bit pre-counter overflows, it counts from positive full-scale (+7) to 0 and outputs Carry
Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer
=1, causing the 6-bit counter to increment by 1. When it underflows, it counts from negative full-scale (-7) to 0 and outputs Borrow =1, causing the 6-bit counter to decrement by 1. Otherwise, the 6-bit counter remains unchanged. The advantage of Fig. 4.2(b) over Fig. 4.2(a) is that the input of DAC does not need to change often since the k-bit up/down counter will reset to 0 when it overflows or underflows. In an adaptive equalizer system, we hope the coefficients will be stable when the coefficients converge. When the step size is small enough, the stable coefficients will lead to low MSE and BER. Section 4.3 will show the simulation results.
If there is an analog discrete-time integrator that could replace the m-bit counter and m-bit DAC, the power dissipation and die area will be greatly saved, as shown in Fig. 4.2(c).
An smart implementation of this analog integrator is a charge pump. Fig. 4.3 shows the mixed-signal integrator which consists of a 4-bit Up/Down counter and a charge pump. Coefficient Ck[n+1] changes when either switch closes, as controlled by Carry and Borrow. When Carry and Borrow are both low, loading capacitor CL keeps the coefficient constant. An equation about step size μ and charge pump voltage is
Figure 4.3 Mixed-signal integrator.
Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer
L
I t
V C
μ ∝ Δ = ⋅ Δ (4.3) where I is the average current of charge pump, Δt is a turn-on time. If the charge current matches the discharge current, we could combine EQ. (4.2) and EQ. (4.3) into EQ. (4.4):
where the result of (Carry-Borrow) can be either +1, -1, or 0. In fact, having the Up/Down counter, we can alleviate the stringent design of charge pump and a precise voltage at the charge pump output is not a requirement. Since an adaptive equalizer will monitor the error, if there is a small current offset in the charge pump, the equalizer system will automatically correct the accumulation of current offset in a long run. When the counter reaches its maximum value (+7) or minimum value (-7), the counter is reset to its mid-scale value, 0. As a result, the charge pump will spend most of the time with both switches open. Either the Up or Down switch can be enabled at most once every 7 clock cycles. Hence, the problem of current mismatch is not a big issue in charge pump design.
In high-speed circuit implementation, it is difficult to update the coefficients of the equalizer as the same as symbol rate. If we add the hopping coefficients update scheme to the mixed-signal integrator, sign-sign LMS algorithm will be replaced by delayed sign-sign LMS algorithm. The delay sign-sign LMS algorithm is given by
( ) ( )
[ 1] [ ] [ ] [ ]
k k D
C n+ =C n + ⋅μ sign e n−D ⋅sign y n− −k D (4.5) where D is the number of delay bits time. Since hopping scheme slows down the clock rate in the adaptation circuit, a sequence to adapt the coefficients is per D bits of original received data. Therefore, the current coefficient is adapted by the error and decision terms with D bits before. We call this method as “delayed sign-sign LMS with hopping update scheme.” We will employ this algorithm in our proposed
Chapter 4 Discrete-Time Adaptive Decision-Feedback Equalizer
DT-ADFE design.