5.1 Conclusions
An implementation of continuous-time equalizer and an analysis of discrete-time DFE are presented in this thesis. For the continuous-discrete-time equalizer, we propose a 6-Gb/s continuous-time equalizer with level-shifter using 90 nm CMOS technology. It provide a light weight and stable solution to compensate a severe channel loss. The area of level-shifter and equalizer stage is 0.053× 0.053 mm2. The power consumption of these two blocks and first stage of buffer is 3.79mW.
From the simulation results, the proposed equalizer can compensate the channel loss of 13.87dB under the 6 GHz data rate. The circuit is implemented in UMC 1P9M 90 nm 1.0 V Regular-Vt CMOS technology. The total chip area including pads is 0.49× 0.49 mm2, and power consumption including buffer stage is 78.83 mW.
For the discrete-time DFE, we explore two mechanisms that are based on power saving and area reducing strategy. The used two parallel data paths for half-rate operation architecture [8] deals with 10-Gb/s input signal. It has one-bit speculation and 5 taps to cancel the ISI effects. We build the mathematical model based on this architecture in MATLAB. The adaptation of DFE coefficients uses sign-sign LMS algorithm. For the hopping update scheme, the power consump-tion of coefficients update block can be reduced. The operaconsump-tion frequency of the update block is equal to the data frequency divides by how many bits the system updates the coefficients once. And we can save the power for the same ratio.
For ping-pong update scheme, two data paths calculate the sign of error under different conditions. The ping-pong update scheme saves one comparator that
calculates the sign of error in each data path. For these two update schemes, we observe the coefficients update and error amount with time. We can get the guideline of setup parameters in design under some system sepcifications espe-cially the time for DFE coefficients convergence. The simulation of combination of the two strategies is also presented.
5.2 Future Works
Equalizers becomes more and more important in communication system while the data rate is increasing. Many new techniques and designs are being proposed. Both continuous-time equalizer and discrete-time equalizer proposed in this thesis have many potential improvements. First, we may add the adap-tion mechanism into our proposed continuous-time equalizer. With adaptaadap-tion mechanism, the proposed equalizer will has a little flexibility for time-variation of channel characteristic. For the discrete-time equalizer, we may consider the adaptation of coefficients update frequency. By this method, we may find the op-timal solution for trade-off between power saving and convergence time of DFE coefficients. Finally, while the data rate keeps increasing, the parallel data paths may increase. How to take use of the property of data dependent coefficients update scheme will be a good issue for saving more hardware.
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