Theory of Equalizer
2.2 Concepts of Equalizers
Equalization is a kind of signal processing. The equalizer deals with the data received from the channel output and then transfers the equalized data to the circuit after it. A common classification of equalizer are continuous-time equalizers [2,3] and discrete-time equalizers [8,13]. The basis of the classification is the method of handling the received data. They do the equalization from different point of view. In this section, we will give a brief introduction of these two categories.
2.2.1 Continuous-Time Equalizers
The continuous-time equalizers (CT-EQ) do equalization without the timing information. The signal dealt with by continuous-time equalizer is not digitized.
Therefore, the circuit belongs to analog domain. Due to the input data is con-tinuous, we can understand the continuous-time equalizer from compensation in frequency domain just like the explanation in the previous section.
However, any circuit has poles and zeros itself. That means to reach infinite high gain at the infinite high frequency is impossible. The frequency response of equalizer is never like what we plot in Fig. 2.1. Gain amount of frequency response will fall after an limited frequency range.
The principle of continuous-time equalizer is to produce an band-pass like
frequency response to reach the equalization function. Fig. 2.3 illustrates the idea of band-pass like frequency response. In this figure, we use piece-wise to sketch a roughly Bode plot.
Figure 2.3: Frequency Response of continuous-time equalizers
First, we assume that there is a zero at a relative low frequency in the equalizer circuit. By the rule of plotting Bode plot, we know that the frequency response will increase in 20dB/dec when there is a zero. The value of gain starts to rise with the frequency increases until reaching frequency of the first pole.
Because a pole will let frequency response decrease in 20dB/dec, the effect of zero is canceled by the lowest frequency pole. As the frequency keep increasing, the frequency will decrease dramatically due to dominate pole which is introduced by the circuit itself.
By such arrangement of poles and zeros, we can get a gain pulse in frequency response. Therefore, to allocate the first pole and first zero at proper frequency can move the gain pulse to the band we focus on. Although the effective response is not flat through the whole frequency, but the equalizer extends the flat part toward system data transmission frequency. In any data transmission system, the specification defines the transmission frequency used in the system. Therefore,
we do not need to compensate the response at the frequency that exceeds the frequency defined in the specification.
If the channel loss is severe, the response of equalizer will need a high gain pulse. One way is to suppress the low frequency gain while keeping the peak gain value. This strategy do not make sense because the low frequency signal suffers too many attenuation. The other way is to push up the peak gain value while keeping the low frequency gain. From Fig. 2.3 we can know that slope of rising response is a constant, +20dB/dec, if there is only one zero. Assume that the numbers of pole and zero do not change. If we push the first pole toward high frequency, the rising trend will stop later. And the response of equalizer will get a high gain pulse.
In summary, the advantage of continuous-time equalizers is having relative simple architecture. Therefore, they have small area and own a good equalization ability. For a well-known and time-invariant channel, the architecture of fixed fre-quency of poles and zeros can provide a stable performance. On the contrary, because continuous-time equalizers handle the equalization function in frequency domain, the adaptive solution is more difficult than discrete-time equalizer. More-over, a little change in the location of poles and zeros due to process variation will affect total response dramatically.
2.2.2 Discrete-Time Equalizers
Discrete-time signal processing is for signals that are defined only at discrete points in time. The processing includes concept of timing index and the order of data becomes a key parameter in operation. Discrete-time equalizer has the same idea of equalizing signal in discrete data points. This category of equalizers handle their operation from the view of cancelling intersymbol-interference (ISI).
Assume that the impulse response of channel is h(t) and the transmitted
signal sequence is x(t), and the signal in the channel output, y(t), is y(t) = x(t)∗ h(t). The data received at timing index n can be written as
y(n) = x(n)h(n) + X
∞m=−∞
m6=0
x(m)h(n − m) = x(n)h(n) + ISI (2.10)
the ISI term is the sum of all the ISI contributed by past and future bits. Although an ideal pulse will be spread out causing ISI to the neighbor bits, the value of spread out ISI data is not obvious for the timing index far from it. The equalizer just needs to cancel the ISI terms that are close to the current timing index.
A finite impulse response (FIR) filter can accomplish this operation. To cover the finite length of past data and future data, the dominate effect of ISI can be removed. The equalizer output can get the data that is near equal to the original data in the transmitter side.
The discrete-time equalizer has a sampler to get discrete time data per sam-ple period. After the samsam-pler samsam-ples the data from the channel output, the discrete data will be passed to the later stage of circuit. Due to the data is discrete, the implementation of the later stage of circuit can be implemented in digital or in analog. Fig. 2.4 shows the circuit architecture of two types of circuit.
The discrete-time digital equalizer (Digital-EQ) shown in Fig. 2.4(a) is also called the digital equalizer. It owns a analog-to-digital converter (ADC) to digitize the analog signal. But when a transmission system needs high resolution and operates at high frequency, the design of ADC will face a huge challenge. On the other hands, the discrete-time analog equalizer [13,14] (DT-EQ) shown in Fig. 2.4(b) will be a proper solution in the high speed application.
To make the sampler work properly, discrete-time equalizer needs an accurate clock to provide correct sampling. The clock source will need the cooperation of clock and data recovery (CDR) circuit. In the total system consideration, the CDR circuit must operate on the raw data first. Another issue about the clock is jitter. In a system that the jitter problem is severe, the effectiveness
(a)
(b)
Figure 2.4: Two types of discrete-time equalizers, z−1 is the register. (a) Discrete-time digital equalizer. (b) Discrete-time analog equalizer.
of equalization will be reduced. Because discrete-time signal processing is for signals that are defined only at discrete points in time, we can arrange these data to separated data paths without losing any information. By paralleling several data path, the circuit can slow down its operation frequency. With the increase of data rate, this is really a good news for equalizer design.
Finally, we give a short conclusion about each type of equalizer in Table 2.2.
Table 2.2: Characteristics of CT-EQ, DT-EQ and Digital-EQ
Type of Equalizer Characteristics
CT-EQ
• Simple architecture
• Adaptive method is quite difficult
• Fixed pole and zero location
DT-EQ
• Clock recovery is necessary
• Easy for adaptation
Digital-EQ
• Circuit is all digital
• Easy for adaptation
• High resolution and speed ADC is required
• Large area and power