Hopping coefficients update scheme

The power consumes by a circuit can be expressed as the following equation

P = C · V DD

· f · p

where,

C: the output loading capacitance, V DD: the voltage of power supply, f : the circuit operation frequency.

p_t: the probability of switching activity.

In this subsection, we analyze the equalizer performance based on the power reduction consideration.

(a)

(b)

Figure 4.6: Data arrangement of (a)half-rate architecture, (b)quarter-rate ar-chitecture

Typical adaptive mechanism for adaptive equalizer is to update the weights of equalizer per bit of data. This method takes every information into consideration and converges the circuit toward stable state within the shortest time in the begining of the transmission. However, from the view of hardware operation, updating the weights of equalizer per bit data means the adaptation circuit in the equalizer needs operating at data rate. With the increasing of data rate, this mechanism will introduce a large power consumption for adaptation circuit once the system is in the stable conditions.

By parallelling data paths, the operation frequency of each data path has been slowed down. The only part that operates at full speed is the weights adap-tation block. Obviously, an effective solution of reducing the power consumption

is to find some strategy for the weights adaptation block.

In fact, updating the weights of equalizer per bit of data is too greedy. The transmitted data is often independent between each other and we do not need to worry about losing the correlation information if we ignore some bits. From the theory of sign LMS algorithm, we know that the convergence of the sign-sign LMS algorithm only depend on the step size µ. Therefore, we can choose some bits from the received sequence as a new received sequence for finding the characteristics of the channel. On other words, we can use the new received sequence to update these coefficients of the DFE. From the circuit operation of view, this method is to update the coefficients of DFE every perticular number of bits. For example, we choose the bits with time indexes that are equal to a multiple of eight as a new sequence to update the coefficients of DFE. In circuit operation, this mechanism is equal to update the coefficients of DFE per eight bits of reveived data. That means we slow down the operation frequency of coefficients updating block to eighth of data tranmission frequency.

Although the time of coefficients convergence time will increase in the be-gining of transmission time if we choose these bits for a long period, we can find a maximum rate to slow down the coefficients update frequency within the re-quirement of convergence time. Our simulation will take three coefficients update frequencies: per bit, per four bits and per sixteen bits. By these three simulations, we can observe the increase of convergence time while the coefficients update fre-quency decreases. And we can find the guideline of setup the maximum rate of slowing down the coeffecients update frequency in a DFE system.

Our simulation takes three conditions into consideration: updating the co-efficients, or called weights, per bit, per four bits, per sixteen bits. That is equivalent to divide the operation frequency by 1, by 4, and by 16 respectively.

Fig. 4.7 shows the change of coefficients, and amount of error with time of the equalizer under data-rate updating. The error is defined as the value difference between slicer input and slicer output. From the weights change plot we can

observe the convergence situation of equalizer weights. And the error plot can reflect what the adaptation algorithm wants to minimize. Fig. 4.8 shows the simulation results under quarter of data-rate adaptation. And the result under sixteenth data-rate adaptation is shown in Fig. 4.9

(a)

(b)

Figure 4.7: Hopping update scheme under data-rate. (a) DFE Coefficients, (b) error.

(a)

(b)

Figure 4.8: Hopping update scheme under 1/4 data-rate. (a) DFE Coefficients, (b) error.

(a)

(b)

Figure 4.9: Hopping update scheme under 1/16 data-rate. (a) DFE Coefficients, (b) error.

From Fig. 4.7 to Fig. 4.9, we can find the convergence time increases with reducing of adaptation frequency. That means slowing down the adaptation fre-quency indeed delay the convergence duration. We calculate the mean of absolute error value (Eave) when the coefficients are convergence. From the figure of error amount, we can measure the coefficients convergence time (Tcon) when the error reduces into the range of ±0.5. The reason of choosing ±0.5 is that the tranmit-ted pattern is ±1, and the decision threshold is zero. We list out the Eave and Tcon of these three simulations as shown in Fig. 4.7 to Fig. 4.9 in Table 4.1.

Table 4.1: Eave and Tcon for hopping update scheme under three different data rate

adaptation frequency (data-rate) 1 1/4 1/16 mean of absolute error value (Eave) 0.2419 0.2452 0.2441

Convergence time (bit) (Tcon) 2600 4450 17450

From Table 4.1, the three cases have roughly the same Eave when the coef-ficients converge. But in the performance of convergence time, the case of 1/16 data-rate adaptation has Tcon that is triple for the case of data-rate adaptation.

In these simulation results the coefficients are converged, however, the case of 1/16 data-rate adaption has 15000 bit time. And from the error plot we can find that the Eave is toward the nagetive side when the coefficients are not converged.

The reason is that the update frequency of coefficients decreases. So that the data are equalized to plus or minus direction for a long time. And the time is long enough to observation in the plot.

From these simulation results, we can derive a concept of dynamic coef-ficients update scheme. We can choose the slowest data rate for the hopping update scheme. Therefore, the power consumption can be minimized during the coefficients convergence time. Because the characteristic of channel varies slowly that may be the order of millisecond, the DFE does not need to update the coef-ficients frequently. On the other words, we can increase the period of coefficient update after the coefficients are converged to save more power consumption.