Equalizer stage

Analog equalizers as introduction in 2.2.1, they do equalization operation by allocating a zero in the low frequency to produce a gain pulse in the frequency response. The equalization filter in our equalizer stage use the topology that introduces a zero in the source terminal of common-source amplifier as shown in Fig. 3.7 [3].

M1 and M2 are as the active load in the circuit. M3 and M4 play the main roles for the function of amplification. M5 and M6 are the current source part.

The resister Rm and capacitor C are the key elements to introduce the zero.

Figure 3.7: Circuit diagram of one equalizer stage

We will derive the transfer function of this equalizer stage by using the half circuit scheme. The first part is to find the effective ground point in the circuit.

We assume the characteristics of M1, M3, and M5 are the same with M2, M4, and M6. We model the current source as two resistors with r_o of the two transistors, and model the active load, M1 and M2 as two simple resistor load, Rp. The circuit diagram is shown in Fig. 3.8(a).

Under the assumption of previous paragraph, the resistance of r_o5 and r_o6 should be the same. This means the source voltage of M3 and M4 are the same, too. Then, the circuit can be further simplified as shown Fig. 3.8(b). We let the current in the differential small-signal equivalent circuit is i, the following can be derived

i = (v

− v

) · gm

= −(v

− v

) · gm

⇒ (v

+ v

) = (v

+ v

) ∵ gm

= gm

∵ v

= v

∴ v

= −v

The equation v_s3 =−vs4 says that the voltage in the two sides of the resistor and capacitor is sysmetric to zero as shown in Fig. 3.8(b). If we split the resister into two serial segments which have the same resistance, the voltage in the middle point, G, of the two segments is equivalent ground point. The same manner can also be applied to the capacitor as shown in Fig. 3.8(c).

Finally, we can get the half circuit of the equalizer stage as shown in Fig. 3.9.

Based on the half circuit, the transfer function is derived as follow:

v

v

= −gm

· R

Rm

2

//

= −gm

· 2R

R

· (1 + sCR

) (3.1)

where R_p is the effective resistance of M1. From the tranfer equation, we can find there is a zero that is used to produce the gain pulse in the frequency response.

The final version of the equalization stage is shown in Fig. 3.10. We replace the resistor, R_m, with a NMOS which gate is connected to VDD. Moreover, in order to improve the PMOS ability of pulling the output voltage up, each PMOS for active load is shunt with another PMOS which gate is connected to the input respectively as a negative resistor. The bias voltage of current source part uses the same source as the level-shifter uses.

The equalizer block is composed of two cascade stages. The margin of in-creasing frequency between the first zero and the first pole is limited. So, we usually surpress a little low-frequency gain to get a sharp gain pulse in the fre-quency response. If there is only one stage, the low-frefre-quency gain will be surpress too low while pushing the gain pulse. If we use two cascade stages, we can get a sharp gain pulse in the final output while surpressing the low-frequency gain as less as possible.

Fig. 3.11 shows the frequency response of the two equalization stages and the total frequency response. Because the two stages suffer different input and output loading, the two stage will have different zeros and poles frequency. In the first equalization stage, the frequency of first zero is at about 755 MHz, and

(a) (b)

(c)

Figure 3.8: Small signal circuit of equalizer. (a) Simplified equivalent small-signal model. (b) Further simplified equivalent small-small-signal model. (c) Virtual ground in equivalent small-signal model.

the stage has a real zero at about 1.95 GHz and a pair of complex zero at about 2.6 GHz. On the other hand, the first stage has two pair of complex poles at about 1.41 GHz and 2.96 GHz. There is also a real pole at 2.39 GHz. Therefore, we can observe that the frequency response of first equalization stage decreases dramatically after the gain peak frequency.

In the second equalization stage, the frequencies of first two zeros are at about 790 MHz and 3.89 GHz. While the frequencies of first two poles are at about 2 GHz and 3.9 GHz. The second stage owns the first pole and the first

Figure 3.9: Half circuit of equalizers.

Figure 3.10: Final circuit of equalization stage

zero at the frequency higher than the first stage owns. We push the gain pulse of the second stage to higher frequency than the gain pulse of the first stage.

Moreover, by minimizing the gate capacitance of the first buffer stage, loading in the output of the second equalization stage is dominated by the stage itself.

We can push the frequency of poles to higher frequency. So that the trend of decreasing in the second stage response will not be so dramatically as the first

Gain (dB)

Figure 3.11: Frequency dependence of gain in each equalization stage and total response.

stage. These two methods let the second stage provide more compensation ability at high frequency than the first stage provides as shown in Fig. 3.11.

In Fig. 3.11 we can also find that the equalizer contributes nagative gain value under the frequency about 400 MHz. As our architecture decribed in Section 3.2, the low-frequency gain is dominated by the level-shifter stage. The equalizer introduces the gain boosting in high frequency, and the low-frequency gain will be provided by the level-shifter. Fig. 3.12 shows the response of the equalizer stage and the total response of level-shifter and equalizer stage. The level-shifter amplifies the low-frequency gain about 9.5 dB, and the effect of amplification also extend to the frequency of gain pulse. On the other words, the level-shifter not only provides the gain in low frequency but also contributes amplification in high frequency. However, the difference between equalizers and amplifiers is that the equalizers can cancel the ISI components in signal while amlifiers just amplify the

signal without any correction mechanism. The level-shifter just lifts the response up through a limited frequency, it can not extend the flatten response towards high frequency. The gain pulse used to flat the response is still provieded by the equalizer stage.

Figure 3.12: Response of equalizer stage and combination of level-shifter and equalizer.

The final frequency response in the equalizer output is shown in Fig. 3.13.

Our proposed equalizer is under the 6GHz system. The clock rate is 3GHz. In Fig. 3.13, the channel response is -25.35dB at 3GHz. After compensation by our equalizer, the response at 3GHz is -11.48dB. The proposed equalizer recovers 13.87dB channel loss.

In Fig. 3.14, we show the group delay in the equalizer output. We know that the group delay is the differential of the phase response. Therefore, for a linear phase response system, the group delay should be a constant. In Fig. 3.14 we can observe that when the frequency is small than xxGHz, the group delay

Gain (dB)

Figure 3.13: Frequency response of channel output and equalizer output.

is almost a constant. That means the proposed equalizer does not introduce too much phase distortion.

However, the signal is used in time domain for system application. The effect of equalization can not be measured just in the frequency domain. Therefore, the performance in the time domain is most important because the meaning of equalizer is to corrent the signal distorted in the channel. The goal of our equalizer in time domain is to open the data amplitude to±300mV. The specification of the proposed system is to transmit data with±300mV, so that we need to recover the received data amplitude amplitude as much as possible. If the signal amplitude can not reach ±300mV, the buffer stage will amplify the signal to the goal.The signal in the output of equalizer stage is been equalized, even if the amplitude do not reach the specification. The buffer stage just amplifies the equalized signal amplitude to meet the requirment in specification.

We use the RLGC element in HSPICE to fit the reponse of a HDMI cable.

Group Delay (Sec)

Figure 3.14: Group delay in the equalizer output

We change the length of the channel model to get about the -25dB channel loss at the clock frequency 3GHz under 6GHz data rate. Base on this channel model, we apply psuedorandom bit sequence (PRBS) pattern to the channel input and observe the eye diagram of three points: channel output, equalizer output, and buffer output. The PRBS pattern is set to have ±300 mV swing with 6 Gbps and the length of the PRBS pattern is 1000 bits. Fig. 3.15 shows the eye diagram of pre-layout simulation. Fig. 3.15(a) shows the diagram of channel output. Due to the channel loss, the signal is hard to be distinguished. Fig. 3.15(b) shows that the equalizer opens the data eye to about ±280 mV. The peak-to-peak jitter of the eye at the equalizer output is 22.85 ps and the RMS jitter is 7.47 ps, and the jitter histogram is shown in Fig. 3.16(a). The equalized signal is further amplified by buffer stage to±300 mV swing, as shown in Fig. 3.15(c). At buffer output, the data eye has peak-to-peak jitter of 22.96 ps and RMS jitter is 7.51 ps, and the jitter histogram is shown in Fig. 3.16(b). The buffer stage introduces about 0.1 ps peak-to-peak jitter to the data eye. The design goal of

buffer is also to push the loadings including bounding line and connectors in the measurement environment. If we just need to amplify and shape the output eye to the specification, we do not need to design such a buffer stage that with large driving ability.

Amplitude (V)

Figure 3.15: Eye diagram of pre-layout simulation: (a) channel output. (b) equalizer output. (c) buffer output

(a)

(b)

Figure 3.16: Jitter histogram of pre-layout simulation: (a) equalizer output.

(b) buffer output