Chapter 1 Introduction
1.3 Dissertation Organization
Chapter two begins with an introduction to the theory and the experiments designed to explore dopant diffusion under mechanical stress. The implementation of the proposed stress-dependent diffusion model into the TCAD simulation tools, TSUPREM4 and MEDICI, is then presented. Three applications, stress dependent diffusion effect on the MOSFETs threshold voltage, stress dependent diffusion effect on the subthreshold leakage of the low dopant concentration well nMOSFET, and anisotropic diffusion under uniaxial strain are introduced in detail.
Chapter three discusses the influence of mechanical stress on the on-state behavior of the MOSFET. The change in structure of the energy-band, and the resulting impact on drive current for both n and pMOSFETs, is discussed. The implementation of a new model into SPICE that accounts for the mechanical stress effect is also proposed for the circuit design.
Chapter four first addresses the dopant scattering effect at well-mask edges on the modern MOSFETs by a designed wafer experiment. In-depth understanding is displayed using full process and device simulations of TCAD tools. Physic-based SPICE models is proposed and is validated with experimental data for better circuit simulation accuracies.
Finally, Chapter five offers a conclusion to the research, together with a summary of the accomplishments, and addresses future work to be extended to the
References
[1.1] International technology roadmap for semiconductors, 2005 edition, executive summary.
[1.2] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., Dec. 1999, pp. 827-830.
[1.3] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117-120.
[1.4] Y. M. Sheu, Kelvin Y. Y. Doong, C. H. Lee, M. J. Chen, and C. H. Diaz, “Study on STI mechanical stress induced variations on advanced CMOSFETs,” in Proc.
of ICMTS, Mar. 2003, pp. 205-208.
[1.5] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K.
Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc. of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
[1.6] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N.
Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design,” in IEDM Tech. Dig., Dec. 2000, pp. 247-250.
[1.7] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chen, B. C.
Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T.
Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., Dec. 2003, pp.
73-76.
[1.8] K. Rim, J, Chi, H. Chen, K.A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P.M. Mooney, D. Lacey, K. Koester, K.
Chan, D. Boyd, M. Ieong, and H.-S. Wong, “Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs,“ In VSLI Symp. Tech. Dig., Jun.
2002, pp. 98–99.
[1.9] J. Jung, S. Yu, M. L. Lee, J. L. Hoyt, E. A. Fitzgerald, and D. A. Antoniadis
“Mobility Enhancement in Dual-Channel P-MOSFETs,” IEEE Trans. Electron Devices, vol. 51, pp. 1424-1431, September 2004.
[1.10] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z.
Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y.
El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Trans.
Electron Devices, vol. 51, pp. 1790-1797, November 2004.
[1.11] K. W. Ang, K. J. Chui, V. Bliznetsov, A. Du, N. Balasubramanian, M. F. Li, G.
Samudra, and Y. C. Yeo, ” Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions,” in IEDM Tech. Dig., Dec. 2004, pp.
1069-1071.
[1.12] S. Tyagi, C. Auth, P. Bai, G. Curello, H. Deshpande, S. Gannavaram, O.
Golonzka, R. Heussner, R. James, C. Kenyon, S-H Lee, N. Lindert, M. Liu, R.
Nagisetty, S. Natarajan, C. Parker, J. Sebastian, B. Sell, S. Sivakumar, A. St Amour, K. Tone “An advanced low power, high performance, strained channel 65nm technology,” in IEDM Tech. Dig., Dec. 2005, pp. 245-248.
[1.13] J. Damiano, C. K. Subramanian, M. Gibson, Y.-S. Feng, L. Zeng, J. Sebek, E.
Deeters, C. Feng, T. McNelly, M. Blackwell, H. Nguyen, H.Tian, J. Scott, J.
Zaman, C. Honcik, M. Miscione, K. Cox, and J. D. Hayden, “Characterization and elimination of trench dislocations,” in VSLI Symp. Tech. Dig., Jun. 1998, pp.
212–213.
[1.14] T. K. Kim, D. H. Kim, J. K. Park, T. S. Park, Y. K. Park, H. J. Lee, K. Y. Lee, J. T.
Kong, J. W. Park, “Modeling of cumulative thermo-mechanical stress (CTMS) produced by the Shallow trench isolation process for. 1Gb. DRAM and beyond” in IEDM Tech. Dig., Dec. 1998, pp. 145-148.
[1.15] D. Ha, C. Cho, D. Shin, G. H. Koh, T. Y. Chung, and K. Kim, “Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices,” IEEE Trans. Electron Devices, vol. 46, pp. 940-946, May 1999.
[1.16] J. W. Sleight, C. Lin, and G. J. Grula, “Stress Induced Defects and Transistor Leakage for Shallow Trench Isolated SOI,” IEEE Electron Devices Lett., vol. 20, pp. 248-250, Dec. 1999.
[1.17] Z. K. Lee, M. B. McIlrath, and D. A. Antoniadis, “Two-dimensional doping profile characterization of MOSFET’s by inverse modeling using I-V
characteristics in the subthreshold region,” IEEE Trans. Electron Devices, vol. 46, pp. 1640-1649, August 1999.
[1.18] G. Dorda, “Peizoresistance in quantized conduction bands in silicon inversion layers,” J. Appl. Phys., vol. 42, pp. 2053-2060, April 1971.
[1.19] J. Welser, J. L. Hoyt, and J. F. Gibbons, “Electron mobility enhancement in strained-Si N-type metal-oxide-semiconductor field-effect transistors,” IEEE Electron Device Lett., vol. 15, pp. 100–102, Feb. 1994.
[1.20] A. Lochtefeld and D. A. Antoniadis, “Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress,”
IEEE Electron Device Lett., vol. 22, pp. 591–593, Aug. 2001.
[1.21] S. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field-effect transistors,’ J. Appl. Phys., pp. 1567-1577, vol. 80, August 1996.
[1.22] E. X. Wang, P. Matagne, L. Shifren, B. Obradovic, R. Kotlyar, S. Cea, M. Stettler, and M. D. Giles, “Physics of hole transport in strained silicon MOSFET inversion layers,” IEEE Trans. Electron Devices, vol. 53, pp. 1840-1851, August 2006.
[1.23] X. F. Fan, X. Wang, B. Winstead, L. F. Register, U. Ravaioli, and S. K. Banerjee,
“MC Simulation of Strained-Si MOSFET With Full-Band Structure and Quantum Correction,” IEEE Trans. Electron Devices, vol. 51, pp. 962-970, June 2004.
[1.24] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S.
Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y.
El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Trans.
Electron Devices, vol. 51, pp. 1790-1797, November 2004.
[1.25] S. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs” in IEDM Tech. Dig., Dec. 2004, pp. 221-224.
[1.26] T. B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R.
Mann, “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans.
Electron Devices, vol. 50, pp. 1946-1951, September 2003.
[1.27] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K.
Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc.
of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
[1.28] J. Watts, K. W. Su, and M.Basel, “Netlisting and Modeling Well-Proximity Effects,” IEEE Trans. Electron Devices, vol. 53, pp. 2179-2186, September 2006.
[1.29] Y. M. Sheu, K. W. Su, S. Tian, S. J. Yang, C. C. Wang, M. J. Chen, and S. Liu,
“Modeling the Well-Edge Proximity Effect in Highly Scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp. 2792-2798, November 2006.
Berkeley Short-channel IGFET Model (BSIM) version 4.5.0 manual, chapter 14.
Fig. 1.1 Half pitch and gate length trends predicted by ITRS (adapted from Ref.[1.1]).
nMOSFET
pMOSFET
Fig. 1.2 TEM images of 35nm-gate-length MOSFETs using mechanical strained technologies (adapted from Ref.[1.12]).
Fig. 1.3 Schematic representation of the constant-energy ellipses for (a) and (b) unstrained Si and (c) and (d) strained Si. (a) and (c) are for a 3DEG in bulk Si. (b) and (d) are those of a 2DEG in a Si inversion layer. (e) and (f) are the schematic diagrams
Fig. 1.4 Simplified valence band E vs. k diagram for strained Si (adapted from Ref.[1.25]).
(a) 2-D dopant concentration contour plot
(b) Dopant profiles of lateral cut line in the 2D contour plot
Fig. 1.5 (a) Contour plot of simulated doping near resist mask edge. Both boron (intermediate and near-surface) and phosphorus (deep) implantations were simulated. (b) Simulated lateral doping profiles of B and P immediately below the silicon surfaces (adapted from Ref.[1.12]).
gate
pWell
source drain
Fig. 1.6 Simulated dopant distribution contours of a novel MOSFET using a TCAD tool (TSURPEM4).
gate
pWell
drain source
0 100 200 300 400 500 600
0 0.2 0.4 0.6 0.8 1 1.2
drain voltage (volt) dr ai n c u rr ent ( µ A/ µ m) .
Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V
Fig. 1.7 Simulated (a) electrical current distribution contours and (b) output current-voltage plot of the MOSFET shown in Fig. 1.6.
Chapter 2
Dopant Diffusion Under Mechanical Stress 2.1 Preface
Shallow trench isolation (STI) induced mechanical stress increases in magnitude with reduced device active areas of highly scaled CMOS technology, causing a non-negligible impact on device performance [2.1]-[2.4]. Both experimental work and numerical simulations have been conducted to calculate the STI stress magnitude and distribution encountered in scaled MOSFETs [2.5]-[2.9].
The results show that the silicon stress level near the STI region is high. As design rules or layout dimensions scale down, the high-stress region encroaches further into the MOSFET channel. Thus, STI mechanical stress has a significant influence on state-of-the-art device performance.
Earlier work studying the mechanical stress effect has been focused on the MOSFET drive current shift, either in the form of localized or planar stress conditions [2.1]- [2.3], [2.6], [2.10]-[2.14]. Several studies have been performed to link STI mechanical stress to mobility changes while accounting for the observed current shift [2.2], [2.12], [2.13], although no threshold voltage shift mechanism has been investigated. G. Scott, et al. [2.14] have investigated both the drive current and threshold voltage shift, suggesting a difference in stress-induced diffusivity as the plausible origin of the threshold voltage shift. So far, however, there has been no further elaboration on this aspect. On the other hand, there has been a great deal of work devoted to dopant diffusion behavior in silicon under the influence of
mechanical stress [2.15]-[2.19]. Cowern, et al. [2.15] proposed a strain-induced dopant diffusivity model of boron diffusion in SiGe. S. T. Ahn, et al. [2.17]
concluded that in the presence of high-stress nitride film, phosphorus diffusion in the silicon was retarded, whereas antimony diffusion was enhanced. Aziz [2.18]
established a relationship between hydrostatic pressure and biaxial strain via thermodynamic formulation, while accommodating calculation of the activation energy shift due to strain. Based on Aziz’s and Cowern’s theoretical work [2.15], [2.18], Zangenberg, et al. [2.19] critically reviewed the findings over the past 10 years and further identified the strain effect on boron and phosphorus diffusion in SiGe.
However, most studies in the area of mechanical stress induced dopant diffusion changes remain in fundamental research, i.e., at the silicon material level, and have not yet been extended to semiconductor device characterization and modeling.
It is well recognized that the key MOSFET parameters, such as threshold voltage, drain induced barrier lowering, body factor, and subthreshold swing, are all strongly dependent on dopant distribution details. Thus, it is crucial to examine stress-dependent dopant diffusion for scaled MOSFETs under mechanical stress.
In this chapter, a stress-dependent diffusion model and incorporate it into a two-dimensional process simulation environment to assess the doping distribution effect in scaled MOSFETs is presented. The proposed model is corroborated by extensive experimental data in a sub-100nm CMOS technology.
2.2 Stress-dependent Diffusion Model and Modeling Methodology
2.2.1 Model Description
The dopant diffusion change due to mechanical stress has been derived from point defect (interstitials and vacancies) changes[2.18]. Mechanical strain influences the point defect formation and migration, while the microscopic volume change and the pressure both contribute to the Gibb’s free energy change. Thus, the dopant diffusivity ratio with and without strain can be expressed in an Arrhenius form; and the strain-induced point defect energy change can be translated to the dopant diffusivity change. For example, in the case of a compressively strained SiGe layer where Cowern studied boron diffusion [2.15], the stress condition is regarded as biaxial and the dopant diffusion dependence follows the Arrhenius form
−
= kT
D sQ
DS A '
exp (2.1)
where DS is the dopant diffusivity under strain, DA is the dopant diffusivity without strain, s is the biaxial strain in the plane of the SiGe layer, and is the activation energy per strain. The concept of this equation is consistent with experimental data [2.15], [2.18] and theoretical calculations 12) showing a linear deffect of the mechanical strain to dopant diffusivity ratios on a log scale. Recently, Diebel [2.20] studied stress-dependent point defect equilibrium concentration and diffusion by means of ab initio calculations.
Q '
Analogous to equation (2.1), a stress dependent dopant diffusion model for dopant diffusion under STI mechanical stress, named Volume-change-ratio Induced Diffusion Activation Energy Shift Model (VIDAESM) is developed. The volume change ratio, Vcr, is a function of position due to non-uniform stress distributions.
In this study, the MOSFET width is large enough to allow the three-dimensional stress effect to be reduced to the two-dimensional one. The activation energy involved is the product of a dopant dependent coefficient and volume change ratio, meaning that Eq. (2.1) can be re-written in the case of dopant diffusion under STI mechanical stress
where DS is the dopant diffusivity under strain, DA is the dopant diffusivity without strain, Vcr is the volume change ratio due to stress, ∆ES is the activation energy per volume change ratio depending on the dopant species, and T is the temperature.
When the strain is small, the volume change ratio can be expressed as
zz direction perpendicular to the silicon surface, εzz is the strain along the channel width direction, and εt is the strain summation of εxx, εyy, and εzz. Note that εzz is zero in the two-dimensional simulation due to wide structures adopted. Therefore, Eq. (2.2)
becomes
A two-dimensional numerical process simulator, TSUPREM4, is chosen to perform the process simulation. TSUPREM4 is capable of simulating intrinsic dopant diffusion, three-stream dopant-point defect pairing diffusion, oxidation enhanced diffusion effect, dopant clustering effect, and dislocation loop effect. For assessment of mechanical stress, the simulator also simultaneously solves force balance equations while taking into account thermal expansion, intrinsic stress, geometry re-arrangement after etch and deposition processes, and the thermal oxidation process [2.21]. The stress-dependent diffusion model, VIDAESM, has been incorporated into the simulator through the user-specified equation interface to adaptively calculate stress-dopant diffusivity during the process simulation.
2.2.2 Modeling Methodology
To model stress-dependent dopant diffusion for various stress levels, a series of MOSFETs with various active area sizes are designed and fabricated. Fig. 2.1 schematically shows the cross section view of a test device along the channel direction. The mechanical stress effect was explored here with active area size, Xactive, and gate length Lg, both used as the main structural parameters.
The flow chart of the modeling procedure is shown in Fig. 2.2. Firstly, the
one-dimensional dopant profiles were processed using blanket control wafers, which covered the range of the process conditions of the device wafers. The results were then taken as stress-free dopant profiles and used to calibrate the dopant diffusion parameters without stress-dependent models.
Secondly, two-dimensional MOSFET structures were simulated using the mechanical stress model. Calibrated diffusion parameters were employed to simulate a large Xactive MOSFET, where the stress level is low. All front-end major process steps from the STI to the source/drain anneal were considered. The corresponding simulation geometries were calibrated using TEM cross-sectional images. Some fine-tunings of two-dimensional dopant profile parameters, such as implant lateral straggles and segregation factors, are needed to fit the silicon device I-V characteristics. Fig. 2.3 shows the calibration result of a short channel nMOSFET I-V with a large Xactive.
Next, with the stress distribution known, the stress-dependent diffusion models were introduced to simulate MOSFETs with varying Xactive values. After implementing the stress-dependent diffusion model, process simulation results were used as device simulation inputs. MEDICI was chosen as the numerical device simulator. The device modeling parameters, such as carrier mobility, work function, and silicon/oxide interface charges were calibrated to fit the I-V of large Xactive
MOSFETs. Then, device simulations with various Xactive values were performed and compared with silicon device data. The above procedure was iterated from process to device cycle until the current-voltage data was all satisfactorily reproduced in all
cases. The ∆ES values from the previous work [2.15] were employed as the initial guess values. It is worth noting that the numerical convergence and simulation speed were not greatly influenced after implementing VIDAESM. The simulation time incorporating VIDAESM increases by about 7% compared to that without VIDAESM.
2.2.3 Experiment on MOSFET Threshold Voltages and Modeling Results
The silicon wafers were fabricated using novel CMOS processes. The control wafers for one-dimensional SIMS analysis were processed using the same thermal steps as device wafers. Fig. 2.4 displays SIMS results for both n and pMOSFET.
The implant conditions were BF2 2keV 1×1015cm-3 and As 2keV 1×1015cm-3 for ultra shallow junction calibration and the junction depths are around 260 angstroms for both devices by taking the substrate doping as 2×1018cm-3. The calibrated simulation profile is also plotted in Fig. 2.4. The calibration procedure included the fine-tuning of implant damage, dopant-point defect pairing diffusion, silicon-oxide dopant segregation, oxidation enhanced diffusion models, dopant clustering models, dopant-defect clustering models, and intrinsic diffusion models.
The stress simulation involved the main process steps, which are STI formation, gate oxidations, and poly-gate formation in sequence. Viscoelastic oxidation model was used to simulate the stress dependent oxide growth. The Young’s moduli used were 1.87×1012dyne/cm2 for the silicon and 6.6×1011dyne/cm2 for the oxide layers.
The intrinsic stress used is –1.5×109dyne/cm2 for the STI oxide and 3.3×108dyne/cm2
for gate spacer oxide. The other parameters follow the default values in the TSUPREM4 manual [2.21]. The stress distribution results for different Xactive values are given in Fig. 2.5. It can be seen that the polarity of the strain εxx in the lateral direction is negative, meaning that the MOSFET core area experiences a compressive stress. On the other hand, strain εyy in the vertical direction is tensile with a magnitude much smaller than εxx. In particular, Fig. 2.5(b) reveals that εxx drastically increases in magnitude with decreasing Xactive values. Three reference points A, B, and C are chosen to inspect the value of the strain. A is at the center of the gate, B is 75nm away from the gate center and C is 150nm from the gate center. The depth of these points is 20nm from the silicon surface. Fig. 2.6 highlights the magnitude of the strain versus the Xactive value at points A, B, and C in Fig. 2.5. The negative polarity of the strain means that the general strain conditions in the active area are compressive, and the magnitude increases rapidly as value of Xactive decreases. The compressive stress mainly comes from lower thermal expansion rate of the STI oxide compared to silicon, and the thermal gate oxidation induced volume expansion at the STI edge. As Xactive decreases, the STI approaches the MOSFET core region and increases the magnitude of compressive stress. The strain at rapid thermal peak temperature remains compressive and the magnitude is about 0.15% at the MOSFET core region for the minimum Xactive case.
The MOSFET channel width in the silicon experiment was fixed at 10µm, large enough to ensure that the stress along the channel width direction is negligible.
Simulations were conducted to evaluate the mechanical stress along the channel
width direction. The results showed that the average strain level for channel width W=10µm is around -0.02%, which is at least two order of magnitude lower than the peak strain level used in this study. The MOSFET design set consisted of Xactive
values from 0.6µm to 10µm and Lg from 65nm to 0.42µm. It has been recognized that boron and phosphorus diffusion are retarded by compressive strain [2.15], [2.19], [2.22]. The stress simulation results show that the MOSFET channel stress and strain magnitudes for Xactive=10µm are around -1×108 dyne/cm2 and –0.04%, respectively. As the Xactive value shrinks to 0.6µm, the corresponding stress and strain magnitudes become around -5×109 dyne/cm2 and -0.4%, respectively. The compressive strain level in the channel region is quite close to the strain produced by 10% germanium in silicon, which falls within the range of Cowern’s and Zangenberg’s studies [2.15], [2.19].
In the present work, the impurities introduced to form nMOSFET are boron,
In the present work, the impurities introduced to form nMOSFET are boron,