Impact on Circuit Design

It would not be sufficient to consider only the W and L of MOSFETs during the design of circuits for advanced CMOS technologies. Both the layout shape and

circuit performance. It is quite a straightforward matter to simply enlarge the design margin of the circuit to cover the LOD effect, but this would be too luxurious and impractical. Designers may need to take the LOD effect into rough consideration at the beginning of the design process and should check it again when the layout is completed.

As shown in Figs. 3.17 and 3.18, the PMOS performance is enhanced, but the NMOS performance is degraded when the LOD is shrunk. So the total circuit delay may not change too much because the LOD effect on the nMOSFET and the pMOSFET drive current is opposite. However, the rise time and fall time will probably have been seriously altered. The threshold voltage shift induced by the LOD effect is another issue, which will further cause the NMOS devices performance degradation, and will also possibly worsen the cases with corner conditions. In general, the LOD effect is more significant for longer channel (0.2um~1um) and wider channel (>1um) and thus high-speed input/output (IO) circuits would be more susceptible to the LOD effect than core circuits. The impact of the LOD effect also needs to be considered when designing patterns for SPICE modeling.

Modeling accuracy would be greatly enhanced if the proper choice were made with regard to the default LOD size.

References

[3.1] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., Dec. 1999, pp. 827-830.

[3.2] C. C. Wu, Y. K. Leung, C. S. Chang, M. H. Tsai, H. T. Huang, D. W. Lin, Y. M.

Sheu, C. H. Hsieh, W. J. Liang, L. K. Han, W. M. Chen, S. Z. Chang, S. Y. Wu, S.

S. Lin, H. C. Lin, C. H. Wang, P. W. Wang, T. L. Lee, C. Y. Fu, C. W. Chang, S.

C. Chen, S. M. Jang, S. L. Shue, H. T. Lin, Y. C. See, Y. J. Mii, C. H. Diaz, Burn J.

Lin, M. S. Liang, Y. C. Sun, “A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications,” in IEDM Tech. Dig., Dec. 2002, pp. 65-68.

[3.3] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., pp.

2234-2252, vol. 80, Nov. 1996.

[3.4] V. Senez, T. Hoffmann, E. Robiliart, G. Bouche, H. Jaouen, M. Lunenborg, and G. Carnevale, “Investigations of stress sensitivity of 0.12 CMOS technology using process modeling,” in IEDM Tech. Dig., Dec. 2001, pp. 831-834.

[3.5] T. Kuroi, T. Uchida, K. Horita, M. Sakai, Y. Inoue,and T. Nishimura, “Stress analysis of shallow trench isolation for 256 M DRAM and beyond,” in IEDM Tech. Dig., Dec. 1998, pp. 141-144.

[3.6] A. Lochtefeld and D. A. Antoniadis, “Investigating the relationship between

IEEE Electron Devices Lett., vol. 22, pp. 591-593, Dec. 2001.

[3.7] H. Park, K. S. Jones, J. A. Slinkman, and M. E. Law, “The effects of strain on dopant diffusion in silicon,” in IEDM Tech. Dig., Dec. 1993, pp. 303-306.

[3.8] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117-120.

Fig. 3.1 Key MOSFET layout parameter definitions in this work and schematic cross section along channel length direction.

-0.4

Fig. 3.2 Long channel threshold voltage VT versus (a) Xactive and (b) Xecc for a variety of W. Obviously, VT is insensitive to STI mechanical stress.

1 10 100

480 520 560 600 640 680 720

50 10 1 0.6

Xactive (µm)

(a) nMOS, W=10µm

Ioff (nA/µm)

Idsat (µA/µm)

1 10 100

220 240 260 280 300 320

50 10 1 0.6

X^active (µm)

(b) pMOS, W=10µm

Ioff (nA/µm)

Idsat (µA/µm)

Fig. 3.3 Short channel Idsat-Ioff for (a) nMOSFET and (b) pMOSFET for a variety of Xactive. Idsat at Ioff=10nA/µm is taken as drive current index.

Fig. 3.4 Short channel Idsat versus active area dimension Xactive with different W for (a) nMOSFET and (b) pMOSFET. nMOSFET Idsat is degraded while pMOSFET Idsat is enhanced as active area size decreases. Idsat becomes insensitive to Xactive when active area size is greater than 5µm.

Fig. 3.5 Short channel Idsat versus gate placement inside active area Xecc for different W for (a) nMOSFET and (b) pMOSFET. nMOSFET Idsat is degraded while pMOSFET Idsat is enhanced as gate placement is closer to STI edge.

Fig. 3.6 Short channel Idsat versus W for (a) nMOSFET and (b) pMOSFET with various Xactive. Both n and pMOSFET drain currents degrade as W decreases.

+10¹⁰ + 10⁹ + 10⁷ + 10⁵ + 10³ + 10¹

−100¹

−10³

−10⁵

−10⁷

−10⁹

−10¹¹

σ

_xx

dyne/cm²

silicon

surface stress to be extracted

STI polysilcon

STI

Fig. 3.7 Simulated final stress Sxx distribution for Xactive=0.6µm. Stress near Si/SiO2 interface is found to be compressive.

Fig. 3.8 Simulated strain εxx inside silicon along a line 20Å deep below Si/SiO2 interface for different active area dimensions. Strain magnitude increases as active area size decreases.

Fig. 3.9 Simulated hydrostatic pressure and strain εxx for different active area dimensions. Stress and strain magnitudes increase rapidly as active area size decreases from around 5µm.

Fig. 3.10 Experimental drive current sensitivity and simulated strain εxx both versus active area size for (a) n-FET and (b) p-FET. A one-to-one mapping remains effective for both n-FETs and p-FETs.

Fig. 3.11 Experimental drive current shift with respect to W=10mm, Xecc=0 versus Xecc

for different Xactive. Simulated strain εxx is also shown together for comparisons. The trends of drive current and strain match well.

Fig. 3.12 Stress distribution near the gate oxide interface of MOSFET using 2D simulation.

Fig. 3.13 Drain current shift with respect to different LOD sizes for different channel lengths.

Fig. 3.14 schematic stress distribution within the channel regions.

Fig. 3.15 Threshold voltage shift with respect to different LOD sizes for different channel lengths.

Fig. 3.16 A typical layout of MOS devices needing more instance parameters (swi, sai and sbi) in addition to the traditional L and W.

Fig. 3.17 nMOSFET drain current (Id) difference in percentage between SA=0.25µm and 5µm comparing various channel lengths and widths.

Fig. 3.18 pMOSFET drain current (Id) difference in percentage between SA=0.25µm and 5µm comparing drain currents in linear and saturation regions.

Fig. 3.19 Temperature sensitivity of LOD effect. LOD effect is quite insensitive to temperature and simply a linear equation could simulate the dependence.

Fig. 3.20 Vth shift between SA=0.25µm and SA=5µm with Vds=0.1V and Vdd for different channel lengths.

Fig. 3.21 Gamma shift versus LOD with different channel lengths. Gamma increases as LOD decreases because of higher channel doping concentrations due to diffusion retardations by compressive stress.

Fig. 3.22 Symmetric and asymmetric irregular layouts under study and the corresponding drain current shift in percentage.

Chapter 4

Well-Edge Proximity Effect 4.1 Preface

As CMOS VLSI technology progresses to the nanometer regime, several physical effects become significant as a result of aggressive layout scaling [4.1]-[4.3].

MOSFETs are formed during the front-end of the fabrication process, which mainly consists of shallow trench isolation (STI), MOSFET wells, and MOSFET gate formation. The effect of the well-edge proximity to the MOSFET gates was first reported by Hook [4.4] and originates from the lateral scattering of ion implantations at the photoresist edge when forming MOSFET wells, which in turn causes a change in the MOSFET threshold voltage.

In this chapter, a silicon wafer experiment was performed using state-of-the-art CMOS technology to investigate this effect. Monte Carlo ion scattering and integrated TCAD simulation was conducted to evaluate the dopant profile variations of the well ion implantation. The calibrated process and device TCAD simulations were used to quantify the impact on MOSFET electrical characteristics. Utilizing a physics-based understanding and silicon experimental results, a new model that corrects the inaccuracies of current SPICE models is proposed.

4.2 Ion Scattering Physics and Modeling

mechanisms. The first mechanism is elastic nuclear stopping, which causes the ions to be scattered away from their original paths. The second mechanism is inelastic electronic stopping, which acts as a drag force causing negligible angular deflections of the moving ions.

The principal assumption of the Monte Carlo model is that the interaction of the energetic ions with the solid may be separated into a series of distinct two-body collisions (binary collision approximation). Thus, Monte Carlo modeling of ion implantation consists of following the ions from one scattering event to the next, and properly accounting for all energy loss mechanisms and deflections. The Monte Carlo model for implants into crystalline silicon was described in detail in [4.5].

Here, only the models pertaining to high-energy ion implantation into the photoresist will be discussed.

In the Monte Carlo model, the photoresist is treated as an amorphous material with the average path length of the ion between collisions being l =1/³ N _{, where N} is the atomic density of the photoresist. The collision partners are randomly selected, assuming that the probabilities of encountering each component of atoms are proportional to their stoichiometric abundances (assuming 50% hydrogen, 37.5%

carbon, and 12.5% oxygen). For each collision, the impact parameter is determined byp= R_np^max, where Rn is a uniformly distributed random number between 0 and 1,

and pmax is the maximum impact parameter given byl/ π . The interactions between the ions and the target atoms are modeled using the Ziegler-Biersack-Littmark (ZBL) universal interatomic potential [4.6]. If the atomic

mass of the projectile is greater than that of the target atom, it can be shown that, for a single collision, a maximum scattering angle exists:

) respectively. Therefore, although hydrogen is more abundant in composition, carbon and oxygen are more effective in deflecting the implanted ions. Most ions experience many collisions before they are scattered out of the photoresist.

For electronic stopping, the Lindhard-Scharff (LS) formula [4.7] is used:

m E

where Z1 and E are the atomic number and the kinetic energy of the projectile, respectively. Z2 is the average atomic number of the photoresist, and α is an empirical correction factor. It is interesting to note that without any adjustment of the parameter α (=1), LS stopping power predicts the projected ranges of B and P implants below 1 MeV very well.

At high energy, the cross-section for nuclear scattering is small, and the ions experience very few nuclear collisions. Thus electronic stopping is the dominant energy loss mechanism. For example, for a B 300 keV implant, electronic stopping accounts for 88% of the total energy loss. In this energy regime, most ions move in approximately straight lines, and are rarely scattered out of the photoresist. As the ions slow down and approach their projected range, the nuclear scattering

experiencing many collisions, some ions are scattered out of the photoresist edge.

Once an ion is scattered out of the photoresist, it is assumed to move in a straight line until it re-enters the silicon substrate. The exact entry point depends on the position at which the ion exits the photoresist, its direction of motion, and the topography of the device.

Fig. 4.2 shows the angular distribution and the depth distribution of the ions that are scattered out of the photoresist edge for B 300 keV and P 625 keV implants.

Both of these dopants have approximately the same projected range at 1.08µm in the photoresist. It is worthwhile noting that, for the given implant conditions, the total number of ions that are scattered out of the photoresist is roughly the same for both B and P. It can also be seen that most ions are scattered out of the photoresist just before reaching the projected range. In addition, ions exit the photoresist edge with a peak at angle of ~10°, and a significant portion of ions exit with angles below 30°.

Ions exiting at large angles may travel a long distance in a lateral direction and be implanted into the active area of the MOSFET. Thus, the dopant distribution due to the well-edge proximity effect can be accurately simulated using the Monte Carlo simulator.

4.3 TCAD Numerical Simulation

Full process two-dimensional TCAD simulation was performed to model MOSFET dopant distribution and electrical behavior. Monte Carlo well ion implantation mentioned in the previous section was applied to simulate the dopant

scattering effect at the edge of the well photoresist. The well to gate-edge distance is denoted as SC, and is shown in Fig. 4.1. Ions scatter from the well photoresist edges and are implanted into the silicon active areas when forming retrograde wells using high-energy boron and phosphorus ion implantations for n and pMOSFETs, respectively. Fig. 4.3 shows the simulation dopant distributions after the well ion implantations. In the graph for SC=0.9µm, the well dopant concentrations are low and almost constant at the silicon surfaces through the active area for both n and p-wells. As SC decreases to 0.54µm, several extra dopant clusters introduced from well-edge ion scattering can be observed at the STI and silicon surface near the well photoresist edges. When SC further decreases to 0.4µm, the extra dopant clusters move toward the center of the active area and the well dopant concentrations become higher in cases where the SC is larger. In Fig. 4.4, final vertical boron and phosphorus profiles along the MOSFET center for various well to gate edge distances are shown for n and pMOSFETs, respectively. The additional implants, besides the retrograde well implants, are boron 1.4×10¹³ cm^-2 100 KeV for the n-MOSFET and phosphorus 1×10¹³ cm^-2 240 KeV for the pMOSFET. As observed, the channel dopant concentration increases as the well photoresist edge approaches the MOSFET active area. To further quantify the extra dopant concentration introduced by well-edge ion scattering, the average dopant concentration for the area 20nm below the MOSFET gate versus SC were plotted in Fig. 4.5.

The silicon experiment using novel CMOS technology was conducted to explore the well-edge proximity effect. MOSFETs with various well to gate-edge

distances were designed, fabricated, and electrically measured. The process and device simulations were first calibrated according to a standard MOSFET set, in which the SC is larger than 10µm. Then simulations using various SC values were performed to obtain the threshold voltage trend of the MOSFET versus SC. Fig. 4.6 shows the matched result of silicon experiment and TCAD simulation.

4.4 Compact Model for SPICE

Since this new layout-dependent phenomenon increases the threshold voltage and thus decreases the drain current of the MOSFETs, it is especially important for those circuits with high integration density. This effect might also introduce uncertainties to those circuits that are sensitive to the matching of threshold voltage.

Therefore, it is necessary to consider this effect in the SPICE simulation and the post-layout extraction flow. However, the most challenging part of a layout-dependent model is to determine a method of catering for various layout styles in as complete a manner as possible while retaining the efficiency of the procedure.

Fig. 4.7 shows typical several layout styles of a MOSFET in a well. As shown in Fig. 4.7(a) and (b), the well edges are close to the MOSFETs in the channel-length direction, and in Fig. 4.7(c) and (d) the proximity occurs in the channel-width direction. Narrow MOSFETs will have a strong well-edge proximity effect for layout (c) and (d) as a large portion of the channel region is influenced by the dopant ion scattering at the well edge. However, the MOSFET channel width does not play an

important role in layout (a) and (b). A useful compact model should cover each of these possibilities.

Fig. 4.8 is another generalized example to cover various layout conditions, including those shown in Fig. 4.7. From Fig. 4.8, the overall additional dose of dopant introduced by ion scattering at the well edges and that affect the channel region can be represented by the following integrals:



where f(x) is used to account for both the lateral and vertical distribution variations of the scattered well dopants. In some cases, f(x) might be a combination of several exponential terms. However, our analysis shows that 1/x² is a good approximation for f(x) to cover most conditions. With this approximation, an effective device-to-well-edge distance, SCeff, is proposed:

5

Note that the SCeff can easily summarize all four conditions shown in Fig. 4.7.

A smaller SCeff indicates that the MOSFET is closer to the well edge and the well-edge proximity effect will be more severe. Then, the impact of the well-edge proximity effect can be described by adding more SCeff-dependent equations to the conventional model. Since the major effect is due to the MOSFET dopant profile change, three corresponding MOSFET parameters, threshold voltage, body effect coefficient, and carrier mobility, are modified to include the variations caused by this effect. The respective equations are shown as follows:



where Vth0 is the threshold voltage of the MOSFET, K2 is the body effect parameter, and the µeff is the effective carrier mobility. SCeff is the effective distance from the well edge to the channel region, which can be extracted from circuit layouts for each MOSFET by the layout parameter extraction (LPE) tools using equation (4.4).

SCREF, SC0, KVTH0WE, K2WE, KU0WE, and NWE are the fitting parameters.

This model has been verified using various types of MOSFET layout patterns,

as shown in Fig. 4.7. Devices with different channel lengths and widths are also considered here in order to check the dependence of the well-proximity effect on W and L. Fig. 4.9, Fig. 4.10 and Fig. 4.11 show the comparison between the model and the silicon for the threshold voltage shift, drive current degradation, and body effect increase of MOS transistors. As shown in these plots, the correlation between the model and the silicon is quite reasonable. Note that no matter whether the device is close to the well edge either in the channel length or in the width direction, the concept of SCeff can explain those differences and thus the data obtained from layouts illustrated in Fig. 4.7 show the same trend in the threshold voltage change (dVth) vs.

SCeff plot, as indicated in fig. 4.9. For those devices with smaller SCeff, the threshold voltage will also increase further, but it may saturate at a certain value.

Fig. 4.10 shows the drive current degradation induced by the well-edge proximity effect. When SCeff becomes smaller, the threshold voltage increases and thus the drive current will decrease. In addition to the Vth change, our analysis shows that the effective mobility is also degraded by the well-edge proximity effect. This is because the impurity scattering becomes more severe as the dopant concentration increases. Fig. 4.11 demonstrates the dependence of the body effect on the well-proximity effect. When SCeff is small, the average doping density in the channel region will increase. Then the body effect (gamma) will become higher at the same time. The model is able to predict this change.

References

[4.1] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., Dec. 1999, pp. 827-830.

[4.2] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117-120.

[4.3] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K.

Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc.

of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.

[4.4] T. B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R.

Mann, “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans.

Electron Devices, vol. 50, pp. 1946-1951, September 2003.

[4.5] S. Tian, “Predictive Monte Carlo ion implantation simulator from sub-keV to above 10 MeV”, J. Appl. Phys., vol. 93, pp. 5893-5904, May 2003.

[4.6] J. F. Ziegler, J. P. Biersack, and U. Littmark, “The Stopping and Range of Ion in Solids”, Pergamon, New York, 1985.

[4.7] J. Lindhard and M.Scharff, “Energy Dissipation by Ions in the keV region”, Phys. Rev., vol. 124, pp. 128-130, October 1961.

High-energy ions

gate

SC

substrate

STI well

photoresist

Fig. 4.1 Origin of well edge proximity effect. High-energy dopant ions scatter at the well photoresist edge during the well ion implantation and the scattered ions are implanted in the MOSFET channel before the gate is formed. SC denotes the

Fig. 4.1 Origin of well edge proximity effect. High-energy dopant ions scatter at the well photoresist edge during the well ion implantation and the scattered ions are implanted in the MOSFET channel before the gate is formed. SC denotes the

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