先進金氧半場效電晶體對於佈局之依賴效應

國 立 交 通 大 學

電子工程學系電子研究所

博 士 論 文

先進金氧半場效電晶體對於佈局之依賴效應

Layout Dependent Effect on Advanced MOSFETs

研 究 生 ： 許義明

指導教授 ： 陳明哲 博士

先進金氧半場效電晶體對於佈局之依賴效應

LAYOUT DEPENDENT EFFECT ON

ADVANCED MOSFETS

研

究 生：許義明 Student:

Yi-Ming

Sheu

指導教授：陳明哲 博士

Advisor: Dr. Ming-Jer Chen

國立交通大學

電子工程學系

電子研究所

博士論文

A Dissertation

Submitted to Department of Electronics Engineering &

Institute of Electronics

College of Electrical Engineering and Computer Science

National Chiao-Tung University

in Partial Fulfillment of the Requirements

for the Degree of Doctor of Philosophy

in

Electronics Engineering

March 2007

先進金氧半場效電晶體對於佈局之依賴效應

學生: 許義明 指導教授: 陳明哲博士

國立交通大學 電子工程學系 電子研究所

Abstract (in Chinese)

摘要 次 100 奈米先進互補金氧半技術中之金氧半場效電晶體對於佈局的依賴效應已經 日趨明顯。本篇論文展示了兩個主要引起金氧半場效電晶體行為對於佈局依賴性的要素 - 製程引起的機械應力效應和井邊緣親近效應。 在製程引起的機械應力效應方面，第一點，本論文使用閘極長度為65 奈米的先進 互補金氧半技術完成了實驗之設計與執行。第二點，以包含種種機械應力來源並考慮全 製程的數值運算完整的模擬了整個金氧半場效電晶體結構。第三點，提出了一個新的應 力相依的摻雜擴散模型並將之加入於數值模擬軟體中，而模擬結果符合了矽晶片實驗實 驗範圍內之金氧半場效電晶體的次臨限(subthreshold)特性。第四點，本論文探討了淺 溝渠及熱氧化製程引起的機械應力和金氧半場效電晶體開狀態(on-state)對於佈局的依 賴效應的關係，發展出一組精簡、可變化規模(scalable)的新積體電路模擬程式(SPICE) 模型來解釋淺溝渠機械應力對金氧半場效電晶體性能的影響，並且成功預測晶片實驗中 各條件的實驗結果。 本論文亦使用了次 100 奈米先進互補金氧半技術詳細探討了由離子佈植時邊界摻

雜散射引起的井邊緣親近效應。晶片實驗和技術電腦輔助設計(TCAD)模擬被用來從物 理和製程的角度探討這個效應。蒙地卡羅離子散射模型和技術電腦輔助設計模擬提供了 金氧半場效電晶體內部如何形成改變的物理了解。一個基於此物理了解的精簡新積體電 路模擬程式模型被提出來並且以晶片實驗中各測試組結果完成此模型之校正。

Layout Dependent Effect on Advanced MOSFETs

Student: Yi-Ming Sheu Advisor: Dr. Ming-Jer Chen

Department of Electronics Engineering and Institute of Electronics National Chiao-Tung University

Abstract (in English)

The layout dependent effect on the MOSFETs characteristics has become more and more significant in advanced sub-100nm CMOS technologies. This dissertation demonstrates the experimental results, theories and modeling of two main factors making MOSFET behaviors layout dependent – process induced mechanical stress effect and well-edge proximity effect.

For the process induced mechanical stress effect, first, complete experiments are designed and conducted using novel CMOS technology with a minimum physical gate length of 65nm to investigate the mechanical stress effect. Second, full-process numerical simulations are performed for modeling complete MOSFET structures containing various mechanical stress sources. Third, a new stress-dependent dopant diffusion model is proposed and is implemented into the simulation software and the simulation results match MOSFET subthreshold characteristics of the silicon wafer experiment within the design space. Fourth, the

relationship between layout dependence of MOSFET on-state characteristics and mechanical stress caused by shallow trench isolation (STI) and thermal oxidation has been investigated, and a new compact and scaleable SPICE model accounting for the STI mechanical stress effect on MOSFET electrical performance is developed and successfully matches the experimental data under various conditions.

The well-edge proximity effect caused by the boundary dopant scattering during ion implantations is further explored using a sub-100nm CMOS technology in detail. TCAD simulations together with silicon wafer experiments have been conducted to investigate the impact of this effect from a physics and process perspective. The Monte Carlo ion scattering model and TCAD simulations provide a physical understanding of how the internal changes of the MOSFETs are formed. A new compact model for SPICE is proposed using physics-based understanding and has been calibrated using experimental silicon test sets.

Index Terms: dopant diffusion, mechanical stress, strain, shallow trench

isolation, MOSFET, mobility, Well-Edge Proximity, ion scattering, SPICE, modeling and simulation

Acknowledgements

First of all, I would like to express my sincere gratitude to my advisor, Prof. Ming-Jer Chen, for his constant guidance and support during my doctorate studies. Moreover, I was also deeply affected by his passion and persistence on academic research.

I also wish to show my appreciation to all of the committee members, including, Prof. Lih-Juann Chen, Prof. Jenn-Gwo Hwu, Prof. Ya-Ming Lee, Prof. Tien-Sheng Chao, Dr. Chih-Sheng Chang, Prof. Tahui Wang, Prof. Horng-Chih Lin, and Prof. Ming-Jer Chen for their invaluable comments and suggestions.

I have been very lucky to work with such intelligent and experienced colleagues in Taiwan Semiconductor Manufacturing Company (TSMC) for many years. Especially, I would like to acknowledge Dr. Carlos H. Diaz, Dr. Chih-Sheng Chang, Dr. Ke-Wei Su, Dr. Sheng-Jier Yang, Dr. Huan-Tsung Huang, and Da-Wen Lin for frequently providing insightful opinions and stimulating discussions. My thanks also go to TSMC TCAD group members and my other colleagues who assist in the success of the experiments.

The electronics engineering department of NCTU has provided me not only the base knowledge for my research but also a truly delightful learning experience. I would like to express my appreciation to Prof. S. M. Sze, Prof. Long-Ing Chen, Prof. Ching-Yuan Wu, Prof. Shun-Tung Yen, and all of the scholars who helped expand my knowledge in their classes and lectures.

and encouragement throughout my whole life. This dissertation is dedicated to them.

謝誌

首先，誠摯的感謝指導教授陳明哲博士多年以來的細心指導及大力支持。除此之 外，我深受老師對求學問的熱情與堅持所感動。 特別感謝論文口試委員陳力俊教授、胡振國教授、李雅明教授、趙天生教授、 張智勝博士、汪大暉教授、林鴻志教授以及陳明哲教授在百忙之中給予寶貴的建議及指 教。 很幸運的，能和台灣積體電路製造公司非常具有智慧及經驗的同事一起工作。其 中，我特別要感謝Carlos H. Diaz 博士、張智勝博士、蘇哿偉博士、楊勝傑博士、黃煥 宗博士和林大文先生經常提供寶貴的意見及討論。在此，也要對台積電 TCAD 成員及 其他對論文中實驗有幫助的同仁表達謝意。 交通大學電子工程研究所不僅提供我研究的基礎知識還有快樂的學習時光。課業 上，感謝施敏教授、陳龍英教授、吳慶源教授、顏順通副教授及其他學者教授我豐富的 知識及資訊。 最後，我要感謝我的家人長久以來支持、愛和鼓勵。這本論文，獻給他們。

Content (Index)

Abstract (in Chinese)...i

Abstract (in English) ...iii

Acknowledgements...v

Content (Index) ...viii

Table Captions ...x Figure Captions...xi Chapter 1 Introduction ...1 1.1 Overview...1 1.2 TCAD modeling...5 1.3 Dissertation Organization ...8 References ...9

Chapter 2 Dopant Diffusion Under Mechanical Stress ...21

2.1 Preface ...21

2.2 Stress-dependent Diffusion Model and Modeling Methodology ...23

2.2.1 Model Description ...23

2.2.2 Modeling Methodology...25

2.2.3 Experiment on MOSFET Threshold Voltages and Modeling Results...27

2.3 Experiment on MOSFET Subthreshold Leakage with Stress-Dependent Transient–Enhanced-Diffusion Effect Included...32

Modeling ...66

3.1 Preface ...66

3.2 STI Mechanical Stress Effects on Modern MOSFET Drive Currents ...66

3.2.1 Layout Matrix and Experimental Results ...66

3.2.2 Simulation and Systematic Analysis...68

3.3 SPICE Model for STI Mechanical Stress Effect...70

3.3.1 MOSFET Measurement Data Analysis...70

3.3.2 Model Development...71

3.3.3 Model Verification...74

3.3.4 Impact on Circuit Design...76

References ...78

Chapter 4 Well-Edge Proximity Effect...102

4.1 Preface ...102

4.2 Ion Scattering Physics and Modeling ...102

4.3 TCAD Numerical Simulation ...105

4.4 Compact Model for SPICE ...107

References ...111

Chapter 5 Summary and Future Work...123

5.1 Summary...123

5.2 Recommendations for Future Work ...125

Vita ...127

Table Captions

Chapter 2

Figure Captions

Chapter 1

Fig. 1.1 Half pitch and gate length trends predicted by ITRS (adapted from Ref.[1.1]).

Fig. 1.2 TEM images of 35nm-gate-length MOSFETs using mechanical strained technologies (adapted from Ref.[1.12]).

Fig. 1.3 Schematic representation of the constant-energy ellipses for (a) and (b) unstrained Si and (c) and (d) strained Si. (a) and (c) are for a 3DEG in bulk Si. (b) and (d) are those of a 2DEG in a Si inversion layer. (e) and (f) are the schematic diagrams for bulk strained Si and an inversion layer in strained Si, respectively. (adapted from Ref.[1.19]).

Fig. 1.4 Simplified valence band E vs. k diagram for strained Si (adapted from Ref.[1.25]).

Fig. 1.5 (a) Contour plot of simulated doping near resist mask edge. Both boron (intermediate and near-surface) and phosphorus (deep) implantations were simulated. (b) Simulated lateral doping profiles of B and P immediately below the silicon surfaces (adapted from Ref.[1.12]).

Fig. 1.6 Simulated dopant distribution contours of a novel MOSFET using a TCAD tool (TSURPEM4).

Fig. 1.7 Simulated (a) electrical current distribution contours (b) output current-voltage plot of the MOSFET shown in Fig. 1.6.

Chapter 2

Fig. 2.1 Schematic cross section of the device along channel length direction with active area size Xactive and gate length Lg both as parameters. The stress

condition is compressive mainly because of the lower thermal expansion rate of STI oxide compared to silicon, and the thermal gate oxidation induced volume expansion at the STI edge.

Fig. 2.2 Flow chart of the modeling procedure.

Fig. 2.3 I-V calibration result of a short channel nMOSFET with large Xactive for (a)

VD=0.05V and (b) VD=1V. Lg=65nm and Xactive=10µm. Symbols stand

for the silicon data. Solid lines are the calibrated simulation result.

Fig. 2.4 SIMS and calibration results of one-dimensional dopant profile for (a) nMOSFET and (b) pMOSFET.

Fig. 2.5 Simulated strain distribution in the silicon of entire front-end process for Lg=65nm and (a) Xactive=10µm and (b) Xactive=0.6µm. A small Xactive causes

a much higher strain.

Fig. 2.6 The magnitude of strain versus Xactive corresponding to three points A, B,

and C in Fig. 2.5.

Fig. 2.7 The depletion region boundaries with substrate bias, VB, for 65nm

nMOSFET at (a) VD=0.05V and (b) VD=1V.

Fig. 2.8 I-V comparison among experimental data, simulation without

stress-dependent diffusion model, and simulation with stress-dependent diffusion model for a small Xactive MOSFET at (a) VD=0.05V and (b) VD=1V.

lines are the simulation without stress dependent diffusion model. Solid lines are the simulation with stress dependent diffusion model.

Fig. 2.9 Comparison of experimental and simulated nMOSFET VG at different ID

level for various Lg and Xactive. Minimum Xactive for Lg=65nm is 0.6µm, for

Lg=0.18µm is 0.74µm, and for Lg=0.42µm is 1µm. Final set of dopant diffusion parameters can model MOSFETs of different Xactive under various

drain voltages and substrate biases. Symbols stand for silicon data. Solid lines represent simulations with stress dependent diffusion model.

Fig. 2.10 Experimental and simulated threshold voltage dependence on Xactive of (a)

nMOSFET and (b) pMOSFET. nMOSFET threshold voltage, VT, is more

dependent on Xactive than the p-type counterpart. Simulation with stress

dependent diffusion model is able to describe stress induced VT shift.

Fig. 2.11 Net doping contours for (a) Xactive=10µm, no stress-dependent model, (b)

Xactive=10µm, with stress-dependent model, (c) Xactive=0.6µm, no

stress-dependent model, and (d) Xactive=0.6µm, with stress-dependent

model. For Xactive=0.6µm, the source/drain junction is significantly

shallower in the MOSFET core region when the stress-dependent diffusion model is turned on. The gate length is 65nm.

Fig. 2.12 Dopant profiles of (a) vertical direction for Xactive=0.6µm nMOSFET, (b)

vertical direction for Xactive=10µm nMOSFET, (c) lateral direction for

Xactive=0.6µm nMOSFET, and (d) lateral direction for Xactive=0.6µm

simulation with stress-dependent diffusion model and dashed lines are

without stress-dependent diffusion model. Xactive=0.6µm with

stress-dependent model device exhibits significant retardation of dopant diffusion.

Fig. 2.13 Experimental and simulated ID-VG curves for Xactive=1.46µm. Symbols

represent experimental data, dashed lines are the simulation results without considering stress-dependent diffusion models, and solid lines are the final simulated results including stress-dependent diffusion models.

Fig. 2.14 Simulated strain distribution in the silicon after entire front-end process for

Xactive=0.68µm. The total strain is in the MOSFET core region are

compressive due to thermal gate oxidation and thermal mismatch between STI oxide and silicon.

Fig. 2.15 ID values at VG =-0.4 V for Xactive=20.2 µm, Xactive=1.46µm, and Xactive=0.68µm.

Symbols represent experimental data and solid lines are the final simulated results including stress-dependent diffusion models.

Fig. 2.16 Measured pMOSFET saturation threshold voltage versus the spacing between the nearby trench isolation sidewalls in the channel length direction. Also shown are those (lines) from the process-device coupled simulation with and without the strain induced activation energies.

Fig. 2.17 Uniaxial strain induced activation energy in the applied stress direction (parallel to the silicon surface) versus that normal to the silicon surface. The lines are from Eq. (2.14) and (2.15) for a literature range (Ref.

Also plotted are the data points from the underlying experiment and the existing ab initio calculations (Ref. [3.20], [3.29]).

Chapter 3

Fig. 3.1 Key MOSFET layout parameter definitions in this work and schematic cross section along channel length direction.

Fig. 3.2 Long channel threshold voltage VT versus (a) Xactive and (b) Xecc for a variety

of W. Obviously, VT is insensitive to STI mechanical stress.

Fig. 3.3 Short channel Idsat-Ioff for (a) nMOSFET and (b) pMOSFET for a variety of Xactive. Idsat at Ioff=10nA/µm is taken as drive current index.

Fig. 3.4 Short channel Idsat versus active area dimension Xactive with different W for

(a) nMOSFET and (b) pMOSFET. nMOSFET Idsat is degraded while pMOSFET Idsat is enhanced as active area size decreases. Idsat becomes insensitive to Xactive when active area size is greater than 5µm.

Fig. 3.5 Short channel Idsat versus gate placement inside active area Xecc for

different W for (a) nMOSFET and (b) pMOSFET. nMOSFET Idsat is degraded while pMOSFET Idsat is enhanced as gate placement is closer to STI edge.

Fig. 3.6 Short channel Idsat versus W for (a) nMOSFET and (b) pMOSFET with various Xactive. Both n and pMOSFET drain currents degrade as W

decreases.

Fig. 3.7 Simulated final stress Sxx distribution for Xactive=0.6µm. Stress near Si/SiO2

Fig. 3.8 Simulated strain εxx inside silicon along a line 20Å deep below Si/SiO2

interface for different active area dimensions. Strain magnitude increases as active area size decreases.

Fig. 3.9 Simulated hydrostatic pressure and strain εxx for different active area

dimensions. Stress and strain magnitudes increase rapidly as active area size decreases from around 5µm.

Fig. 3.10 Experimental drive current sensitivity and simulated strain εxx both versus

active area size for (a) n-FET and (b) p-FET. A one-to-one mapping remains effective for both n-FETs and p-FETs.

Fig. 3.11 Experimental drive current shift with respect to W=10mm, Xecc=0 versus

Xecc for different Xactive. Simulated strain εxx is also shown together for

comparisons. The trends of drive current and strain match well.

Fig. 3.12 Stress distribution near the gate oxide interface of MOSFET using 2D simulation.

Fig. 3.13 Drain current shift with respect to different LOD sizes for different channel lengths.

Fig. 3.14 schematic stress distribution within the channel regions.

Fig. 3.15 Threshold voltage shift with respect to different LOD sizes for different channel lengths.

Fig. 3.16 A typical layout of MOS devices needing more instance parameters (swi, sai and sbi) in addition to the traditional L and W.

Fig. 3.18 pMOSFET drain current (Id) difference in percentage between SA=0.25µm and 5µm comparing drain currents in linear and saturation regions.

Fig. 3.19 Temperature sensitivity of LOD effect. LOD effect is quite insensitive to temperature and simply a linear equation could simulate the dependence. Fig. 3.20 Vth shift between SA=0.25µm and SA=5µm with Vds=0.1V and Vdd for

different channel lengths.

Fig. 3.21 Gamma shift versus LOD with different channel lengths. Gamma increases as LOD decreases because of higher channel doping concentrations due to diffusion retardations by compressive stress.

Fig. 3.22 Symmetric and asymmetric irregular layouts under study and the corresponding drain current shift in percentage.

Chapter 4

Fig. 4.1 Origin of well edge proximity effect. High-energy dopant ions scatter at the well photoresist edge during the well ion implantation and the scattered ions are implanted in the MOSFET channel before the gate is formed. SC denotes the distance of well-photoresist edge to MOSFET gate edge.

Fig. 4.2 (a) Angular and (b) depth distributions of the ions scattered out of the photoresist edge for B 300keV and P 625keV implants. The angle is measured from the incident direction, and the depth is the vertical distance from the top surface of the photoresist to the point where the ion exits from the photoresist edge.

The well dopant distributions are influenced by the SC value. When SC decreases, extra well dopant clusters move toward the center of the active area.

Fig. 4.4 TCAD simulated vertical channel dopant profile versus well to gate edge distance, SC. The channel dopant concentration increases as the well photoresist edge approaches the MOSFET active area.

Fig. 4.5 TCAD simulated average dopant concentration for the area 20nm below the MOSFET gate versus SC.

Fig. 4.6 MOSFET threshold voltage shift versus well to gate edge distance of the silicon experimental and TCAD simulated results for n and pMOSFET. Lg=0.216µm.

Fig. 4.7 Typical layouts showing different positions of MOS transistors in a well. Fig. 4.8 Schematic presentation of a MOSFET layout and parameters used to

establish a well-edge proximity SPICE model.

Fig. 4.9 Model verification results of the MOSFET threshold voltage shift compared to the silicon experiment data.

Fig. 4.10 Model verification results of the MOSFET drive current degradation compared to the silicon experiment data.

Fig. 4.11 Model verification results of the MOSFET body effect change compared to the silicon experiment data.

Chapter 1

Introduction

1.1 Overview

During the last half of the previous century, the evolution of semiconductor technology became a major influence in the development of modern electronics. Developing a greater understanding of the function of both the positive and negative aspects of layout dependent effects such as the mechanical stress effect and the boundary ion implantation scattering effect is an essential part of device design and operation, and will no doubt continue to play an increasingly important role in the continuing evolution of the technology.

In Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSEFT) technology, layout dependent effects are inherently generated through the manufacturing processes, such as shallow trench isolation (STI), thermal oxidation, film deposition, and ion implantation scattering at the photoresist edges, which until recently were considered as a secondary effect. Moore’s law states that the number of transistors that can be created in a specific space will approximately double for each successive generation (18~24 months), which means that, as the technology follows the predicted path, the mechanical stress effect becomes more severe and gains more importance and focus. The trend toward increasingly smaller device sizes combined with predictions by the ITRS [1.1], shown in Fig. 1.1, clearly illustrates the past achievements of the industry, and also suggests that this trend is likely to

continue to follow Moore’s law for the foreseeable future.

Mechanical stress is the first effect being considered to make MOSFET layout dependent [1.2]-[1.5]. For some technologies, such as piezoresistive sensors and micro-electro-mechanical systems (MEMS), mechanical stress is a major feature of device operation. In the CMOS technologies, as the active area of each device is reduced, device designers are often forced to place the stress-generating sources closer together, with the influence of individual components often being superimposed upon each other, which, in turn, increases the magnitude of the mechanical stress. In addition, scaling rules also require MOSFET channel lengths to be reduced, thereby, accelerating the rate of increase in the average channel stress of the MOSFET, causing a significant impact on device performance that cannot be neglected [1.2]-[1.5]. Another aspect is that MOSFET performance can also be regarded as acting in a similar manner to Moore’s law, increasing by ~15% per generation as, in the past, any improvement could be roughly achieved simply by scaling the length, oxide thickness and junction depth. The era of such simplicity has now dissipated as polysilicon gate depletion, gate oxide leakage, the quantum mechanical effect, and carrier scattering became more severe once the technology entered the sub-100nm regime. In this situation, mechanical stress is not only considered to be a by-product of the aggressive downscaling of device feature sizes, but, recently, has also been generated deliberately in order to improve MOSFET performance. Technologies, such as the inclusion of a cap layer with high-level intrinsic stress following the formation of source and drain [1.6], [1.7], strained

silicon epitaxy on a strain-relaxed SiGe [1.8], [1.9], and a lattice mis-matched source and drain using selective epitaxy of SiGe [1.10] or SiC [1.11], have been widely used to boost MOSFET drive currents. Fig. 1.2 illustrates a set of recent cross-sectional TEM pictures for a CMOSFET with 35nm gate lengths, which show that the mechanical strain improved the mobility of the NMOSFET by 40% and the PMOSFET by 100% when compared to the unstrained MOSFETs [1.12].

Any analysis of the influence of mechanical stress on a MOSFET can be divided into two categories: (1). Physical changes that occur during the device fabrication process and, (2). Energy band structure changes. Of the two most common physical changes, the first, crystal flaws, has been observed since the early stages of semiconductor technology. There are several types of defects that can be commonly observed in silicon crystal, which are usually classified from their dimensionalities, such as interstitial atoms and vacancies (point defects), dislocations (line defects), stacking faults and slip lines (area defects), and voids (volume defects). Point defects always exist in the crystals and are highly mobile, generated and eliminated with low energy barriers as temperature increases. Their distribution plays an important role in dopant diffusion and is also affected by mechanical stress. Line defects and area defects are generally unwanted and are produced under enormous levels of mechanical stress during the manufacturing process. These crystal flaws will induce a large unwanted leakage current, if they are located near the PN junctions (source and drain or wells), or damage the gate oxide of the MOSFET. Several papers [1.13]-[1.16] have reported that the crystal defects generated by the

mechanical stress produced a junction leakage current as a result of the scaling of the devices. Large volume defects in the crystal, such as voids, are detrimental, but are seldom observed nowadays since they are usually well-controlled in modern silicon crystal growth technology and are not easily generated during the CMOS manufacturing process. Instead, dopant clusters and precipitates have become an increasingly important type of volume defect due to high dopant concentration and shorter thermal annealing time.

Dopant diffusion changes under different magnitudes of stress represent the second most common physical change and have become more prominent recently as a result of increases in the magnitude of mechanical stress as the dimensions of the MOSFET are scaled down. Changes in dopant diffusion result in a difference in the final dopant distribution, which will be reflected in the changes in subthreshold behavior and short channel effects (SCE) in the MOSFET. One of the difficulties encountered in stress-dependent dopant diffusion studies is that it is hard to measure the 2-D dopant diffusion directly. Therefore, the methodology of inverse modeling [1.17], which makes use of the sensitivity of the MOSFET subthreshold current-voltage to 2-D dopant profile, is utilized in this dissertation.

The second category covers the resultant mechanical stress in the MOSFET, inducing a silicon energy band structure change, which, in turn, affects the carrier effective mass of the carrier, together with the mobility and the on-state drive current of the MOSFET [1.18]-[1.25]. Fig. 1.3 and 1.4 shows the simplified band structure changes with the mechanical stress for electrons and holes, respectively, adopted

from Ref.[1.21] and [1.25]. The benefit of improving carrier mobility using mechanical stress, rather than improving the gate dielectric constant, is that the loading capacitance will not increase.

The second effect making the highly scaled MOSFET characteristics layout dependent is the dopant scattering at photo-mask edge during the ion implantations. Recently, strong effects have been observed especially when CMOS wells are formed by using high energy ion implantations [1.26]-[1.30]. The effect of the well-edge proximity to the MOSFET gates was first reported by Hook [1.26] and originates from the lateral scattering of ion implantations at the photoresist edge when forming MOSFET wells, which in turn causes a change in the MOSFET threshold voltage. Fig. 1.5 shows the simulated two-dimensional dopant distribution contours and lateral doping profiles of B and P immediately below the silicon surfaces. The studies on this effect are still preliminary and the effect becomes of increasing importance as CMOS devices continue to shrink further.

1.2 TCAD modeling

Numerical simulation has been widely applied in many scientific and engineering fields. It has been utilized for the physical understanding of semiconductor technology development through physical understanding in semiconductors, and is named as Technology Computer-Aided Design, or TCAD. As the technology continues to be developed, TCAD has become of increasing importance for two main reasons. The first mainly is because both the process and

the device physics have become more and more complex. From the process perspective, except for mechanical stress increases during scaling, novel process flows, including multi-species ion implantations and extremely short thermal process times, cause the dopant diffusion behavior to greatly deviate from traditional diffusion laws. In such cases, it is difficult to predict the dopant distribution in the device simply by using empirical calculations. The dopant profiles can only be obtained by solving complex coupled equations, such as damage production, point defect annihilation, and the cluster effect between point defects and dopants.

The second reason is a result of the need for cost reductions by increasing the wafer size for mass production, so the cost of a single wafer for experimental purposes increases rapidly as the wafer diameter increases. Furthermore, the high process-complexity of nano-scaled CMOS technology makes the cost of a single experiment conditions even higher. Therefore, TCAD is needed to help comprehend the complex physical phenomena inside semiconductor devices, to predict the result from process conditions, and to decide the domain of the wafer experiment. In fact, it not only helps to reduce the cost, but also shortens the time taken to reach the mass production stage, since computer simulation time is generally much shorter than the wafer process times. With the development and addition of some remarkable computer capabilities, researchers are now able to quickly conduct “virtual experiments” using a computer before real experiments in silicon are performed, and they can aim for targets with smaller experiment domains.

finite-differential and finite-element methods, which first establish the desired simulation structures (continuum) and divide the structures into diminutive elements and nodes using meshes. Then, basic physical equations are implemented and solved for the boundary conditions of each element and node, and a consistent result is obtained for the continuum. For process simulations, basic theories of dopant and defect diffusions, ion implantations, oxidation, and mechanical stress evolutions are solved. Fig. 1.6 shows the simulation results of dopant distribution in a MOSFET. After process simulation, device simulation is desired in order to determine the potential electrical behavior of the device. For device simulation, Poisson’s equation, carrier drift-diffusion equations, tunneling equations and quantum effect approximation equations are solved according to terminal bias conditions. Fig. 4 shows the carrier distribution of the MOSFET.

As the rush toward the next generation of semiconductor technology gathers pace, the necessity for conducting experimental work, as well as numerical simulations, in order to realize the impact of layout dependent effects on scaled MOSFETs, has gained focus. The goal of this dissertation is to study the layout dependent effect by conducting experiments using nano-scaled MOSFET technology, and to perform numerical process and device simulations using TCAD tools to investigate the mechanical stress distribution, stress-dependent dopant diffusion, and boundary dopant scattering effects during ion implantations encountered in the MOSFET from a full process point of view, and to explain MOSFET behavior using the proposed physical-based models.

1.3 Dissertation Organization

Chapter two begins with an introduction to the theory and the experiments designed to explore dopant diffusion under mechanical stress. The implementation of the proposed stress-dependent diffusion model into the TCAD simulation tools, TSUPREM4 and MEDICI, is then presented. Three applications, stress dependent diffusion effect on the MOSFETs threshold voltage, stress dependent diffusion effect on the subthreshold leakage of the low dopant concentration well nMOSFET, and anisotropic diffusion under uniaxial strain are introduced in detail.

Chapter three discusses the influence of mechanical stress on the on-state behavior of the MOSFET. The change in structure of the energy-band, and the resulting impact on drive current for both n and pMOSFETs, is discussed. The implementation of a new model into SPICE that accounts for the mechanical stress effect is also proposed for the circuit design.

Chapter four first addresses the dopant scattering effect at well-mask edges on the modern MOSFETs by a designed wafer experiment. In-depth understanding is displayed using full process and device simulations of TCAD tools. Physic-based SPICE models is proposed and is validated with experimental data for better circuit simulation accuracies.

Finally, Chapter five offers a conclusion to the research, together with a summary of the accomplishments, and addresses future work to be extended to the

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Fig. 1.1 Half pitch and gate length trends predicted by ITRS (adapted from Ref.[1.1]).

nMOSFET

pMOSFET

Fig. 1.2 TEM images of 35nm-gate-length MOSFETs using mechanical strained technologies (adapted from Ref.[1.12]).

Fig. 1.3 Schematic representation of the constant-energy ellipses for (a) and (b) unstrained Si and (c) and (d) strained Si. (a) and (c) are for a 3DEG in bulk Si. (b) and (d) are those of a 2DEG in a Si inversion layer. (e) and (f) are the schematic diagrams

Fig. 1.4 Simplified valence band E vs. k diagram for strained Si (adapted from Ref.[1.25]).

(a) 2-D dopant concentration contour plot

(b) Dopant profiles of lateral cut line in the 2D contour plot

Fig. 1.5 (a) Contour plot of simulated doping near resist mask edge. Both boron (intermediate and near-surface) and phosphorus (deep) implantations were simulated. (b) Simulated lateral doping profiles of B and P immediately below the silicon surfaces (adapted from Ref.[1.12]).

gate

pWell

source drain

Fig. 1.6 Simulated dopant distribution contours of a novel MOSFET using a TCAD tool (TSURPEM4).

gate

pWell

drain

source

0

100

200

300

400

500

600

0

0.2

0.4

0.6

0.8

1

1.2

drain voltage (volt)

dr

ai

n c

u

rr

ent

(

µ

A/

µ

m)

.

Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V

Fig. 1.7 Simulated (a) electrical current distribution contours and (b) output current-voltage plot of the MOSFET shown in Fig. 1.6.

Chapter 2

Dopant Diffusion Under Mechanical Stress

2.1 Preface

Shallow trench isolation (STI) induced mechanical stress increases in magnitude with reduced device active areas of highly scaled CMOS technology, causing a non-negligible impact on device performance [2.1]-[2.4]. Both experimental work and numerical simulations have been conducted to calculate the STI stress magnitude and distribution encountered in scaled MOSFETs [2.5]-[2.9]. The results show that the silicon stress level near the STI region is high. As design rules or layout dimensions scale down, the high-stress region encroaches further into the MOSFET channel. Thus, STI mechanical stress has a significant influence on state-of-the-art device performance.

Earlier work studying the mechanical stress effect has been focused on the MOSFET drive current shift, either in the form of localized or planar stress conditions [2.1]- [2.3], [2.6], [2.10]-[2.14]. Several studies have been performed to link STI mechanical stress to mobility changes while accounting for the observed current shift [2.2], [2.12], [2.13], although no threshold voltage shift mechanism has been investigated. G. Scott, et al. [2.14] have investigated both the drive current and threshold voltage shift, suggesting a difference in stress-induced diffusivity as the plausible origin of the threshold voltage shift. So far, however, there has been no further elaboration on this aspect. On the other hand, there has been a great deal of work devoted to dopant diffusion behavior in silicon under the influence of

mechanical stress [2.15]-[2.19]. Cowern, et al. [2.15] proposed a strain-induced dopant diffusivity model of boron diffusion in SiGe. S. T. Ahn, et al. [2.17] concluded that in the presence of high-stress nitride film, phosphorus diffusion in the silicon was retarded, whereas antimony diffusion was enhanced. Aziz [2.18] established a relationship between hydrostatic pressure and biaxial strain via thermodynamic formulation, while accommodating calculation of the activation energy shift due to strain. Based on Aziz’s and Cowern’s theoretical work [2.15], [2.18], Zangenberg, et al. [2.19] critically reviewed the findings over the past 10 years and further identified the strain effect on boron and phosphorus diffusion in SiGe. However, most studies in the area of mechanical stress induced dopant diffusion changes remain in fundamental research, i.e., at the silicon material level, and have not yet been extended to semiconductor device characterization and modeling.

It is well recognized that the key MOSFET parameters, such as threshold voltage, drain induced barrier lowering, body factor, and subthreshold swing, are all strongly dependent on dopant distribution details. Thus, it is crucial to examine stress-dependent dopant diffusion for scaled MOSFETs under mechanical stress.

In this chapter, a stress-dependent diffusion model and incorporate it into a two-dimensional process simulation environment to assess the doping distribution effect in scaled MOSFETs is presented. The proposed model is corroborated by extensive experimental data in a sub-100nm CMOS technology.

2.2 Stress-dependent Diffusion Model and Modeling Methodology

2.2.1 Model Description

The dopant diffusion change due to mechanical stress has been derived from point defect (interstitials and vacancies) changes[2.18]. Mechanical strain influences the point defect formation and migration, while the microscopic volume change and the pressure both contribute to the Gibb’s free energy change. Thus, the dopant diffusivity ratio with and without strain can be expressed in an Arrhenius form; and the strain-induced point defect energy change can be translated to the dopant diffusivity change. For example, in the case of a compressively strained SiGe layer where Cowern studied boron diffusion [2.15], the stress condition is regarded as biaxial and the dopant diffusion dependence follows the Arrhenius form







−

=

kT

sQ

D

D

_{S A}

exp

'

_(2.1)

where DS is the dopant diffusivity under strain, DA is the dopant diffusivity without strain, s is the biaxial strain in the plane of the SiGe layer, and is the activation energy per strain. The concept of this equation is consistent with experimental data [2.15], [2.18] and theoretical calculations 12) _{showing a linear deffect of the mechanical}

strain to dopant diffusivity ratios on a log scale. Recently, Diebel [2.20] studied stress-dependent point defect equilibrium concentration and diffusion by means of

ab initio calculations.

'

Analogous to equation (2.1), a stress dependent dopant diffusion model for dopant diffusion under STI mechanical stress, named Volume-change-ratio Induced Diffusion Activation Energy Shift Model (VIDAESM) is developed. The volume change ratio, Vcr, is a function of position due to non-uniform stress distributions. In this study, the MOSFET width is large enough to allow the three-dimensional stress effect to be reduced to the two-dimensional one. The activation energy involved is the product of a dopant dependent coefficient and volume change ratio, meaning that Eq. (2.1) can be re-written in the case of dopant diffusion under STI mechanical stress     ∆₋ = kT y x T V E T D y x T D S cr A S ) , , ( exp ) ( ) , , ( _(2.2)

where DS is the dopant diffusivity under strain, DA is the dopant diffusivity without strain, Vcr is the volume change ratio due to stress, ∆ES is the activation energy per volume change ratio depending on the dopant species, and T is the temperature. When the strain is small, the volume change ratio can be expressed as

zz yy xx t cr T x y T x y T x y T x y V ( , , )≅

ε

( , , )≡

ε

( , , )+

ε

( , , )+

ε

(2.3)

where εxx is the strain along the channel length direction, εyy is the strain in the direction perpendicular to the silicon surface, εzz is the strain along the channel width direction, and εt is the strain summation of εxx, εyy, and εzz. Note that εzz is zero in the two-dimensional simulation due to wide structures adopted. Therefore, Eq. (2.2)

becomes     ∆₋ = kT y x T E T D y x T D S t A S ) , , ( exp ) ( ) , , (

ε

(2.4)

A two-dimensional numerical process simulator, TSUPREM4, is chosen to perform the process simulation. TSUPREM4 is capable of simulating intrinsic dopant diffusion, three-stream dopant-point defect pairing diffusion, oxidation enhanced diffusion effect, dopant clustering effect, and dislocation loop effect. For assessment of mechanical stress, the simulator also simultaneously solves force balance equations while taking into account thermal expansion, intrinsic stress, geometry re-arrangement after etch and deposition processes, and the thermal oxidation process [2.21]. The stress-dependent diffusion model, VIDAESM, has been incorporated into the simulator through the user-specified equation interface to adaptively calculate stress-dopant diffusivity during the process simulation.

2.2.2 Modeling Methodology

To model stress-dependent dopant diffusion for various stress levels, a series of MOSFETs with various active area sizes are designed and fabricated. Fig. 2.1 schematically shows the cross section view of a test device along the channel direction. The mechanical stress effect was explored here with active area size, Xactive,

and gate length Lg, both used as the main structural parameters.

one-dimensional dopant profiles were processed using blanket control wafers, which covered the range of the process conditions of the device wafers. The results were then taken as stress-free dopant profiles and used to calibrate the dopant diffusion parameters without stress-dependent models.

Secondly, two-dimensional MOSFET structures were simulated using the mechanical stress model. Calibrated diffusion parameters were employed to simulate a large Xactive MOSFET, where the stress level is low. All front-end major

process steps from the STI to the source/drain anneal were considered. The corresponding simulation geometries were calibrated using TEM cross-sectional images. Some fine-tunings of two-dimensional dopant profile parameters, such as implant lateral straggles and segregation factors, are needed to fit the silicon device I-V characteristics. Fig. 2.3 shows the calibration result of a short channel nMOSFET I-V with a large Xactive.

Next, with the stress distribution known, the stress-dependent diffusion models were introduced to simulate MOSFETs with varying Xactive values. After

implementing the stress-dependent diffusion model, process simulation results were used as device simulation inputs. MEDICI was chosen as the numerical device simulator. The device modeling parameters, such as carrier mobility, work function, and silicon/oxide interface charges were calibrated to fit the I-V of large Xactive

MOSFETs. Then, device simulations with various Xactive values were performed and

compared with silicon device data. The above procedure was iterated from process to device cycle until the current-voltage data was all satisfactorily reproduced in all

cases. The ∆ES values from the previous work [2.15] were employed as the initial guess values. It is worth noting that the numerical convergence and simulation speed were not greatly influenced after implementing VIDAESM. The simulation time incorporating VIDAESM increases by about 7% compared to that without VIDAESM.

2.2.3 Experiment on MOSFET Threshold Voltages and Modeling Results

The silicon wafers were fabricated using novel CMOS processes. The control wafers for one-dimensional SIMS analysis were processed using the same thermal steps as device wafers. Fig. 2.4 displays SIMS results for both n and pMOSFET. The implant conditions were BF2 2keV 1×1015cm-3 and As 2keV 1×1015cm-3 for ultra

shallow junction calibration and the junction depths are around 260 angstroms for both devices by taking the substrate doping as 2×1018_cm-3_{. The calibrated}

simulation profile is also plotted in Fig. 2.4. The calibration procedure included the fine-tuning of implant damage, dopant-point defect pairing diffusion, silicon-oxide dopant segregation, oxidation enhanced diffusion models, dopant clustering models, dopant-defect clustering models, and intrinsic diffusion models.

The stress simulation involved the main process steps, which are STI formation, gate oxidations, and poly-gate formation in sequence. Viscoelastic oxidation model was used to simulate the stress dependent oxide growth. The Young’s moduli used were 1.87×1012_dyne/cm2 _{for the silicon and 6.6×10}11_dyne/cm2 _{for the oxide layers.}

for gate spacer oxide. The other parameters follow the default values in the TSUPREM4 manual [2.21]. The stress distribution results for different Xactive values

are given in Fig. 2.5. It can be seen that the polarity of the strain εxx in the lateral

direction is negative, meaning that the MOSFET core area experiences a compressive stress. On the other hand, strain εyy in the vertical direction is tensile with a

magnitude much smaller than εxx. In particular, Fig. 2.5(b) reveals that εxx drastically

increases in magnitude with decreasing Xactive values. Three reference points A, B,

and C are chosen to inspect the value of the strain. A is at the center of the gate, B is 75nm away from the gate center and C is 150nm from the gate center. The depth of these points is 20nm from the silicon surface. Fig. 2.6 highlights the magnitude of the strain versus the Xactive value at points A, B, and C in Fig. 2.5. The negative

polarity of the strain means that the general strain conditions in the active area are compressive, and the magnitude increases rapidly as value of Xactive decreases. The

compressive stress mainly comes from lower thermal expansion rate of the STI oxide compared to silicon, and the thermal gate oxidation induced volume expansion at the STI edge. As Xactive decreases, the STI approaches the MOSFET core region and

increases the magnitude of compressive stress. The strain at rapid thermal peak temperature remains compressive and the magnitude is about 0.15% at the MOSFET core region for the minimum Xactive case.

The MOSFET channel width in the silicon experiment was fixed at 10µm, large enough to ensure that the stress along the channel width direction is negligible. Simulations were conducted to evaluate the mechanical stress along the channel

width direction. The results showed that the average strain level for channel width W=10µm is around -0.02%, which is at least two order of magnitude lower than the peak strain level used in this study. The MOSFET design set consisted of Xactive

values from 0.6µm to 10µm and Lg from 65nm to 0.42µm. It has been recognized

that boron and phosphorus diffusion are retarded by compressive strain [2.15], [2.19], [2.22]. The stress simulation results show that the MOSFET channel stress and strain magnitudes for Xactive=10µm are around -1×108 dyne/cm2 and –0.04%,

respectively. As the Xactive value shrinks to 0.6µm, the corresponding stress and

strain magnitudes become around -5×109 _dyne/cm2 _{and -0.4%, respectively. The}

compressive strain level in the channel region is quite close to the strain produced by 10% germanium in silicon, which falls within the range of Cowern’s and Zangenberg’s studies [2.15], [2.19].

In the present work, the impurities introduced to form nMOSFET are boron, indium, arsenic and phosphorus, while pMOSFET employed boron and arsenic. Boron, arsenic and phosphorus were all retarded by STI stress as encountered in fitting the silicon MOSFET I-V data. Indium was not considered as a fitting variable because it was observed to be almost immobile during the thermal process, meaning that dopant profile change due to mechanical stress would hardly be observed. As will be mentioned later, the nMOSFETs threshold voltage was observed to increase as the Xactive value decreases. The subthreshold I-V with a low drain bias is strongly

dependent on the accurate doping profile of the MOSFET shallow core region, which is mainly related to arsenic source/drain extension doping and boron halo doping.

In high drain bias cases, the subthreshold I-V depends significantly on the deeper part of the MOSFET doping profile, which is related to phosphorus source/drain, indium halo, and boron halo tail doping profiles. As the gate length varies, the extent of the superposition of tilt-implanted halo doping varies accordingly. Moreover, as the substrate bias increases in magnitude, the depletion region further extends into the substrate from the source, channel and drain regions, considerably influencing subthreshold I-V characteristics. Thus, biasing the MOSFET substrate can serve as a means of verification for the stress-dependent diffusion model. Fig. 2.7 shows the depletion region boundaries of a 65nm nMOSFET for low and high drain voltages.

After numerical iterations were completed, the effects of gate lengths, gate voltages, drain voltages, and substrate biases simultaneously matched with the nMOSFET subthreshold I-V data. This is sufficient to claim that the resulting dopant distributions for the whole device core region are correct. To assess the creditability of this model, device I-V simulations with and without VIDAESM were performed and compared. Fig. 2.8 shows the detailed I-V comparison for a small

Xactive MOSFET with and without VIDAESM. In the absence of VIDAESM, the

simulation fails to correctly describe the I-V dependency on Xactive. Fig. 2.9 displays

a series of comparisons with measured gate voltage at different drain current levels for different combinations of gate lengths, active area sizes, drain voltages, and substrate biases. Remarkably, the extracted diffusion parameter set is able to reproduce all the silicon data well. The broad range of gate lengths, active areas,

drain voltages and substrate biases employed in this experiment confirm that the VIDAESM model is indeed suited for modeling the mechanical stress effect on scaled MOSFETs. To further ensure the extracted parameter set also valid for pMOSEFTs, threshold voltage dependence on Xactive is simulated and compared with silicon data

for both nMOSFETs and pMOSFETs. Fig. 2.10 shows the final results. The threshold voltage is defined by using constant drain current method. The strain effect is estimated to have less 10% drain current variations for Lg=65nm MOSFETs,

which causes less then 4mV variations. It can be seen that the nMOSFET threshold voltage increases with decreasing Xactive values while pMOSFET threshold voltage is

relatively insensitive to Xactive. The trends for both nMOSFETs and pMOSFETs are

adequately described by the extracted parameter set.

Finally, Table I lists the extracted ∆ES values for all impurities involved. The ∆ES for phosphorus is -30eV per volume shift ratio and is largest among the impurities. The ∆ES for arsenic is -14eV per volume shift ratio, whereas the ∆ES for boron is -7eV. These coefficients confirm diffusion retardation by the compressive stress in pure silicon, excluding the Ge chemical effect in strained SiGe experiments. Fig. 2.11 illustrates the two-dimensional contour of the nMOSFET net doping concentration for a gate length of 65nm. As shown in the figure, for Xactive=10µm,

the dopant contours with and without the stress-dependent model are comparable, while the source/drain junction for Xactive=0.6µm is significantly shallower and

effective gate length is longer in the MOSFET core region when the stress-dependent diffusion model is introduced. To more clearly visualize the effect of the

stress-dependent model, one can inspect the dopant profile along specific cut-lines. Fig. 2.12 and 2.13 displays corresponding vertical and lateral doping profiles for a 65nm gate length nMOSFET with Xactive as a parameter. As can be seen, significant

dopant diffusion retardation prevails at small Xactive values and this explains an

increase in threshold voltage as the Xactive decreases.

2.3 Experiment on MOSFET Subthreshold Leakage with

Stress-Dependent Transient–Enhanced-Diffusion Effect Included

This work has been conducted to corroborate the validity of the STI mechanical stress-dependent diffusion model mentioned in section 2.2 using a MOSFET device with an underlying lightly doped well, which exhibits a significant mechanical stress effect on the subthreshold I-V characteristics. The stress-dependent point defect equilibrium concentration and diffusion, which dominates the transient enhanced diffusion (TED), has also been taken into account.

The results of Diebel’s study [2.20] also show a linear dependence of both point defect equilibrium concentration and diffusivity in a log scale on the mechanical strain. Thus, it is reasonable to express the point defect equilibrium concentration and diffusion in an Arrhenius form:







 ∆

₋

=

kT

y

x

T

E

T

C

y

x

T

C

C t A S

)

,

,

(

exp

)

(

)

,

,

(

* *

ε

(2.5)

where is the point defect equilibrium concentration under strain. To investigate the transient enhanced diffusion, only strain-dependent interstitial diffusion is needed. ∆EC for the vacancy extracted from calculation results[2.20] is +7.9eV/unit strain. Extracted ∆EC and ∆ES (in Eq. (2.5)) values for the interstitial are –7.0 and +0.99eV/unit strain, respectively. Furthermore, interstitial diffusivity and equilibrium concentration product, , is reduced under the compressive strain conditions. Two-dimensional process/device simulators, TSUPREM4 and MEDICI, were employed. The stress-dependent diffusion models were incorporated into TSUPREM4 through its user-specified equation interface.

* S C * I IC D

A series of n-channel MOSFETs were fabricated using state-of-the-art process technology. Test structures had three active area length (Xactive in Fig. 2.1) values:

0.68µm, 1.46µm, and 20.2µm. Xactive is the design parameter to modulate mechanical

stress. The minimum Xactive dimension of 0.68µm takes the presence of one contact

window area in the source/drain into account. The gate length and width were 0.17µm and 10µm, respectively. The retrograde well implantations are omitted so as to enhance the sensitivity of the subthreshold characteristics to STI mechanical stress, offering the opportunity to verify the validity of the above mentioned diffusion model. The measured subthreshold I-V characteristics at VD = 1.2V are depicted in

Fig. 2.13, with the substrate bias as a parameter. Previous work [2.23] revealed that the substrate bias measurement is a suitable verification index of the MOSFET doping profile because of the high sensitivity of carrier diffusion current to the dopant profile. The procedure for obtaining ∆ES values for various impurities began

by calibrating the one-dimensional dopant profiles in blanket control wafers, using processes that covered the range of device wafer process conditions. The results were taken as stress-free dopant profiles and used to calibrate the dopant diffusion parameters without considering stress-dependent diffusion effect. Two-dimensional MOSFET structures were then simulated in conjunction with the mechanical stress model. Calibrated diffusion parameters were employed to simulate a large Xactive

case, where the stress level is negligible. All major front-end process steps from the STI to the source/drain anneal were considered. The corresponding simulation geometries were calibrated using TEM cross-sectional images. Device simulations were performed and the device model parameters were calibrated to fit the I-V of the large Xactive MOSFET. Next, the process simulations based on VIDAESM for all

Xactive values were conducted with an initial set of ∆ES values. Then, the device

simulations with smaller Xactive values were performed and compared with the I-V

data. The above procedure was iterated until a satisfactory reproduction of subthreshold I-V data was achieved in all cases.

The simulated strain distribution results for Xactive = 0.68µm are given in Fig.

2.14. It can be seen that the magnitude of the total strain, or volume change ratio, (εxx+εyy), is negative in the MOSFET core area, meaning that the device experiences

compressive stresses during the process. In addition, the (εxx+εyy) of Xactive =

0.68　m was found to be much larger in magnitude than Xactive = 20.2µm. The

compressive stress stems mainly from the lower thermal expansion rate of the STI oxide when compared to silicon, as well as the thermal gate oxidation induced

volume expansion at the STI edge. Thus, as Xactive decreases, the STI approaching the

MOSFET core region increases the magnitude of the compressive stress. The extracted the ∆ES for phosphorus, arsenic and boron in the last section are –30, –14, and –7 eV/unit strain, respectively. The negative sign of ∆ES denotes diffusion retardation caused by the compressive stress in pure silicon for these impurities, and is in agreement with the literature [2.15],[2.19],[2.22]for boron and phosphorus. Note that, so far, no conclusive argument has been reached regarding the arsenic diffusion behavior under a general non-uniformly compressive stress in pure silicon.

In the MOSFET structure used in this section, source and drain phosphorus diffusion is much more sensitive to the mechanical stress than boron and arsenic because of the absence of the high concentration retrograde P-type doping well. The experimental silicon and simulation results are shown in Fig. 2.13 and Fig. 2.15. In the absence of the VIDAESM, the simulated leakage current (that is, the flat region in Fig. 2.14) was found to be much higher for MOSFETs with smaller Xactive values as

illustrated in dashed lines in Fig. 2.13. The ID value for Xactive= 1.46 µm at VB = −1 V

and VG = −0.4 V is 2.5×10−10A/µm without using VIDAESM, which is much larger

than the result obtained using VIDAESM (6.3×10−11A/µm). The corresponding silicon experimental data is 5.6 ×10−11A/µm. The simulations that incorporated VIDAESM revealed that the punchthrough between the deeper part of the phosphorus source and drain is responsible for the leakage current. This means that the dopant diffusion becomes less as Xactive is decreased, and is consistent with the results indicated in Fig.