Recommendations for Future Work

The mechanical stress has become a major strategy for MOSFETs scaling in the advanced CMOS technologies. In this work, the isotropic stress-dependent diffusion model and anisotropic diffusion derivation for uniaxial stress cases have been developed and are sufficient to explain the experimental data. However, even stronger anisotropic stress can be expected in future technologies, and then a generalized anisotropic stress-dependent diffusion model for arbitrary stress conditions and the experiment designed for extracting the stress-dependent activation energies is necessary.

More mechanical stress simulations and analyses other than STI and oxidations, such as, silicon germanium/silicon carbon source and drain, strained cap layers and damascene gate are good topics for further studies on MOSFET performance improvements. Analytical stress-mobility models and stress induced band edge shift models can be implemented into the device simulators for more precise analyses on the stress induced MOSFEST on-state characteristics.

More boundary dopant scattering effects of the ion implantations other than

well formation ion implantations can be explored in the future. This topic can be combined with random dopant concentration fluctuation effects since the device scaling leads to limited counts of dopant atoms in a scaled MOSFET.

As the devices continued scaled, three dimensional (3-D) dopant diffusion, mechanical stress, and the boundary dopant scattering effects will also be more pronounced and need to be taken into considerations for the device design.

Meanwhile, the three dimensional capability of TCAD tools needs to be improved on the numerical solving issues.

Vita (博士候選人學經歷表)

姓 名: 許義明 Yi-Ming Sheu

性 別: 男

出生日期: 1968 . 1 . 27 出 生 地: 台灣新竹

學 歷: 國立成功大學材料系學士畢業

國立中央大學光電研究所碩士畢業

國立交通大學電子工程研究所固態組

經 歷: 華昕電子研發工程師

台灣積體電路製造公司製程整合工程師

台灣積體電路製造公司研發工程師

台灣積體電路製造公司研發副理

Publication list

1. ( 1 點 ) Y. M. Sheu, Kelvin Y. Y. Doong, C. H. Lee, M. J. Chen, and C. H. Diaz,

“Study on STI mechanical stress induced variations on advanced CMOSFETs,” in Proc. of ICMTS, Mar. 2003, pp. 205-208.

2. Y. M. Sheu, C. S. Chang, H. C. Lin, S. S. Lin, C. H. Lee, C. C. Wu, M. J. Chen, and C.

H. Diaz, “Impact of STI mechanical stress in highly scaled MOSFETs,” in Int. Symp.

VLSI-TSA, Oct. 2003, pp. 269-272.

3. K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K. Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc. of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.

4. C. C. Wu, Y. K. Leung, C. S. Chang, M. H. Tsai, H. T. Huang, D. W. Lin, Y. M. Sheu, C. H. Hsieh, W. J. Liang, L. K. Han, W. M. Chen, S. Z. Chang, S. Y. Wu, S. S. Lin, H. C.

Lin, C. H. Wang, P. W. Wang, T. L. Lee, C. Y. Fu, C. W. Chang, S. C. Chen, S. M. Jang, S. L. Shue, H. T. Lin, Y. C. See, Y. J. Mii, C. H. Diaz, Burn J. Lin, M. S. Liang, Y. C. Sun,

“A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications,” in IEDM Tech. Dig., Dec.

2002, pp. 65-68.

5. K. W. Su, K. H. Chen, T. X, Chung, H. W. Chen, C. C. Huang, H. Y. Chen, C. Y.

Chang, D. H. Lee, C. K. Wen, Y. M. Sheu, S.J. Yang, C. S. Chiang, C. C. Huang, F. L.

Yang, Y. T. Chia, “Modeling Isolation-induced Mechanical Stress Effect on SOI MOS

6. C.C. Wang, T.Y. Huang, Y. M. Sheu, Ray Duffy, Anco Heringa, N.E.B. Cowern, Peter B. Griffin, Carlos H. Diaz, “Boron diffusion in strained and strain-relaxed SiGe,” SISPAD 2004, pp. 41-44.

7. Fu-Liang Yang, Chien-Chao Huang, Hou-Yu Chen, Jhon-Jhy Liaw, Tang-Xuan Chung, Hung-Wei Chen, Chang-Yun Chang, Cheng-Chuan Huang, Kuang-Hsin Chen, Di-Hong Lee, Hsun-Chih Tsao, Cheng-Kuo Wen, Shui-Ming Cheng, Yi-Ming Sheu, Ke-Wei Su, Chi-Chun Chen, Tze-Liang Lee, Shih-Chang Chen, Chih-Jian Chen, Cheng-Hung Chang, Jhi-Cheng Lu, Weng Chang, Chuan-Ping Hou,Ying-Ho Chen, Kuei-Shun Chen, Ming Lu, Li-Wei Kung, Yu-Jun Chou, Fu-Jye Liang, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Bor-Wen Chan, Yi-Chun Huang, Han-Jan Tao, Jyh-Huei Chen, Yung-Shun Chen, Yee-Chia Yeo, Samuel K-H Fung, Carlos H. Diaz, Chii-Ming M. Wu, Burn J.

Lin, Mong-Song Liang, Jack Y.-C. Sun, and Chenming Hu, “A 65nm Node Strained SOI Technology with Slim Spacer,” in IEDM Tech. Dig., Dec. 2003, pp. 627-630.

8. J. R. Shih, Y. M. Sheu, H. C. Lin and Ken Wu “Pattern Density Effect of Trench Isolation-Induced Mechanical Stress on Device Reliability in sub-0.1um Technology,”

IRPS 2004, pp.489-492.

9. ( 3 點 ) Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling Mechanical Stress Effect on Dopant Diffusion in Scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 30-38, January 2005.

10. Yi-Ming Sheu, Tsung-Yi Huang, Yu-Ping. Hu, Chih-Chiang Wang, Sally Liu, Ray Duffy, Anco Heringa, Fred Roozeboom, Nick E. B. Cowern, and Peter B. Griffin,

“Modeling Dopant Diffusion in Strained and Strain-Relaxed Epi-SiGe,” SISPAD 2005, pp. 75-78.

11. Yi-Ming Sheu, Ke-Wei Su, Sheng-Jier Yang, Hsien-Te Chen, Chih-Chiang Wang, Ming-Jer Chen, and Sally Liu, “Modeling well edge proximity effect on highly-scaled MOSFETs,” Custom Integrated Circuits Conference, 2005, pp. 826–829.

12. C. C. Wang, Y. M. Sheu, Sally Liu, R. Duffy, A. Heringa, N. E. B. Cowern, P.B.

Griffin, “Boron diffusion in strained and strain-relaxed SiGe,” Materials Science and Engineering B 2005, pp. 39-44.

13. ( 1 點 ) Yi-Ming Sheu, Sheng-Jier Yang, Chih-Chiang Wang, Chih-Sheng Chang, Ming-Jer Chen, Sally Liu and Carlos H. Diaz, “Reproducing Subthreshold characteristics of metal-oxide-semiconductor field effect transistors under Shallow Trench Isolation Mechanical Stress Using a Stress-Dependent Diffusion Model,” J.

Jap Appl. Phys., Vol. 45, No. 32, pp. L849–L851, August 2006.

14. K. C. Ku, C. F. Nieh, L. P. Huang, Y. M. Sheu, C. C. Wang, C. H. Chen,H. Chang, L. T. Wang, T. L. Lee, S. C. Chen, M. S. Liang, and J. Gong, "Effects of germanium and carbon co-implants on phosphorus diffusion in silicon," Appl. Phys. Lett, vol. 89, pp.

112104-1–112104-3, September 2006.

15. ( 3 點 ) Yi-Ming Sheu, Ke-Wei Su, Shiyang Tian, Sheng-Jier Yang, Chih-Chiang Wang, Ming-Jer Chen, and Sally Liu, “Modeling the well-edge proximity effect in highly-scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp. 2792-2798, November 2006.

16. ( 3 點 ) Ming-Jer Chen, and Yi-Ming Sheu, “Effect of uniaxial strain on

anisotropic diffusion in silicon,” Appl. Phys. Lett., vol. 89, pp. 161908-1–161908-1, October 2006.

17. C. F. Nieh, K. C. Ku, C. H. Chen, H. Chang, L. T. Wang, L. P. Huang, Y. M. Sheu, C. C. Wang, T. L. Lee, S. C. Chen, M. S. Liang, J. Gong, “Millisecond anneal and short-channel effect control in Si CMOS transistor performance,” Electron Device Lett., vol. 27, pp.969–971, December 2006.

18. Ming H. Yu, J. H. Li, H. H. Lin, C. H. Chen, K. C. Ku, C. F. Nie, H. K. Hisa, Y. M.

Sheu, C. W. Tsai, Y. L. Wang, H. Y. Chu, H. C. Cheng, T. L. Lee, S. C. Chen, and M. S.

Liang, “Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond,” in IEDM Tech. Dig., Dec. 2006, pp. 867-871.

共 11 點

Yi Ming Sheu Patent Filing List:

U.S.A. patent list:

1. Method of forming a self-aligned twin well structure with a single mask Inventor: SHEU YI-MING (TW); YANG FU-LIANG (TW)

Applicant: TAIWAN SEMICONDUCTOR MFG Patent no. US6703187.

2. Planarizing method for fabricating gate electrodes

Inventor: LIN YO-SHENG (TW); SHEU YI-MING (TW); LIN DA-WEN (TW); HSIEH CHI-HSUN (TW)

Applicant: TAIWAN SEMICONDUCTOR MFG Patent no. US6670226.

3. Electrostatic discharge device protection structure

Inventor: CHAN YI-LANG (TW); YANG FU-LIANG (TW); SHEU YI MING (TW) Applicant: TAIWAN SEMICONDUCTOR MFG

Patent no. US6800516.

4. Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions

Inventor: SHEU YI-MING (TW); CHAN YI-LING (TW); LIN DA-WEN (TW); LIEN WAN-YIH (TW); DIAZ CARLOS H (TW)

Applicant: TAIWAN SEMICONDUCTOR MFG Patent no. US6673683.

5. Damascene gate electrode method for fabricating field effect transistor (FET)

device with ion implanted lightly doped extension regions

Inventor: DIAZ CARLOS H (US); SHEU YI-MING (TW); JANG SYUN-MING (TW);

TAO HUN-JAN (TW); YANG FU-LIANG (TW) Applicant: TAIWAN SEMICONDUCTOR MFG Patent no. US6974730.

6. Narrow width effect improvement with photoresist plug process and STI corner ion implantation

Inventor: SHEU YI-MING (TW); LIN DA-WEN (TW); CHEN CHENG-KU (TW);

YEH PO-YING (TW); PENG SHI-SHUNG (TW); WU CHUNG-CHENG (TW) Applicant: TAIWAN SEMICONDUCTOR MFG

Patent no. US7071515.

7. Recessed gate structure with reduced current leakage and overlap capacitance Inventor: LIN DA-WEN (TW); SHEU YI-MING (TW); LEUNG YING-KEUNG (HK) Applicant: TAIWAN SEMICONDUCTOR MFG

Patent no. US7012014.

中華民國專利：

1. 第 33 卷 31 期－公告編號 公告日期：95 年 11 月 01 日

專利名稱：積體電路裝置、半導體裝置及其製造方法

申請單位：台灣積體電路製造股份有限公司

申請案號：093136129 申請日期：93 年 11 月 24 日 專利證書號：I265638

發明人：鄭水明 、馮家馨 、程冠倫、許義明

2. 第 33 卷 15 期－公告編號 公告日期：95 年 05 月 21 日

專利名稱：電晶體元件與其形成方法及互補式金氧半元件的製造方法 申請案號：093102910 申請日期：93 年 02 月 09 日 專利證書號：I255530 申請單位：台灣積體電路製造股份有限公司

發明人：許義明、吳忠政

3. 第 33 卷 10 期－公告編號 公告日期：95 年 04 月 01 日 專利名稱：具有低電流洩漏及重疊電容之嵌壁式閘極結構

申請案號：093137422 申請日期：93 年 12 月 03 日 專利證書號：I252583 申請單位：台灣積體電路製造股份有限公司

發明人：林大文、許義明、梁英強

4. 第 31 卷 30 期－公告編號 公告日期：93 年 10 月 21 日 專利名稱：降低反窄通道效應之淺溝渠隔離製程

申請案號：092113971 申請日期：92 年 05 月 23 日 專利證書號：222701 申請單位：台灣積體電路製造股份有限公司

發明人：許義明、林大文、陳政谷、葉柏盈、彭世熊、吳忠政

5. 第 31 卷 04 期－公告編號 574746 公告日期：93 年 02 月 01 日 專利名稱：具凹陷通道之金氧半場效應電晶體之製造方法

申請單位：台灣積體電路製造股份有限公司

發明人：卡羅司、許義明、章勳明、陶宏遠、楊富量

6. 第 31 卷 01 期－公告編號 569346 公告日期：93 年 01 月 01 日 專利名稱：在無邊界接觸窗製程中形成蝕刻終止層之方法

申請案號：091122713 申請日期：91 年 10 月 02 日 專利證書號：193690 申請單位：台灣積體電路製造股份有限公司

發明人：傅竹韻、謝奇勳、許義明、章勳明

7. 第 30 卷 32 期－公告編號 561506 公告日期：92 年 11 月 11 日 專利名稱：金氧半場效電晶體的製造方法

申請案號：091116299 申請日期：91 年 07 月 22 日 專利證書號：192142 申請單位：台灣積體電路製造股份有限公司

發明人：許義明、詹宜陵、林大文、連萬益、卡羅司

8. 第 30 卷 12 期－公告編號 529152 公告日期：92 年 04 月 21 日 專利名稱：汲極內具有缺陷區之靜電放電保護結構及其製造方法

申請案號：091100994 申請日期：91 年 01 月 22 日 專利證書號：176409 申請單位：台灣積體電路製造股份有限公司

發明人：詹宜陵、楊富量、許義明

9. 第 29 卷 31 期－公告編號 508727 公告日期：91 年 11 月 01 日

專利名稱：形成淺溝槽隔離結構之方法

申請案號：090122991 申請日期：90 年 09 月 19 日 專利證書號：166780 申請單位：台灣積體電路製造股份有限公司

發明人：陳方正、許義明、陶宏遠、邱顯光、張銘慶

10. 第 29 卷 26 期－公告編號 502315 公告日期：91 年 09 月 11 日 專利名稱：具有不同摻質之複晶矽層的製作方法

申請案號：090125933 申請日期：90 年 10 月 19 日 專利證書號：163288 申請單位：台灣積體電路製造股份有限公司

發明人：林佑昇、謝奇勳、許義明、林大文