Chapter 4 Well-Edge Proximity Effect
4.4 Compact Model for SPICE
Since this new layout-dependent phenomenon increases the threshold voltage and thus decreases the drain current of the MOSFETs, it is especially important for those circuits with high integration density. This effect might also introduce uncertainties to those circuits that are sensitive to the matching of threshold voltage.
Therefore, it is necessary to consider this effect in the SPICE simulation and the post-layout extraction flow. However, the most challenging part of a layout-dependent model is to determine a method of catering for various layout styles in as complete a manner as possible while retaining the efficiency of the procedure.
Fig. 4.7 shows typical several layout styles of a MOSFET in a well. As shown in Fig. 4.7(a) and (b), the well edges are close to the MOSFETs in the channel-length direction, and in Fig. 4.7(c) and (d) the proximity occurs in the channel-width direction. Narrow MOSFETs will have a strong well-edge proximity effect for layout (c) and (d) as a large portion of the channel region is influenced by the dopant ion scattering at the well edge. However, the MOSFET channel width does not play an
important role in layout (a) and (b). A useful compact model should cover each of these possibilities.
Fig. 4.8 is another generalized example to cover various layout conditions, including those shown in Fig. 4.7. From Fig. 4.8, the overall additional dose of dopant introduced by ion scattering at the well edges and that affect the channel region can be represented by the following integrals:
where f(x) is used to account for both the lateral and vertical distribution variations of the scattered well dopants. In some cases, f(x) might be a combination of several exponential terms. However, our analysis shows that 1/x2 is a good approximation for f(x) to cover most conditions. With this approximation, an effective device-to-well-edge distance, SCeff, is proposed:
5
Note that the SCeff can easily summarize all four conditions shown in Fig. 4.7.
A smaller SCeff indicates that the MOSFET is closer to the well edge and the well-edge proximity effect will be more severe. Then, the impact of the well-edge proximity effect can be described by adding more SCeff-dependent equations to the conventional model. Since the major effect is due to the MOSFET dopant profile change, three corresponding MOSFET parameters, threshold voltage, body effect coefficient, and carrier mobility, are modified to include the variations caused by this effect. The respective equations are shown as follows:
where Vth0 is the threshold voltage of the MOSFET, K2 is the body effect parameter, and the µeff is the effective carrier mobility. SCeff is the effective distance from the well edge to the channel region, which can be extracted from circuit layouts for each MOSFET by the layout parameter extraction (LPE) tools using equation (4.4).
SCREF, SC0, KVTH0WE, K2WE, KU0WE, and NWE are the fitting parameters.
This model has been verified using various types of MOSFET layout patterns,
as shown in Fig. 4.7. Devices with different channel lengths and widths are also considered here in order to check the dependence of the well-proximity effect on W and L. Fig. 4.9, Fig. 4.10 and Fig. 4.11 show the comparison between the model and the silicon for the threshold voltage shift, drive current degradation, and body effect increase of MOS transistors. As shown in these plots, the correlation between the model and the silicon is quite reasonable. Note that no matter whether the device is close to the well edge either in the channel length or in the width direction, the concept of SCeff can explain those differences and thus the data obtained from layouts illustrated in Fig. 4.7 show the same trend in the threshold voltage change (dVth) vs.
SCeff plot, as indicated in fig. 4.9. For those devices with smaller SCeff, the threshold voltage will also increase further, but it may saturate at a certain value.
Fig. 4.10 shows the drive current degradation induced by the well-edge proximity effect. When SCeff becomes smaller, the threshold voltage increases and thus the drive current will decrease. In addition to the Vth change, our analysis shows that the effective mobility is also degraded by the well-edge proximity effect. This is because the impurity scattering becomes more severe as the dopant concentration increases. Fig. 4.11 demonstrates the dependence of the body effect on the well-proximity effect. When SCeff is small, the average doping density in the channel region will increase. Then the body effect (gamma) will become higher at the same time. The model is able to predict this change.
References
[4.1] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., Dec. 1999, pp. 827-830.
[4.2] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117-120.
[4.3] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K.
Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc.
of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
[4.4] T. B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R.
Mann, “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans.
Electron Devices, vol. 50, pp. 1946-1951, September 2003.
[4.5] S. Tian, “Predictive Monte Carlo ion implantation simulator from sub-keV to above 10 MeV”, J. Appl. Phys., vol. 93, pp. 5893-5904, May 2003.
[4.6] J. F. Ziegler, J. P. Biersack, and U. Littmark, “The Stopping and Range of Ion in Solids”, Pergamon, New York, 1985.
[4.7] J. Lindhard and M.Scharff, “Energy Dissipation by Ions in the keV region”, Phys. Rev., vol. 124, pp. 128-130, October 1961.
High-energy ions
gate
SC
substrate
STI well
photoresist
Fig. 4.1 Origin of well edge proximity effect. High-energy dopant ions scatter at the well photoresist edge during the well ion implantation and the scattered ions are implanted in the MOSFET channel before the gate is formed. SC denotes the distance of well-photoresist edge to MOSFET gate edge.
Fig. 4.2 (a) Angular and (b) depth distributions of the ions scattered out of the photoresist edge for B 300 keV and P 625 keV implants. The angle is measured from the incident direction, and the depth is the vertical distance from the top surface of the photoresist to the point where the ion exits from the photoresist edge.
10X 10X
10X
10X 10X
10X
SC=0.9µm SC=0.54µm
SC=0.4µm
STI
NWell
STI
NWell
STI
NWell STI
PWell STI
PWell STI
PWell
SC=0.54µm SC=0.9µm
SC=0.4µm Well PR
Fig. 4.3 TCAD simulated dopant distribution versus well to gate edge distance, SC.
The well dopant distributions are influenced by the SC value. When SC decreases, extra well dopant clusters move toward the center of the active area.
0 10 20 30 40 50 1015
1016 1017 1018
phosphorus (cm-3 )
depth (nm) p-MOSFET
SC=0.54µm SC=0.9µm SC=0.4µm
0 10 20 30 40 50
1015 1016 1017 1018
boron (cm-3 )
depth (nm) n-MOSFET
SC=0.54µm SC=0.9µm SC=0.4µm
Fig. 4.4 TCAD simulated vertical channel dopant profile versus well to gate edge distance, SC. The channel dopant concentration increases as the well photoresist edge approaches the MOSFET active area.
0.1 1 10 3.4x1017
3.6x1017 3.8x1017 4.0x1017 4.2x1017 4.4x1017 4.6x1017
boron (cm-3 )
SC (µm)
0.1 1 10
0.0 2.0x1016 4.0x1016 6.0x1016 8.0x1016 1.0x1017 1.2x1017
phorphorus (cm-3 )
SC (µm)
Fig. 4.5 TCAD simulated average dopant concentration for the area 20nm below the MOSFET gate versus SC.
TCAD simulation Silicon data
-10 0 10 20 30 40 50
0.1 1 10
n-MOSFET
∆Vth (mV)
SC (µm)
-10 0 10 20 30 40 50
0.1 1 10
p-MOSFET
∆Vth (mV)
SC (µm)
Fig. 4.6 MOSFET threshold voltage shift versus well to gate edge distance of the silicon experimental and TCAD simulated results for n and pMOSFET.
Lg=0.216µm.
MOS
Well
(c) (a)
MOS
Well
Well (b)
Well (d) MOS
MOS
Fig. 4.7 Typical layouts showing different positions of MOS transistors in a well.
SC6
SC5
L L6
SC4 SC3
W4 W3
L7=L
SC7 W2 SC2
SC1
W1
Well
OD
PO
Fig. 4.8 Schematic presentation of a MOSFET layout and parameters used to establish a well-edge proximity SPICE model.
0.001 0.010 0.100 1.000
0.1 1 10
SCeff (µm)
Vth_gm shift (V)
model
W/L=0.9µm/0.216µm W/L=0.27µm/0.216µm W/L=0.6µm/0.24µm
Fig. 4.9 Model verification results of the MOSFET threshold voltage shift compared to the silicon experiment data.
1%
10%
100%
0.1 1 10
SCeff (µm) Id_sat degradation (%)
model (both Vth and U0 shift) model (Vth shift)
W/L=0.9µm/0.216µm W/L=0.27µm/0.216µm W/L=0.6µm/0.24µm
Fig. 4.10 Model verification results of the MOSFET drive current degradation compared to the silicon experiment data.
1%
10%
100%
0.1 1 10
SCeff (µm)
Gamma shift (%)
model
W/L=0.9µm/0.216µm W/L=0.27µm/0.216µm W/L=0.6µm/0.24µm
Fig. 4.11 Model verification results of the MOSFET body effect change compared to the silicon experimental data.
Chapter 5
Summary and Future Work 5.1 Summary
This dissertation concerns the accomplishment of exploring and modeling of two main layout dependent effects- mechanical stress and boundary dopant scattering during ion implantations on the modern MOSFETs.
The mechanical stress dependent dopant diffusion phenomenon is investigated through the wafer experiments using the sub-100nm CMOS technologies. An accurate stress-dependent dopant and point defects diffusion model is proposed.
The model has been implemented into process and device simulators and has been validated by the extensive experimental data. A complete set of MOSFET devices with various gate lengths and active areas have been designed and fabricated from state-of-the-art sub-100nm process for model verification. Retarded dopant diffusion for phosphorus, boron, and arsenic has been observed and explained by calibrated dopant profiles while accurately accounting for silicon threshold voltage changes and I-V behaviors. The major benefit of this model is that only a single set of physically based diffusion parameters is required to reproduce device subthreshold characteristics for different active areas, gate lengths, drain voltages, and substrate biases. The proposed model therefore can serve as a compact and accurate method for practically dealing with STI mechanical stress dependent dopant diffusion in ULSI devices. A physical model dealing with anisotropic diffusion in uniaxially stressed silicon is also derived and is quantitatively connected to the
biaxial case. A process-device coupled simulation is performed on a p-type MOSFET undergoing uniaxial stress during the manufacturing process. A systematic treatment is conducted and the resulting fundamental material parameters are in satisfactory agreement with literature values.
For mechanical stress effect on the MOSFEST on-state characteristics, a well-planned active area layout experiment to examine STI mechanical stress effect on state-of-the-art bulk n and pMOS transistors; highlighting the effect of active area scaling and gate placement is demonstrated. Mechanical stress simulation yields compressive-type strain, successfully explaining experimental observations.
Systematic analysis is then achieved, yielding striking results: (i) the experimental drive current sensitivity tracks the compressive-type strain along the channel well; (ii) the oxidation step after STI formation is identified the primary origin of the strain.
A scaleable model for the mechanical stress effect on MOS electrical performance is also proposed. This model includes the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order parameters. Based on the model, new effective MOSFET active area length formulas are derived to improve the simulation efficiency and have been verified by data from various layouts. This model matches the measurement data well and is proven to be useful for circuit design in advanced CMOS technologies.
For the boundary dopant scattering effect during ion implantations, the well mask edge proximity is investigated. An experiment accounting for the impact of
this effect is conducted using a sub-100nm CMOS technology. Ion scattering models and TCAD simulations provide an internal view of the influence of this effect on the MOSFET. Additional SPICE models are established based on the physical understanding observed from the TCAD simulation and verified using the results from specially designed silicon experiment.
5.2 Recommendations for Future Work
The mechanical stress has become a major strategy for MOSFETs scaling in the advanced CMOS technologies. In this work, the isotropic stress-dependent diffusion model and anisotropic diffusion derivation for uniaxial stress cases have been developed and are sufficient to explain the experimental data. However, even stronger anisotropic stress can be expected in future technologies, and then a generalized anisotropic stress-dependent diffusion model for arbitrary stress conditions and the experiment designed for extracting the stress-dependent activation energies is necessary.
More mechanical stress simulations and analyses other than STI and oxidations, such as, silicon germanium/silicon carbon source and drain, strained cap layers and damascene gate are good topics for further studies on MOSFET performance improvements. Analytical stress-mobility models and stress induced band edge shift models can be implemented into the device simulators for more precise analyses on the stress induced MOSFEST on-state characteristics.
More boundary dopant scattering effects of the ion implantations other than
well formation ion implantations can be explored in the future. This topic can be combined with random dopant concentration fluctuation effects since the device scaling leads to limited counts of dopant atoms in a scaled MOSFET.
As the devices continued scaled, three dimensional (3-D) dopant diffusion, mechanical stress, and the boundary dopant scattering effects will also be more pronounced and need to be taken into considerations for the device design.
Meanwhile, the three dimensional capability of TCAD tools needs to be improved on the numerical solving issues.
Vita (博士候選人學經歷表)
姓 名: 許義明 Yi-Ming Sheu
性 別: 男
出生日期: 1968 . 1 . 27 出 生 地: 台灣新竹
學 歷: 國立成功大學材料系學士畢業
國立中央大學光電研究所碩士畢業
國立交通大學電子工程研究所固態組
經 歷: 華昕電子研發工程師
台灣積體電路製造公司製程整合工程師
台灣積體電路製造公司研發工程師
台灣積體電路製造公司研發副理
Publication list
1. ( 1 點 ) Y. M. Sheu, Kelvin Y. Y. Doong, C. H. Lee, M. J. Chen, and C. H. Diaz,
“Study on STI mechanical stress induced variations on advanced CMOSFETs,” in Proc. of ICMTS, Mar. 2003, pp. 205-208.
2. Y. M. Sheu, C. S. Chang, H. C. Lin, S. S. Lin, C. H. Lee, C. C. Wu, M. J. Chen, and C.
H. Diaz, “Impact of STI mechanical stress in highly scaled MOSFETs,” in Int. Symp.
VLSI-TSA, Oct. 2003, pp. 269-272.
3. K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K. Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc. of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
4. C. C. Wu, Y. K. Leung, C. S. Chang, M. H. Tsai, H. T. Huang, D. W. Lin, Y. M. Sheu, C. H. Hsieh, W. J. Liang, L. K. Han, W. M. Chen, S. Z. Chang, S. Y. Wu, S. S. Lin, H. C.
Lin, C. H. Wang, P. W. Wang, T. L. Lee, C. Y. Fu, C. W. Chang, S. C. Chen, S. M. Jang, S. L. Shue, H. T. Lin, Y. C. See, Y. J. Mii, C. H. Diaz, Burn J. Lin, M. S. Liang, Y. C. Sun,
“A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications,” in IEDM Tech. Dig., Dec.
2002, pp. 65-68.
5. K. W. Su, K. H. Chen, T. X, Chung, H. W. Chen, C. C. Huang, H. Y. Chen, C. Y.
Chang, D. H. Lee, C. K. Wen, Y. M. Sheu, S.J. Yang, C. S. Chiang, C. C. Huang, F. L.
Yang, Y. T. Chia, “Modeling Isolation-induced Mechanical Stress Effect on SOI MOS
6. C.C. Wang, T.Y. Huang, Y. M. Sheu, Ray Duffy, Anco Heringa, N.E.B. Cowern, Peter B. Griffin, Carlos H. Diaz, “Boron diffusion in strained and strain-relaxed SiGe,” SISPAD 2004, pp. 41-44.
7. Fu-Liang Yang, Chien-Chao Huang, Hou-Yu Chen, Jhon-Jhy Liaw, Tang-Xuan Chung, Hung-Wei Chen, Chang-Yun Chang, Cheng-Chuan Huang, Kuang-Hsin Chen, Di-Hong Lee, Hsun-Chih Tsao, Cheng-Kuo Wen, Shui-Ming Cheng, Yi-Ming Sheu, Ke-Wei Su, Chi-Chun Chen, Tze-Liang Lee, Shih-Chang Chen, Chih-Jian Chen, Cheng-Hung Chang, Jhi-Cheng Lu, Weng Chang, Chuan-Ping Hou,Ying-Ho Chen, Kuei-Shun Chen, Ming Lu, Li-Wei Kung, Yu-Jun Chou, Fu-Jye Liang, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Bor-Wen Chan, Yi-Chun Huang, Han-Jan Tao, Jyh-Huei Chen, Yung-Shun Chen, Yee-Chia Yeo, Samuel K-H Fung, Carlos H. Diaz, Chii-Ming M. Wu, Burn J.
Lin, Mong-Song Liang, Jack Y.-C. Sun, and Chenming Hu, “A 65nm Node Strained SOI Technology with Slim Spacer,” in IEDM Tech. Dig., Dec. 2003, pp. 627-630.
8. J. R. Shih, Y. M. Sheu, H. C. Lin and Ken Wu “Pattern Density Effect of Trench Isolation-Induced Mechanical Stress on Device Reliability in sub-0.1um Technology,”
IRPS 2004, pp.489-492.
9. ( 3 點 ) Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling Mechanical Stress Effect on Dopant Diffusion in Scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 30-38, January 2005.
10. Yi-Ming Sheu, Tsung-Yi Huang, Yu-Ping. Hu, Chih-Chiang Wang, Sally Liu, Ray Duffy, Anco Heringa, Fred Roozeboom, Nick E. B. Cowern, and Peter B. Griffin,
“Modeling Dopant Diffusion in Strained and Strain-Relaxed Epi-SiGe,” SISPAD 2005, pp. 75-78.
11. Yi-Ming Sheu, Ke-Wei Su, Sheng-Jier Yang, Hsien-Te Chen, Chih-Chiang Wang, Ming-Jer Chen, and Sally Liu, “Modeling well edge proximity effect on highly-scaled MOSFETs,” Custom Integrated Circuits Conference, 2005, pp. 826–829.
12. C. C. Wang, Y. M. Sheu, Sally Liu, R. Duffy, A. Heringa, N. E. B. Cowern, P.B.
Griffin, “Boron diffusion in strained and strain-relaxed SiGe,” Materials Science and Engineering B 2005, pp. 39-44.
13. ( 1 點 ) Yi-Ming Sheu, Sheng-Jier Yang, Chih-Chiang Wang, Chih-Sheng Chang, Ming-Jer Chen, Sally Liu and Carlos H. Diaz, “Reproducing Subthreshold characteristics of metal-oxide-semiconductor field effect transistors under Shallow Trench Isolation Mechanical Stress Using a Stress-Dependent Diffusion Model,” J.
Jap Appl. Phys., Vol. 45, No. 32, pp. L849–L851, August 2006.
14. K. C. Ku, C. F. Nieh, L. P. Huang, Y. M. Sheu, C. C. Wang, C. H. Chen,H. Chang, L. T. Wang, T. L. Lee, S. C. Chen, M. S. Liang, and J. Gong, "Effects of germanium and carbon co-implants on phosphorus diffusion in silicon," Appl. Phys. Lett, vol. 89, pp.
112104-1–112104-3, September 2006.
15. ( 3 點 ) Yi-Ming Sheu, Ke-Wei Su, Shiyang Tian, Sheng-Jier Yang, Chih-Chiang Wang, Ming-Jer Chen, and Sally Liu, “Modeling the well-edge proximity effect in highly-scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp. 2792-2798, November 2006.
16. ( 3 點 ) Ming-Jer Chen, and Yi-Ming Sheu, “Effect of uniaxial strain on
anisotropic diffusion in silicon,” Appl. Phys. Lett., vol. 89, pp. 161908-1–161908-1, October 2006.
17. C. F. Nieh, K. C. Ku, C. H. Chen, H. Chang, L. T. Wang, L. P. Huang, Y. M. Sheu, C. C. Wang, T. L. Lee, S. C. Chen, M. S. Liang, J. Gong, “Millisecond anneal and short-channel effect control in Si CMOS transistor performance,” Electron Device Lett., vol. 27, pp.969–971, December 2006.
18. Ming H. Yu, J. H. Li, H. H. Lin, C. H. Chen, K. C. Ku, C. F. Nie, H. K. Hisa, Y. M.
Sheu, C. W. Tsai, Y. L. Wang, H. Y. Chu, H. C. Cheng, T. L. Lee, S. C. Chen, and M. S.
Liang, “Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond,” in IEDM Tech. Dig., Dec. 2006, pp. 867-871.
共 11 點
Yi Ming Sheu Patent Filing List:
U.S.A. patent list:
1. Method of forming a self-aligned twin well structure with a single mask Inventor: SHEU YI-MING (TW); YANG FU-LIANG (TW)
Applicant: TAIWAN SEMICONDUCTOR MFG Patent no. US6703187.
2. Planarizing method for fabricating gate electrodes
Inventor: LIN YO-SHENG (TW); SHEU YI-MING (TW); LIN DA-WEN (TW); HSIEH CHI-HSUN (TW)
Applicant: TAIWAN SEMICONDUCTOR MFG Patent no. US6670226.
3. Electrostatic discharge device protection structure
Inventor: CHAN YI-LANG (TW); YANG FU-LIANG (TW); SHEU YI MING (TW) Applicant: TAIWAN SEMICONDUCTOR MFG
Patent no. US6800516.
4. Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions
Inventor: SHEU YI-MING (TW); CHAN YI-LING (TW); LIN DA-WEN (TW); LIEN WAN-YIH (TW); DIAZ CARLOS H (TW)
Applicant: TAIWAN SEMICONDUCTOR MFG Patent no. US6673683.
5. Damascene gate electrode method for fabricating field effect transistor (FET)
device with ion implanted lightly doped extension regions
Inventor: DIAZ CARLOS H (US); SHEU YI-MING (TW); JANG SYUN-MING (TW);
TAO HUN-JAN (TW); YANG FU-LIANG (TW) Applicant: TAIWAN SEMICONDUCTOR MFG Patent no. US6974730.
6. Narrow width effect improvement with photoresist plug process and STI corner ion implantation
Inventor: SHEU YI-MING (TW); LIN DA-WEN (TW); CHEN CHENG-KU (TW);
YEH PO-YING (TW); PENG SHI-SHUNG (TW); WU CHUNG-CHENG (TW) Applicant: TAIWAN SEMICONDUCTOR MFG
Patent no. US7071515.
7. Recessed gate structure with reduced current leakage and overlap capacitance Inventor: LIN DA-WEN (TW); SHEU YI-MING (TW); LEUNG YING-KEUNG (HK) Applicant: TAIWAN SEMICONDUCTOR MFG
Patent no. US7012014.
中華民國專利：
1. 第 33 卷 31 期－公告編號 公告日期：95 年 11 月 01 日
1. 第 33 卷 31 期－公告編號 公告日期：95 年 11 月 01 日