Fully-Silicided Gates

High-performance CMOS technology generally requires two different workfunctions for n-MOS and p-MOS devices. This condition results in complex gate stacks and complex process. Only one kind of gate dielectrics deposited is basically required. One of the approaches uses a single metal layer, which sets workfunction for one type of transistor and an alloy of the same metal formed from an additional layer for the other transistor. An excellent technique, compatible with very large scale integrated VLSI CMOS technology of forming tunable metal gates by full silicidation FUSI of doped polysilicon gates, was recently demonstrated. The ability to form a pileup of dopant at the silicide/dielectric interface and thus to modulate the gate electrode workfunction appears to be strongly related to the silicidation conditions [1-11]. It is widely reported that the silicidation temperature and the ratio of Si and Ni thickness, affect the phase of the FUSI gate. Formation of dopant pileup in front of advancing silicide and ultimately at the silicide/gate dielectric interface is depend on what the diffuse species are. Virtually immobile dopant atoms in silicon at silicidation temperatures pile-up at the silicide front when silicon is the moving specie. Ni-rich silicides such as Ni2Si form by Ni atoms moving into Si, thus there is no dopant pileup. The pileup formed during NiSi formation implies that Si is moving specie during process. This phenomena is counter to Ni reacted with undoped Si. We would suggest that the presence of immobile dopant may be the key point of the FUSI gates. Several groups have been recently

studied FUSI gates on high-k dielectrics. Metal gates are proved to decrease severe Fermi level pinning observed on polysilicon/Hf-based dielectric stacks, believed to have been caused by Si-Hf interaction. No pinning was also reported for NiSi-HfAlNO system and for NiSi on HfO2. However, some studies show that FUSI NiSi does exhibit the pinning. It has been reported for NiSi gates on Hf silicate, NiSi and PtSi on HfOxN, and for NiSi on HfSiON.

So we have to improve the stack formation process, and particularly the type and quality of interface between metal and dielectric to have better performance [1-11]-[1-15]. In Fig. 1-6, we summarize all the challenges of MOSFETs mentioned in Chapter 1.

Materials SiO2 Si N3 4 Al O2 3 HfSiO4 ZrO2 HfO2 La O2 3

κ 3.9 7 9 11 25 25 30

Table.1-1 Static dielectric constant (K) of various materials.

Fig. 1-1 The ITRS Roadmap for semiconductor 2007.

Fig. 1-2 Static dielectric constants versus energy band gap for candidate materials.

Fig. 1-3 Schematic of band offsets determining carrier injection in oxide band states.

Ve>1V

Vh>1V 1.1V

0V

CB

VB

Si Oxide

Fig. 1-4 The values of work function for different metal materials.

Fig.1-5 Energy band diagram (left) and charging character of interface states (right) for the metal-dielectric interface.

Fig. 1-6 The challenging issues of MOSFETs.

Depletion effect (poly gate) TOP IL

Fermi level pinning

Chapter 2

The Experimental Procedure

2.1 The Fabrication Step

The gate-first IrxSi/HfSiON p-MOSFETs and HfxSi/HfSiON n-MOSFETS were fabricated on 12-in N-type Si wafers with resistivity of 1–10 Ω・ cm. After RCA cleaning, 4-nm HfSiO dielectric (Hf / (Hf + Si) =50%) was deposited by atomic-layer deposition (ALD).

HfSiON gate dielectric was formed by applying NH3 plasma surface nitridation on HfSiO. For p-MOSFETs, 5–30-nm amorphous Si and 20–30-nm Ir were deposited by physical vapor deposition (PVD) [2-1]. For Ir/Si/HfSiON capacitors, a 1000℃ RTA was applied for 10 s to form IrxSi gates. For MOSFETs, additional 400-nm Si was deposited on top of Ir/Si to avoid ion implantation penetrating through the thin Ir/Si. After gate definition, Boron was implanted at 25-KeV energy and 5 × 10¹⁵ cm⁻² dose, and activated at 1000℃ RTA for10 s. Meanwhile, IrxSi was also formed during RTA, where the x = 3 was determined by X-ray diffraction measurements.

For n-MOSFETS, amorphous Si with various thickness of 50 to 5 nm was deposited on HfSiON as a silicide layer and metal barrier for subsequently deposited 20-nm-thick Hf by physical vapor deposition (PVD) [2-3]. The MOS capacitor was formed by patterning and RTA at 1000℃ for 10 s. Then, additional 150-nm-thick amorphous Si was deposited on

+

formed by using a phosphorus ion implantation at 35 KeV. Then, the 1000 ◦C RTA was applied to activate the implanted dopant and the n-MOSFET was fabricated by this self-aligned gate first process. At such high 1000℃ RTA temperature, the fast silicidation reaching to the Si/HfSiON interface may also reduce the reaction of thin amorphous Si (5 nm) with high- κ dielectric to cause Fermi-level pinning.

2.2 The Measurement of MOSFET

We used ion-mass spectroscopy (SIMS) to measure the Ir distribution profile. The fabricated p-MOSFETs and n-MOSFETs were further characterized by capacitance–voltage (C–V) and current–voltage (I–V) measurements. The capacitance–voltage (C–V) and current–voltage (I–V) measurements are measured by HP 4156C semiconductor parameter analyzer and HP 4284A precision LCR meter. In order to compare, Al, Ir-gated, and Hf-gated MOS capacitors on HfSiON were also fabricated. To prevent the different oxide charge from causing error in Φm eff, extraction, HfSiON was subjected to the same thermal cycle (1000

℃ RTA for 10 s) before Al gate deposition.

2.3 Process Flow

N- or P-Type Si

N- or P-Type Si

Fig. 2-1 N- or P-Type Si Substrate

Fig. 2-2 RCA clean

Fig. 2-4 NH3 Plasma Nitridation N- or P-Type Si

HfSiO N- or P-Type Si

HfSiO

Fig. 2-3 Deposit HfSiO

N- or P-Type Si HfSiON Amorphous-Si

Fig. 2-5 Deposit Amorphous-Si

Fig. 2-6 Deposit Ir or Hf N- or P-Type Si

HfSiON Amorphous-Si

Ir or Hf

Fig. 2-7 Deposit Si

Fig. 2-8 Gate Definition N- or P-Type Si

HfSiON Amorphous-Si

Ir or Hf Amorphous-Si

N- or P-Type Si HfSiON Amorphous-Si

Ir or Hf Amorphous-Si

Fig. 2-9 Ion implantation

Fig. 2-10 1000℃, 10s, RTA N- or P-Type Si

HfSiON Amorphous-Si

Ir or Hf Amorphous-Si

Amorphous-Si Ir or Hf Amorphous-Si

N- or P-Type Si HfSiON

S D

Fig. 2-11 Fabricated MOSEFET Ir3Si or HfSix

Amorphous-Si

N- or P-Type Si HfSiON

S D

Chapter 3

The Characteristics and Analysis of P-MOSFET

3.1 Introduction

We have measured the J-V characteristics of the MOSFETs, and then want to find out their threshold voltages by using equation (10).

( ) the mobility. Using equation (11) finds out the gd in linear region, and equation (12) gives the

effective mobility. 3.2 The Effective Metal Workfunctions

We have fabricated three different kinds of gate electrodes. The three materials are IrxSi, Ir, and Al. Fig 3.1 and Fig. 3.2 shows the measured C–V characteristics of IrxSi, Ir, and Al gates on HfSiON MOS devices. We use low-temperature Al-gated HfSiON capacitors as a

reference because pure metal deposited at low temperature has less interface reaction with high-κ dielectrics than high-temperature process. The Al-gated HfSiON capacitors have fewer

extrinsic states, and thus the Fermi-level pinning effect is not obvious in the structure [3-4].

fb ^{ms f}/ ox work functions for metal gates and Si, respectively. Q , C^f ox, tox, and equivalent-oxide thickness (EOT) are the oxide charge, capacitance, physical thickness, and EOT for high-κ dielectrics. Since the three kinds of MOS devices have the same thermal cycle(1000 ◦C RTA for 10 s)before gates formation, we could assume that the fixed charge (Qf) amount should be the same. In Fig 3-2, the various flat band voltages (Vfb) may be due to the different metal work functions. Therefore, the principal effect of V^fb shift might be due to the difference of effective workfunction (Φ^m,eff). The processes before gate definition are the same, and the MOS capacitors all have EOT values of 1.6nm. The shifts of C–V curves with different gate electrodes are attributed to the different work functions (Φ^m,eff). Ir/HfSiON after 900 ◦C RTA has a large V^fb shift of 1.15 V to Al gates (Φ^m,eff= 4.1eV). It results in the required high

m,eff

Φ of 5.25 eV. This work-function value is also close to 5.27 eV for Ir. The pure metal Ir gates showed no obvious pinning effect. This is due to weak bonding strengths of Ir–O or Ir–N that reduce the Fermi-level-pinning-related interface reaction. However, we observed

that Ir/HfSiON capacitors failed after 1000℃ RTA.

3.3 Thermal Stability

In Fig 3-3, Ir/HfSiON is failed after 1000℃ RTA. In order to activate the impurities, the gates have 1000℃ RTA after S/D implantation. To improve thermal stability, additional amorphous Si of 5–30 nm was inserted between Ir and HfSiON and also serve as a metal diffusion blocking layer. After 1000℃ RTA, IrxSi gate is formed. Good C–V characteristics were measured for IrxSi/HfSiON devices after the required 1000℃ RTA, although thermal stability was traded off at the Fermi-level pinning. In Fig 3-1, we obtained a high Φ^m,eff of 4.95 eV for IrxSi/HfSiON devices with the inserted 5-nm amorphous Si. Slow depletion for IrxSi /HfSiON devices with 30-nm amorphous Si may be due to nonuniform silicidation as examined by TEM, where locally unreacted Si was found to cause voltage drop in gate electrodes. The formation of FUSI gates is evident from the same inversion and accumulation capacitances measured in MOSFETs.

3.4 The J-V Characteristics

After 1000 ◦C RTA, Ir/HfSiON devices had high leakage currents and failed thus as shown in Fig. 3.3. On the other hand, IrxSi gates on HfSiON successfully improved thermal stability to 1000 ℃ RTA with low leakage current comparable with p⁺ poly-Si gates. 1000

◦C RTA is required for dopant activation after ion implantation of source and drain. The measured large V^fb shift of IrxSi is supported by SIMS profile, as shown in Fig. 3-5. Here, Ir

segregation toward amorphous Si formed IrxSi on HfSiON surface. Therefore, good thermal stability of 1000 ◦C RTA, a reasonable high Φ^m,eff of 4.95 eV, and a low gate dielectric leakage current can be achieved in IrxSi /HfSiON MOS capacitors at the same time. These are the few methods to achieve a high Φ^m,eff in Hf-based oxide p-MOS devices. There is a widely studied tuning method by impurity segregation in FUSI/SiON. However this method can not be applied to high-κ metal oxide due to the stronger interface reaction. In the following, we will study IrxSi /HfSiON devices with the thinnest 5-nm amorphous Si which has the best performance in the experiments. Compared with p-MOSFET, the V^fb of thicker Si layer is too low. Fig. 3-6 shows the transistor I^d–V^d characteristics as a function of

V -g Vt for 1000 ◦C RTA IrxSi/HfSiON p-MOSFETs. The splendid results of Id–Vd curves of IrxSi/HfSiON transistors in Fig. 3-4 show little device performance degradation. Fig. 3-7 shows the Id–V characteristics of Irg xSi-gated p-MOSFETs with HfSiON as the gate dielectric. In this work, we obtained the low Vt of −0.15 V from the linear Id–V plot, g

which is consistent with the large Φ^m,eff of 4.95 eV from C–V curves and the Ir accumulation on HfSiON from SIMS. Fig. 3-8 shows the extracted hole mobilities versus gate electric fields from the measured Id–V data of Irg xSi/HfSiON p-MOSFETs. High hole mobilities of 84 and 53 cm²/V • s are obtained at peak value and 1 MV/cm effective field for IrxSi/HfSiON p-MOSFETs, respectively, which is compatible with the published data in the literature [3-4]. Good hole mobility also indicates low Ir diffusion through HfSiON to

inversion channel, even though excess Ir is necessary to prevent unreacted amorphous Si from causing gate depletion or increased Fermi-level pinning. Therefore, a highΦ^m,eff, a smallV^t, and good hole mobility are achieved in IrxSi/HfSiON p-MOSFETs.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0

5 10 15

20

_Ir

xSi(30/30nm) gate @ 1000^oC 10s RTA Ir_xSi(20/10nm) gate @ 1000^oC 10s RTA Ir_xSi(20/5nm) gate @ 1000^oC 10s RTA

Voltage (V) Capacitance (fF/

µ

m

2

)

Fig. 3-1 C–V curves of HfSiON/n-Si with various Si thickness. The device areas are 100 × 100 µm.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0

5 10 15

20

_Ir

xSi(20/5nm) gate @ 1000^oC 10s RTA Ir gate @ 900^oC 10s RTA

low temperture Al gate reference

Voltage (V) Capacitance (fF/

µ

m

2

)

Fig. 3-2 C–V curves of Ir/HfSiON, IrxSi/HfSiON (20/5nm), and Al/HfSiON.

0.0 0.5 1.0 1.5 2.0 10^-8

10^-6 10^-4 10^-2 10⁰ 10²

Gate Current ( A/cm2 )

Voltage (V)

Ir gate @ 900^oC 10s RTA

Ir gate @ 1000^oC 5s RTA (failed)

Fig. 3-3 Ig-Vg curves of Ir/HfSiON/n-Si with RTA temperatures of 1000 and 900℃ ℃.

0.0 0.5 1.0 1.5 2.0 10^-8

10^-6 10^-4 10^-2 10⁰ 10²

Gate Current ( A/cm2 )

Voltage (V)

low temperature Al gate reference Ir_xSi(30/30nm) gate @ 1000^oC 10s RTA Ir_xSi(20/10nm) gate @ 1000^oC 10s RTA Ir_xSi(20/5nm) gate @ 1000^oC 10s RTA

Fig. 3.4 Ig-Vg curves of IrxSi/HfSiON and Al/HfSiON.

0 50 100 150 200

Fig. 3-5 SIMS profile of Ir3Si gates on HfSiON at different RTA temperatures. The Ir3Si that accumulated toward HfSiON interface is found to unpin the Fermi level.

-2.5 -2.0 -1.5 -1.0 -0.5 0.0

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 10^-10

10^-9 10^-8 10^-7 10^-6 10^-5 10^-4 10^-3

I d (A)

Vg (V)

Ir3Si/HfSiON p-MOSFET

Vds = -0.1 V

Gate length = 10 µm

Fig. 3-7 Id–Vg curves of Ir3Si/HfSiON p-MOSFETs.

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 40

80 120 160 200

Universal

Ir

3

Si/HfSiON p-MOSFET

µ

eff

( cm

2

/V -s e c )

Effective field (MV/cm)

Fig. 3-8 Extracted hole mobilities from Id–Vg characteristics of Ir3Si/HfSiON p-MOSFETs.

Chapter4

The Characteristics and Analysis of N-MOSFET

4.1 The Effective Metal Workfunctions and Thermal Stability

Fig. 4-1, Fig. 4-2, and Fig. 4-3 shows the C–V and J–V characteristics for HfSix/HfSiON and Al/HfSiON capacitors, where the HfSix gate was formed at 1000℃ RTA. The Al-gated capacitor has work-function of 4.1 eV. For various amorphous Si of 50 and 10 nm on HfSiON, the capacitance density decreases as the thickness of amorphous Si increases. This implies that not all amorphous silicon is silicided in HfSix gate on HfSiON. Thus a higher flat-band voltage (V^FB) due to the Fermi-level pinning on high-κ dielectric occurs. In contrast, the HfSix

with thin 5-nm amorphous Si has the same capacitance density with Al gate. It is indicated that all amorphous Si is silicided. From the C–V shift referenced to the control Al gate, an extracted Φ^m,eff of 4.27 eV is obtained for HfSix/HfSiON. This result approaches the desired workfunction (Φ^m) of NMOSFET. The low V^FB _and Φm,eff for HfSix gate capacitors with 5-nm amorphous Si may be due to the Hf diffusion toward the HfSiON surface through thin amorphous Si that decreases the work function. In addition, low leakage current of 1.9 × 10⁻⁵A/cm at −1 V is measured at an equivalent oxide thickness (EOT) of 1.6 nm. This result shows the good thermal stability of HfSix gate on HfSiON dielectric after 1000℃ RTA.

Therefore, the experiment obtained reasonable low Φ^m,eff of 4.27 eV and a low gate leakage

current in HfSix/HfSiON MOS capacitors at the same time [4-5].

4.2 J-V Characteristics

Fig. 4-4 shows the transistor I^D _–VD characteristics as a function of V –^g V^t for the 1000

℃ RTA-annealed HfSix/HfSiON n-MOSFETs. Fig. 4-5 displays I^D _–V characteristics of the g

HfSix/HfSiON n-MOSFETs. A low V^t of only 0.14 V was measured from the linear I^D _–V g

plot, which agrees with the low Φ^m,eff of 4.27 eV from the C–V measurements. Fig. 4-6 shows the electron mobility extracted from the measured I^D _–V curves of the n-MOSFETs. g

A peak electron mobility of 216cm²/V·s was obtained for the HfSix/HfSiON n-MOSFETs.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0

5 10 15 20

25

_HfSi

X(20/50nm)@1000^oCRTA HfSi_X (20/10nm)@1000^oCRTA HfSi_X(20/5nm)@1000^oCRTA

Capacitance (fF/

µ

m

2

)

Voltage (V)

Fig. 4-1 C–V characteristics for high-temperature RTA formed HfSix/HfSiON with various amorphous Si.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0

5 10 15 20

25 Al gate HfSi

X

(20/5nm)@1000

^o

CRTA

Capacitance (fF/ µ m

2

)

Voltage (V)

Fig. 4-2 C–V characteristics for high-temperature RTA formed HfSix (20/5nm) HfSiON and low-temperature Al/HfSiON capacitors.

-2.0 -1.5 -1.0 -0.5 0.0 10

^-10

10

^-8

10

^-6

10

^-4

10

^-2

Al gate @low Temperature HfSi_X(20/50nm)@1000^oCRTA HfSi

X (20/10nm)@1000^oCRTA HfSi_X(20/5nm)@1000^oCRTA

Voltage (V) G a te Cu rrent Density (A/cm

2

)

Fig. 4-3 J - ^g V characteristics for high-temperature RTA formed HfSi^g x/HfSiON and low-temperature Al/HfSiON capacitors.

0.0 0.5 1.0 1.5 2.0 2.5

Fig. 4-4 I^D _–VD characteristics of HfSix/HfSiON n-MOSFET. The amorphous Si on HfSiON was 5 nm and gate length was 10 µm.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 10

^-10

10

^-8

10

^-6

10

^-4

10

^-2

HfSi

_X

(20/5nm)@1000

^o

CRTA HfSi

_X

/HfSiON n-MOSFET I

d

(A)

V

_g

(V)

V

_ds

= 0.1 V

Fig. 4-5 Id–Vg characteristics of HfSix/HfSiON n-MOSFET.

0.0 0.2 0.4 0.6 0.8 1.0 0

200 400 600 800

HfSi

X

(20/5nm)@1000

^o

CRTA Universal

HfSi

x

/HfSiON n-MOSFET

Effective field (MV/cm) µ eff ( cm 2 /V -se c )

Fig. 4-6 Electron mobility of HfSix/HfSiON n-MOSFETs.

Chapter5 Conclusion

In the experiment, we have obtained good device performance of IrxSi/HfSiON p-MOSFETs with a high Φ^m,eff of 4.95 eV, a small Vt of −0.15 V, a peak hole mobility of 84 cm²/V・s, and 1000℃RTA thermal stability. For NMOSFET, a low Φ^m,eff of 4.27eV, threshold voltage of 0.14V, and a mobility of 216cm²/V·s are obtained. They are obviously that the processes can be integrated in current technology. On the other hand, we will study hard to decrease EOT by replacing the high-κgate dielectrics in the future. The threshold voltages of devices are needed to decrease, and avoid the Fermi-Level pinning. However, the research of this work proved that this is an effective way to meet the ITRS roadmap after 2008.

Reference

Chap1:

[1-1] 廖金昌， “The Electrical Characteristics and Application in MOSFETs of High k Gate Dielectric Al2O3 Formed by Aluminum Oxidation”，交通大學，博士論文，九十四年二月。

[1-2] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D.

Hanken, M. Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S.

Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S.

Pae, C. Parker, D. Parsons, C. Prasad , L. Pipes, M. Prince, P. Ranade, T. Reynolds, J.

Sandford, L. Shifren0, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm Logic Technology with High-k-Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”, IEEE, pp.247-250, 2007.

[1-3] A.L.P. Rotondaro, M.R. Visokay, J.J. Chambers, A. Shanware, R. Khamankar, H. Bu, R.T. Laaksonen, L.Tsung, M. Douglas, R. Kuan, M.J. Bevan, T. Grider, J. cPherson, L.

Colombo, “Advanced CMOS Transistors with a Novel HfSiON Grate Dielectric”, Symposium On VLSI Technology Digest of Technical Papers, pp148-149, 2002.

[1-4] D.A. Buchanan, E.P. Gusev, E. Cartier, H. Okorn-Schmidt, K. Rim, M.A. Gribelyuk, A.

K. Chan, R.J. Fleming, P.C. Jamison, J. Brown, R Arndt, IEDM Technical Digest (2000) 223.

[1-5] E.P. Gusev, E. Cartier , D.A. Buchanan , M. Gribelyuk , M. Copel , H. Okorn-Schmidt , C. D’Emic, “Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues” , Microelectronic Engineering 59, pp. 341–349, 2001.

[1-6] Baohong Cheng, Min Cao, Ramgopal Rao, Anand Inani, Paul Vande Voorde, Wayne M.

Greene, Johannes M. C. Stork, Zhiping Yu, Peter M. Zeitzoff, and Jason C. S. Woo, “The Impact of High- κ Gate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFET’s”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 7, pp.1537-1544, JULY 1999.

[1-7] G. D. Wilk and R. M. Wallace, “Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon”, APPLIED PHYSICS LETTERS VOLUME 74, NUMBER 19, pp.2854-2856.

[1.8] John Robertson, “High dielectric constant gate oxides for metal oxide Si”, Rep. Prog.

Phys. 69 (2006), pp. 327–396.

[1-9] Yee-Chia, Yeo Tsu-Jae King, and Chenming Hu, “Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology”, JOURNAL OF APPLIED PHYSICS VOLUME 92, NUMBER 12, pp.7276-7271.

[1-10] H. Y. Yu, Chi Ren, Yee-Chia Yeo, J. F. Kang, X. P. Wang, H. H. H. Ma,

Ming-Fu Li, D. S. H. Chan, and D.L. Kwong, “Fermi Pinning-Induced Thermal Instability of

Metal-Gate Work Functions”, IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, pp.337-339, MAY 2004.

[1-11] M. Copel, R. P. Pezzi, and C. Cabral, Jr., “Interfacial segregation of dopants in fully silicided metal-oxide-semiconductor gates”, APPLIED PHYSICS LETTERS 86, 2005.

[1-12] J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong, “Work Function Tuning of Fully Silicided NiSi Metal Gates Using a TiN Capping Layer”, IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 9, SEPTEMBER 2004.

[1-13] Kousuke SANO, Masaki HINO, Norihiro OOISHI and Kentaro SHIBAHARA,

“Workfunction Tuning Using Various Impurities for Fully Silicided NiSi Gate”, Japanese Journal of Applied Physics Vol. 44, No. 6A, pp. 3774–3777, 2005.

[1-14] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N.

Yasuda', A. Ogawa, K. Tominaga, H. Satake and A. Toriumi, “Partial Silicides Technology for Tunable Work Function Electrodes on High-k Gate Dielectrics - Fermi Level Pinning Controlled PtSi, for HfO, (N) pMOSFET -”, in IEDM Tech. Dig., 2004, pp. 83-86.

[1-15] Jakub Kedzierski, Diane Boyd, Paul Ronsheim, Sufi Zafar, J. Newbury, John Ott, Cyril Cabral Jr., M. Ieong, Wil6ied Haensch, “Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)”, in IEDM Tech. Dig., 2003, pp.

315-318.

[1-16] M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo

“Application of HfSiON as a gate dielectric material”, Appl. Phys. Lett., Vol. 80, No. 17, 29 April 2002.

[1-17] Qiang Lu, Ronald Lin, Pushkar Ranade, Tsu-Jae Ring, Chenming Hu, “Metal Gate Work Function Adjustment for Future CMOS Technology”, Symp. on VLSI Tech., pp.45-46, 2001.

[1-18] Qiang Lu, Yee Chia Yeo, Pushkar Ranade, Hideki Takeuchi, Tsu-Jae King, Chenming Hu, S. C. Song, H. F. Luan‘ and Dim-Lee Kwong, “Dual-Metal Gate Technology for Deep-Submicron CMOS Transistors”, Symp. on VLSI Tech., pp.72-73, 2000.

[1-19] Chang Seo Park, Byung Jin Cho, and Dim-Lee Kwong, “Thermally Stable Fully Silicided Hf-Silicide Metal-Gate Electrode”, IEEE ELECTRON DEVICE LETTERS, VOL.

25, NO. 6, pp.372-374, JUNE 2004.

[1-20] K. Ohmori , T. Chikyow, T. Hosoi, H. Watanabe, K. Nakajima, T. Adachi , A.

Ishikawa, Y. Sugita, Y. Nara, Y. Ohji, K. Shiraishi, K. Yamabe, K. Yamada, “Wide Controllability of Flatband Voltage by Tuning Crystalline Microstructures in Metal Gate Electrodes”, IEEE, pp.345-348, 2007.

[1-21] Wan Sik Hwang, Chen Shen, Xing Peng Wang, Daniel S. H. Chan, and Byung Jin Cho,

“Wide Controllability of Flatband Voltage by Tuning Crystalline Microstructures in Metal Gate Electrodes”, in Symp. on VLSI Tech., pp.156-157, 2007.

[1-22] J. Petry, R. Singanamalla, K. Xiong, C. Ravit, E. Simoen, R. O'Connor, A. Veloso, C.

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