Chapter 1 Introduction
1.1.3 K Values and Thermal Stability
The oxide’s K value should be over 12, preferably 25–30. There is a trade off with the band offset condition, which requires a reasonably large band gap to reduce gate leakage currents. Table 1-1 and figure 1-2 show that the K of candidate oxides varies inversely with the band gap. In fact, a very large K is undesirable in CMOS design because of large fringing fields at the source and drain electrodes [1-5].
The oxide must not react with Si to form either SiO2 or a silicide according to the This is because the resulting SiO2 layer would increase the EOT and negate the effect of using the new oxide. In addition, any silicide formed by (2) is metallic and would short out
the field effect. An interfacial layer of SiO2 often exists between the Si channel and the high κ oxide layer [1-5~1-8]. There are advantages and drawbacks to this interfacial layer, as
long as its presence and thickness can be controlled. The overall EOT of a layer 1 of SiO2 and a layer 2 of high κ oxide is given by the series capacitance formula (3), which becomes formula (4).
1 2
1/C=1/C +1/C (3)
SiO2 hi
EOT=t +EOT κ (4) 1.1.4 Crystalline or amorphous oxides
Unlike silicon oxide which is amorphous up to 1100℃ because of its low coordination covalent bonds, High-κ transition metal oxides are generally poor glass former. This is because the metal oxide bonding is normally a high coordination ionic bond with the d-state electrons and the oxide films crystallize easily at low temperatures. For both HfO2 and ZrO2, crystallization temperature was expected to be above 900℃. However, the real crystallization temperature is much lower of expected values. This difference may contribute to impurities or some sort of nucleation centers. Thus following post-deposition thermal treatment (PDA) will result in a certain degree of local crystallization. Nevertheless, structural defects in as-deposited amorphous films can be removed through thermal annealing in oxygen-containing ambient. Large amount of shallow oxide traps at the grain boundaries of the crystalline phase will be introduced at the same time. As a result, crystallization will give
1.1.5 Band offset
In order to decrease the leakage current, this requires that the potential barrier at each band must be over 1 eV in order to inhibit conduction by the Schottky emission of electrons or holes into the oxide bands, as shown schematically in figure 1-3. However, the reported high-κ materials usually have large leakage current. The large leakage current can be partially attributed to the small conduction band offset energy with respect to the silicon. The small conduction band offset does not only result in large gate direct-tunneling or Fowler–Norheim (FN) current but also give rise to large hot-carrier emission into the gate insulator. This limits the choice of oxide to those with band gaps over 5 eV. Only few materials like Al2O3, ZrO2, HfO2, Y2O3, and La2O3 and various lanthanides and their silicates and aluminates satisfy these requirements. These oxides also have excellent thermal stability.
This is because a high heat of formation correlates with a wide band gap in ionic compounds [1-8].
1.2 Motivation to Study Metal Gate
1.2.1 Introduction
Considerable challenges are encountered when bulk CMOS devices are scaled into the sub-100 nm regime for higher integrated circuit (IC) density and performance. The problems of polysilicon (poly-Si) gate depletion, high gate resistance, high gate tunneling leakage current, and boron penetration into the channel region become more severe as the channel length and gate-oxide thickness are aggressively reduced. In present CMOS, the gate electrodes are not real metals but polycrystalline Si doped highly n-type or p-type, respectively, for NMOS and PMOS. Their workfunctions are 4.05 eV and 5.15 eV, respectively, just as those required. The gate metals to be used must be ‘band edge metals’, with workfunctions equal to the band edge energies of Si, 4.05 and 5.15 eV [1-17].
1.2.2 The Choice of Metal Gates
As the device continuously scaling down, we encountered a lot of difficulties. Such gate electrodes have problems of:
(1)Boron penetration into channels through thin gate dielectric.
(2) High gate resistance.
(3) Polysilicon gate depletion.
(4) High gate tunneling leakage current.
The possible solution is to use the proper metal gate with proper work function.The
parasitic series capacitance due to a depletion in poly crystalline-silicon gates poly gates reduce the gate capacitance and drive current. The metal gate electrode will make poly-depletion free due to the poly depletion will reduce the capacitance and contribute a degradation to EOT in inversion state. The work functions (Φm) of metal play an important role for metal-gate/high- κ MOSFET and are shown in Fig. 1-4. Metal gates with workfunctions near the conduction and valence band edges of Si are used in N- and P-MOSFETs respectively. To achieve the desired dual-metal gate workfunctions on high-κ gate dielectrics, candidate metals need to have vacuum workfunctions smaller (larger) than 4.05eV (5.17 eV) for the NMOS (PMOS). For the PMOS gate, inert metals must be used and this makes gate etching particularly challenging. Reactive metals have to be used as the NMOS gate, and this might introduce extrinsic interface states due to defects arising from an interfacial reaction [1-6]. There are more metal candidates for NMOSFET (Ti, Al, and Ta) than for PMOSFET. Among the possible candidates for PMOSFET, Pt and Ir are very difficult to etch using plasma processes.
On the other hand, thermal stability of the effective metal electrode and metal diffusion are also important considerations. Recently, lots of metal or metal-nitride materials have been widely researched and successfully intergraded in advanced CMOSFET’s, such as TiN, TaN, Pt, Mo and Ir . Tantalum (Ta) has a work-function close to n+ poly-Si. Tantalum nitride (TaN) is quite stable (to maintain thermal stability up to a 1000℃ RTA) because the activation
energy of metal and nitrogen is relatively low. Tantalum is bonded tightly within nitride and no obvious diffuse was observed in fabricated devices. However, TaN gate on high-κ HfO2
shows a significant shift of flat band voltage (VFB) toward the mid-gap of Si due to the interface reaction between the TaN and HfO2 at the high temperature. This is called the
“Fermi-level pinning effect.” Therefore, the Fermi-level pinning effect needs to be avoided by selecting suitable metal gate and high-κ materials for advanced MOSFETs [1-7]-[1-9].
1.3 The Study of Fermi Level Pinning
1.3.1 Introduction
In order to decrease the threshold voltage with the device scaling down, we have to choose metals with proper workfunctions carefully. The identification of metal-gate materials is very difficult because metal-gate workfunctions are observed to vary with different gate dielectrics and the process parameter. These intrinsic states are predominantly donor-like close to Ev, and mostly acceptor-like near Ec as shown in Fig. 1-5. Charge transfer generally occurs across the interface due to the presence of intrinsic interface states. Charging of these interface states creates a dipole that tends to drive the band lineup toward a position that would give zero dipole charge. Figure 1-5 illustrates the case where the metal Fermi level ΦF,m is above the charge neutrality level in the dielectric ECNL,d , creating a dipole that is charged negatively on the dielectric side. This interface dipole drives the band alignment so that EF,m goes toward ECNL,d and the effective metal work function, Φm,eff therefore differs from the vacuum metal work function Φm,vac. This work function change is proportional to the difference between ECNL,d and EF,m, or, equivalently, the difference between Φm,vac and ΦCNL,d [= (EVac-ECNL,d)/q ].
For some gate materials, there are no defects in the interface, and the workfunctions are determined by intrinsic states. According to reported paper, the workfunctions with Fermi-Level pinning effect are affected by annealing temperature. The Fermi level pinning effect is more obvious at higher temperature. The workfunctions would converge at higher
temperature [1-8]-[1-10].
1.3.2 The Effective Workfunctions
We will discuss about the problems of the workfunctions shifts in the chapter. The workfunctions in vacuum are used as references. In the Schottky limit and without fixed charges, the flat band voltage of a MOS capacitor is given by equation (5). Inverting this equation, an effective workfunction of the gate metal (Φm eff, ) can be derived from the measured flat band voltage of the CV plot of the MOS capacitor, by referencing to the by referencing to the workfunction Φs of the Si substrate, 4.05V or 5.15V for a n-type or p-type Si, respectively. We defined a pinning factor as the change of flat band voltage divided by the change in the metal’s vacuum workfunction as equation (7). Linearizing this model leads to another definition of effective workfunction,Φm eff, , as shown in equation (8). In equation (8), Φm vac, is the vacuum or true workfunction of metals and ΦCNL d, is the CNL
energy of the oxide, measured from the vacuum level.
FB m s
S is a slope parameter that accounts for dielectric screening and depends on the electronic component of the dielectric constantε∞.The factor decreases as the dielectric
equation (9). Materials with a smaller S tend to have obvious Fermi-Level pinning and the effective workfunction would approach ΦCNL d, , and the maximum value for S is unity, which indicates that no pinning of the metal Fermi level occurs [1-8]-[1-10].
2
1 1 0.1( 1)
S= ε∞
+ − (9)
1.4 Fully-Silicided Gates
High-performance CMOS technology generally requires two different workfunctions for n-MOS and p-MOS devices. This condition results in complex gate stacks and complex process. Only one kind of gate dielectrics deposited is basically required. One of the approaches uses a single metal layer, which sets workfunction for one type of transistor and an alloy of the same metal formed from an additional layer for the other transistor. An excellent technique, compatible with very large scale integrated VLSI CMOS technology of forming tunable metal gates by full silicidation FUSI of doped polysilicon gates, was recently demonstrated. The ability to form a pileup of dopant at the silicide/dielectric interface and thus to modulate the gate electrode workfunction appears to be strongly related to the silicidation conditions [1-11]. It is widely reported that the silicidation temperature and the ratio of Si and Ni thickness, affect the phase of the FUSI gate. Formation of dopant pileup in front of advancing silicide and ultimately at the silicide/gate dielectric interface is depend on what the diffuse species are. Virtually immobile dopant atoms in silicon at silicidation temperatures pile-up at the silicide front when silicon is the moving specie. Ni-rich silicides such as Ni2Si form by Ni atoms moving into Si, thus there is no dopant pileup. The pileup formed during NiSi formation implies that Si is moving specie during process. This phenomena is counter to Ni reacted with undoped Si. We would suggest that the presence of immobile dopant may be the key point of the FUSI gates. Several groups have been recently
studied FUSI gates on high-k dielectrics. Metal gates are proved to decrease severe Fermi level pinning observed on polysilicon/Hf-based dielectric stacks, believed to have been caused by Si-Hf interaction. No pinning was also reported for NiSi-HfAlNO system and for NiSi on HfO2. However, some studies show that FUSI NiSi does exhibit the pinning. It has been reported for NiSi gates on Hf silicate, NiSi and PtSi on HfOxN, and for NiSi on HfSiON.
So we have to improve the stack formation process, and particularly the type and quality of interface between metal and dielectric to have better performance [1-11]-[1-15]. In Fig. 1-6, we summarize all the challenges of MOSFETs mentioned in Chapter 1.
Materials SiO2 Si N3 4 Al O2 3 HfSiO4 ZrO2 HfO2 La O2 3
κ 3.9 7 9 11 25 25 30
Table.1-1 Static dielectric constant (K) of various materials.
Fig. 1-1 The ITRS Roadmap for semiconductor 2007.
Fig. 1-2 Static dielectric constants versus energy band gap for candidate materials.
Fig. 1-3 Schematic of band offsets determining carrier injection in oxide band states.
Ve>1V
Vh>1V 1.1V
0V
CB
VB
Si Oxide
Fig. 1-4 The values of work function for different metal materials.
Fig.1-5 Energy band diagram (left) and charging character of interface states (right) for the metal-dielectric interface.
Fig. 1-6 The challenging issues of MOSFETs.
Depletion effect (poly gate) TOP IL
Fermi level pinning
Chapter 2
The Experimental Procedure
2.1 The Fabrication Step
The gate-first IrxSi/HfSiON p-MOSFETs and HfxSi/HfSiON n-MOSFETS were fabricated on 12-in N-type Si wafers with resistivity of 1–10 Ω・ cm. After RCA cleaning, 4-nm HfSiO dielectric (Hf / (Hf + Si) =50%) was deposited by atomic-layer deposition (ALD).
HfSiON gate dielectric was formed by applying NH3 plasma surface nitridation on HfSiO. For p-MOSFETs, 5–30-nm amorphous Si and 20–30-nm Ir were deposited by physical vapor deposition (PVD) [2-1]. For Ir/Si/HfSiON capacitors, a 1000℃ RTA was applied for 10 s to form IrxSi gates. For MOSFETs, additional 400-nm Si was deposited on top of Ir/Si to avoid ion implantation penetrating through the thin Ir/Si. After gate definition, Boron was implanted at 25-KeV energy and 5 × 1015 cm−2 dose, and activated at 1000℃ RTA for10 s. Meanwhile, IrxSi was also formed during RTA, where the x = 3 was determined by X-ray diffraction measurements.
For n-MOSFETS, amorphous Si with various thickness of 50 to 5 nm was deposited on HfSiON as a silicide layer and metal barrier for subsequently deposited 20-nm-thick Hf by physical vapor deposition (PVD) [2-3]. The MOS capacitor was formed by patterning and RTA at 1000℃ for 10 s. Then, additional 150-nm-thick amorphous Si was deposited on
+
formed by using a phosphorus ion implantation at 35 KeV. Then, the 1000 ◦C RTA was applied to activate the implanted dopant and the n-MOSFET was fabricated by this self-aligned gate first process. At such high 1000℃ RTA temperature, the fast silicidation reaching to the Si/HfSiON interface may also reduce the reaction of thin amorphous Si (5 nm) with high- κ dielectric to cause Fermi-level pinning.
2.2 The Measurement of MOSFET
We used ion-mass spectroscopy (SIMS) to measure the Ir distribution profile. The fabricated p-MOSFETs and n-MOSFETs were further characterized by capacitance–voltage (C–V) and current–voltage (I–V) measurements. The capacitance–voltage (C–V) and current–voltage (I–V) measurements are measured by HP 4156C semiconductor parameter analyzer and HP 4284A precision LCR meter. In order to compare, Al, Ir-gated, and Hf-gated MOS capacitors on HfSiON were also fabricated. To prevent the different oxide charge from causing error in Φm eff, extraction, HfSiON was subjected to the same thermal cycle (1000
℃ RTA for 10 s) before Al gate deposition.
2.3 Process Flow
N- or P-Type Si
N- or P-Type Si
Fig. 2-1 N- or P-Type Si Substrate
Fig. 2-2 RCA clean
Fig. 2-4 NH3 Plasma Nitridation N- or P-Type Si
HfSiO N- or P-Type Si
HfSiO
Fig. 2-3 Deposit HfSiO
N- or P-Type Si HfSiON Amorphous-Si
Fig. 2-5 Deposit Amorphous-Si
Fig. 2-6 Deposit Ir or Hf N- or P-Type Si
HfSiON Amorphous-Si
Ir or Hf
Fig. 2-7 Deposit Si
Fig. 2-8 Gate Definition N- or P-Type Si
HfSiON Amorphous-Si
Ir or Hf Amorphous-Si
N- or P-Type Si HfSiON Amorphous-Si
Ir or Hf Amorphous-Si
Fig. 2-9 Ion implantation
Fig. 2-10 1000℃, 10s, RTA N- or P-Type Si
HfSiON Amorphous-Si
Ir or Hf Amorphous-Si
Amorphous-Si Ir or Hf Amorphous-Si
N- or P-Type Si HfSiON
S D
Fig. 2-11 Fabricated MOSEFET Ir3Si or HfSix
Amorphous-Si
N- or P-Type Si HfSiON
S D
Chapter 3
The Characteristics and Analysis of P-MOSFET
3.1 Introduction
We have measured the J-V characteristics of the MOSFETs, and then want to find out their threshold voltages by using equation (10).
( ) the mobility. Using equation (11) finds out the gd in linear region, and equation (12) gives the
effective mobility. 3.2 The Effective Metal Workfunctions
We have fabricated three different kinds of gate electrodes. The three materials are IrxSi, Ir, and Al. Fig 3.1 and Fig. 3.2 shows the measured C–V characteristics of IrxSi, Ir, and Al gates on HfSiON MOS devices. We use low-temperature Al-gated HfSiON capacitors as a
reference because pure metal deposited at low temperature has less interface reaction with high-κ dielectrics than high-temperature process. The Al-gated HfSiON capacitors have fewer
extrinsic states, and thus the Fermi-level pinning effect is not obvious in the structure [3-4].
fb ms f/ ox work functions for metal gates and Si, respectively. Q , Cf ox, tox, and equivalent-oxide thickness (EOT) are the oxide charge, capacitance, physical thickness, and EOT for high-κ dielectrics. Since the three kinds of MOS devices have the same thermal cycle(1000 ◦C RTA for 10 s)before gates formation, we could assume that the fixed charge (Qf) amount should be the same. In Fig 3-2, the various flat band voltages (Vfb) may be due to the different metal work functions. Therefore, the principal effect of Vfb shift might be due to the difference of effective workfunction (Φm,eff). The processes before gate definition are the same, and the MOS capacitors all have EOT values of 1.6nm. The shifts of C–V curves with different gate electrodes are attributed to the different work functions (Φm,eff). Ir/HfSiON after 900 ◦C RTA has a large Vfb shift of 1.15 V to Al gates (Φm,eff= 4.1eV). It results in the required high
m,eff
Φ of 5.25 eV. This work-function value is also close to 5.27 eV for Ir. The pure metal Ir gates showed no obvious pinning effect. This is due to weak bonding strengths of Ir–O or Ir–N that reduce the Fermi-level-pinning-related interface reaction. However, we observed
that Ir/HfSiON capacitors failed after 1000℃ RTA.
3.3 Thermal Stability
In Fig 3-3, Ir/HfSiON is failed after 1000℃ RTA. In order to activate the impurities, the gates have 1000℃ RTA after S/D implantation. To improve thermal stability, additional amorphous Si of 5–30 nm was inserted between Ir and HfSiON and also serve as a metal diffusion blocking layer. After 1000℃ RTA, IrxSi gate is formed. Good C–V characteristics were measured for IrxSi/HfSiON devices after the required 1000℃ RTA, although thermal stability was traded off at the Fermi-level pinning. In Fig 3-1, we obtained a high Φm,eff of 4.95 eV for IrxSi/HfSiON devices with the inserted 5-nm amorphous Si. Slow depletion for IrxSi /HfSiON devices with 30-nm amorphous Si may be due to nonuniform silicidation as examined by TEM, where locally unreacted Si was found to cause voltage drop in gate electrodes. The formation of FUSI gates is evident from the same inversion and accumulation capacitances measured in MOSFETs.
3.4 The J-V Characteristics
After 1000 ◦C RTA, Ir/HfSiON devices had high leakage currents and failed thus as shown in Fig. 3.3. On the other hand, IrxSi gates on HfSiON successfully improved thermal stability to 1000 ℃ RTA with low leakage current comparable with p+ poly-Si gates. 1000
◦C RTA is required for dopant activation after ion implantation of source and drain. The measured large Vfb shift of IrxSi is supported by SIMS profile, as shown in Fig. 3-5. Here, Ir
segregation toward amorphous Si formed IrxSi on HfSiON surface. Therefore, good thermal stability of 1000 ◦C RTA, a reasonable high Φm,eff of 4.95 eV, and a low gate dielectric leakage current can be achieved in IrxSi /HfSiON MOS capacitors at the same time. These are the few methods to achieve a high Φm,eff in Hf-based oxide p-MOS devices. There is a widely studied tuning method by impurity segregation in FUSI/SiON. However this method can not be applied to high-κ metal oxide due to the stronger interface reaction. In the following, we will study IrxSi /HfSiON devices with the thinnest 5-nm amorphous Si which has the best performance in the experiments. Compared with p-MOSFET, the Vfb of thicker Si layer is too low. Fig. 3-6 shows the transistor Id–Vd characteristics as a function of
V -g Vt for 1000 ◦C RTA IrxSi/HfSiON p-MOSFETs. The splendid results of Id–Vd curves of IrxSi/HfSiON transistors in Fig. 3-4 show little device performance degradation. Fig. 3-7 shows the Id–V characteristics of Irg xSi-gated p-MOSFETs with HfSiON as the gate dielectric. In this work, we obtained the low Vt of −0.15 V from the linear Id–V plot, g
V -g Vt for 1000 ◦C RTA IrxSi/HfSiON p-MOSFETs. The splendid results of Id–Vd curves of IrxSi/HfSiON transistors in Fig. 3-4 show little device performance degradation. Fig. 3-7 shows the Id–V characteristics of Irg xSi-gated p-MOSFETs with HfSiON as the gate dielectric. In this work, we obtained the low Vt of −0.15 V from the linear Id–V plot, g