Process Flow

N- or P-Type Si

N- or P-Type Si

Fig. 2-1 N- or P-Type Si Substrate

Fig. 2-2 RCA clean

Fig. 2-4 NH3 Plasma Nitridation N- or P-Type Si

HfSiO N- or P-Type Si

HfSiO

Fig. 2-3 Deposit HfSiO

N- or P-Type Si HfSiON Amorphous-Si

Fig. 2-5 Deposit Amorphous-Si

Fig. 2-6 Deposit Ir or Hf N- or P-Type Si

HfSiON Amorphous-Si

Ir or Hf

Fig. 2-7 Deposit Si

Fig. 2-8 Gate Definition N- or P-Type Si

HfSiON Amorphous-Si

Ir or Hf Amorphous-Si

N- or P-Type Si HfSiON Amorphous-Si

Ir or Hf Amorphous-Si

Fig. 2-9 Ion implantation

Fig. 2-10 1000℃, 10s, RTA N- or P-Type Si

HfSiON Amorphous-Si

Ir or Hf Amorphous-Si

Amorphous-Si Ir or Hf Amorphous-Si

N- or P-Type Si HfSiON

S D

Fig. 2-11 Fabricated MOSEFET Ir3Si or HfSix

Amorphous-Si

N- or P-Type Si HfSiON

S D

Chapter 3

The Characteristics and Analysis of P-MOSFET

3.1 Introduction

We have measured the J-V characteristics of the MOSFETs, and then want to find out their threshold voltages by using equation (10).

( ) the mobility. Using equation (11) finds out the gd in linear region, and equation (12) gives the

effective mobility. 3.2 The Effective Metal Workfunctions

We have fabricated three different kinds of gate electrodes. The three materials are IrxSi, Ir, and Al. Fig 3.1 and Fig. 3.2 shows the measured C–V characteristics of IrxSi, Ir, and Al gates on HfSiON MOS devices. We use low-temperature Al-gated HfSiON capacitors as a

reference because pure metal deposited at low temperature has less interface reaction with high-κ dielectrics than high-temperature process. The Al-gated HfSiON capacitors have fewer

extrinsic states, and thus the Fermi-level pinning effect is not obvious in the structure [3-4].

fb ^{ms f}/ ox work functions for metal gates and Si, respectively. Q , C^f ox, tox, and equivalent-oxide thickness (EOT) are the oxide charge, capacitance, physical thickness, and EOT for high-κ dielectrics. Since the three kinds of MOS devices have the same thermal cycle(1000 ◦C RTA for 10 s)before gates formation, we could assume that the fixed charge (Qf) amount should be the same. In Fig 3-2, the various flat band voltages (Vfb) may be due to the different metal work functions. Therefore, the principal effect of V^fb shift might be due to the difference of effective workfunction (Φ^m,eff). The processes before gate definition are the same, and the MOS capacitors all have EOT values of 1.6nm. The shifts of C–V curves with different gate electrodes are attributed to the different work functions (Φ^m,eff). Ir/HfSiON after 900 ◦C RTA has a large V^fb shift of 1.15 V to Al gates (Φ^m,eff= 4.1eV). It results in the required high

m,eff

Φ of 5.25 eV. This work-function value is also close to 5.27 eV for Ir. The pure metal Ir gates showed no obvious pinning effect. This is due to weak bonding strengths of Ir–O or Ir–N that reduce the Fermi-level-pinning-related interface reaction. However, we observed

that Ir/HfSiON capacitors failed after 1000℃ RTA.

3.3 Thermal Stability

In Fig 3-3, Ir/HfSiON is failed after 1000℃ RTA. In order to activate the impurities, the gates have 1000℃ RTA after S/D implantation. To improve thermal stability, additional amorphous Si of 5–30 nm was inserted between Ir and HfSiON and also serve as a metal diffusion blocking layer. After 1000℃ RTA, IrxSi gate is formed. Good C–V characteristics were measured for IrxSi/HfSiON devices after the required 1000℃ RTA, although thermal stability was traded off at the Fermi-level pinning. In Fig 3-1, we obtained a high Φ^m,eff of 4.95 eV for IrxSi/HfSiON devices with the inserted 5-nm amorphous Si. Slow depletion for IrxSi /HfSiON devices with 30-nm amorphous Si may be due to nonuniform silicidation as examined by TEM, where locally unreacted Si was found to cause voltage drop in gate electrodes. The formation of FUSI gates is evident from the same inversion and accumulation capacitances measured in MOSFETs.

3.4 The J-V Characteristics

After 1000 ◦C RTA, Ir/HfSiON devices had high leakage currents and failed thus as shown in Fig. 3.3. On the other hand, IrxSi gates on HfSiON successfully improved thermal stability to 1000 ℃ RTA with low leakage current comparable with p⁺ poly-Si gates. 1000

◦C RTA is required for dopant activation after ion implantation of source and drain. The measured large V^fb shift of IrxSi is supported by SIMS profile, as shown in Fig. 3-5. Here, Ir

segregation toward amorphous Si formed IrxSi on HfSiON surface. Therefore, good thermal stability of 1000 ◦C RTA, a reasonable high Φ^m,eff of 4.95 eV, and a low gate dielectric leakage current can be achieved in IrxSi /HfSiON MOS capacitors at the same time. These are the few methods to achieve a high Φ^m,eff in Hf-based oxide p-MOS devices. There is a widely studied tuning method by impurity segregation in FUSI/SiON. However this method can not be applied to high-κ metal oxide due to the stronger interface reaction. In the following, we will study IrxSi /HfSiON devices with the thinnest 5-nm amorphous Si which has the best performance in the experiments. Compared with p-MOSFET, the V^fb of thicker Si layer is too low. Fig. 3-6 shows the transistor I^d–V^d characteristics as a function of

V -g Vt for 1000 ◦C RTA IrxSi/HfSiON p-MOSFETs. The splendid results of Id–Vd curves of IrxSi/HfSiON transistors in Fig. 3-4 show little device performance degradation. Fig. 3-7 shows the Id–V characteristics of Irg xSi-gated p-MOSFETs with HfSiON as the gate dielectric. In this work, we obtained the low Vt of −0.15 V from the linear Id–V plot, g

which is consistent with the large Φ^m,eff of 4.95 eV from C–V curves and the Ir accumulation on HfSiON from SIMS. Fig. 3-8 shows the extracted hole mobilities versus gate electric fields from the measured Id–V data of Irg xSi/HfSiON p-MOSFETs. High hole mobilities of 84 and 53 cm²/V • s are obtained at peak value and 1 MV/cm effective field for IrxSi/HfSiON p-MOSFETs, respectively, which is compatible with the published data in the literature [3-4]. Good hole mobility also indicates low Ir diffusion through HfSiON to

inversion channel, even though excess Ir is necessary to prevent unreacted amorphous Si from causing gate depletion or increased Fermi-level pinning. Therefore, a highΦ^m,eff, a smallV^t, and good hole mobility are achieved in IrxSi/HfSiON p-MOSFETs.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0

5 10 15

20

_Ir

xSi(30/30nm) gate @ 1000^oC 10s RTA Ir_xSi(20/10nm) gate @ 1000^oC 10s RTA Ir_xSi(20/5nm) gate @ 1000^oC 10s RTA

Voltage (V) Capacitance (fF/

µ

m

2

)

Fig. 3-1 C–V curves of HfSiON/n-Si with various Si thickness. The device areas are 100 × 100 µm.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0

5 10 15

20

_Ir

xSi(20/5nm) gate @ 1000^oC 10s RTA Ir gate @ 900^oC 10s RTA

low temperture Al gate reference

Voltage (V) Capacitance (fF/

µ

m

2

)

Fig. 3-2 C–V curves of Ir/HfSiON, IrxSi/HfSiON (20/5nm), and Al/HfSiON.

0.0 0.5 1.0 1.5 2.0 10^-8

10^-6 10^-4 10^-2 10⁰ 10²

Gate Current ( A/cm2 )

Voltage (V)

Ir gate @ 900^oC 10s RTA

Ir gate @ 1000^oC 5s RTA (failed)

Fig. 3-3 Ig-Vg curves of Ir/HfSiON/n-Si with RTA temperatures of 1000 and 900℃ ℃.

0.0 0.5 1.0 1.5 2.0 10^-8

10^-6 10^-4 10^-2 10⁰ 10²

Gate Current ( A/cm2 )

Voltage (V)

low temperature Al gate reference Ir_xSi(30/30nm) gate @ 1000^oC 10s RTA Ir_xSi(20/10nm) gate @ 1000^oC 10s RTA Ir_xSi(20/5nm) gate @ 1000^oC 10s RTA

Fig. 3.4 Ig-Vg curves of IrxSi/HfSiON and Al/HfSiON.

0 50 100 150 200

Fig. 3-5 SIMS profile of Ir3Si gates on HfSiON at different RTA temperatures. The Ir3Si that accumulated toward HfSiON interface is found to unpin the Fermi level.

-2.5 -2.0 -1.5 -1.0 -0.5 0.0

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 10^-10

10^-9 10^-8 10^-7 10^-6 10^-5 10^-4 10^-3

I d (A)

Vg (V)

Ir3Si/HfSiON p-MOSFET

Vds = -0.1 V

Gate length = 10 µm

Fig. 3-7 Id–Vg curves of Ir3Si/HfSiON p-MOSFETs.

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 40

80 120 160 200

Universal

Ir

3

Si/HfSiON p-MOSFET

µ

eff

( cm

2

/V -s e c )

Effective field (MV/cm)

Fig. 3-8 Extracted hole mobilities from Id–Vg characteristics of Ir3Si/HfSiON p-MOSFETs.

Chapter4

The Characteristics and Analysis of N-MOSFET

4.1 The Effective Metal Workfunctions and Thermal Stability

Fig. 4-1, Fig. 4-2, and Fig. 4-3 shows the C–V and J–V characteristics for HfSix/HfSiON and Al/HfSiON capacitors, where the HfSix gate was formed at 1000℃ RTA. The Al-gated capacitor has work-function of 4.1 eV. For various amorphous Si of 50 and 10 nm on HfSiON, the capacitance density decreases as the thickness of amorphous Si increases. This implies that not all amorphous silicon is silicided in HfSix gate on HfSiON. Thus a higher flat-band voltage (V^FB) due to the Fermi-level pinning on high-κ dielectric occurs. In contrast, the HfSix

with thin 5-nm amorphous Si has the same capacitance density with Al gate. It is indicated that all amorphous Si is silicided. From the C–V shift referenced to the control Al gate, an extracted Φ^m,eff of 4.27 eV is obtained for HfSix/HfSiON. This result approaches the desired workfunction (Φ^m) of NMOSFET. The low V^FB _and Φm,eff for HfSix gate capacitors with 5-nm amorphous Si may be due to the Hf diffusion toward the HfSiON surface through thin amorphous Si that decreases the work function. In addition, low leakage current of 1.9 × 10⁻⁵A/cm at −1 V is measured at an equivalent oxide thickness (EOT) of 1.6 nm. This result shows the good thermal stability of HfSix gate on HfSiON dielectric after 1000℃ RTA.

Therefore, the experiment obtained reasonable low Φ^m,eff of 4.27 eV and a low gate leakage

current in HfSix/HfSiON MOS capacitors at the same time [4-5].

4.2 J-V Characteristics

Fig. 4-4 shows the transistor I^D _–VD characteristics as a function of V –^g V^t for the 1000

℃ RTA-annealed HfSix/HfSiON n-MOSFETs. Fig. 4-5 displays I^D _–V characteristics of the g

HfSix/HfSiON n-MOSFETs. A low V^t of only 0.14 V was measured from the linear I^D _–V g

plot, which agrees with the low Φ^m,eff of 4.27 eV from the C–V measurements. Fig. 4-6 shows the electron mobility extracted from the measured I^D _–V curves of the n-MOSFETs. g

A peak electron mobility of 216cm²/V·s was obtained for the HfSix/HfSiON n-MOSFETs.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0

5 10 15 20

25

_HfSi

X(20/50nm)@1000^oCRTA HfSi_X (20/10nm)@1000^oCRTA HfSi_X(20/5nm)@1000^oCRTA

Capacitance (fF/

µ

m

2

)

Voltage (V)

Fig. 4-1 C–V characteristics for high-temperature RTA formed HfSix/HfSiON with various amorphous Si.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0

5 10 15 20

25 Al gate HfSi

X

(20/5nm)@1000

^o

CRTA

Capacitance (fF/ µ m

2

)

Voltage (V)

Fig. 4-2 C–V characteristics for high-temperature RTA formed HfSix (20/5nm) HfSiON and low-temperature Al/HfSiON capacitors.

-2.0 -1.5 -1.0 -0.5 0.0 10

^-10

10

^-8

10

^-6

10

^-4

10

^-2

Al gate @low Temperature HfSi_X(20/50nm)@1000^oCRTA HfSi

X (20/10nm)@1000^oCRTA HfSi_X(20/5nm)@1000^oCRTA

Voltage (V) G a te Cu rrent Density (A/cm

2

)

Fig. 4-3 J - ^g V characteristics for high-temperature RTA formed HfSi^g x/HfSiON and low-temperature Al/HfSiON capacitors.

0.0 0.5 1.0 1.5 2.0 2.5

Fig. 4-4 I^D _–VD characteristics of HfSix/HfSiON n-MOSFET. The amorphous Si on HfSiON was 5 nm and gate length was 10 µm.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 10

^-10

10

^-8

10

^-6

10

^-4

10

^-2

HfSi

_X

(20/5nm)@1000

^o

CRTA HfSi

_X

/HfSiON n-MOSFET I

d

(A)

V

_g

(V)

V

_ds

= 0.1 V

Fig. 4-5 Id–Vg characteristics of HfSix/HfSiON n-MOSFET.

0.0 0.2 0.4 0.6 0.8 1.0 0

200 400 600 800

HfSi

X

(20/5nm)@1000

^o

CRTA Universal

HfSi

x

/HfSiON n-MOSFET

Effective field (MV/cm) µ eff ( cm 2 /V -se c )

Fig. 4-6 Electron mobility of HfSix/HfSiON n-MOSFETs.

Chapter5 Conclusion

In the experiment, we have obtained good device performance of IrxSi/HfSiON p-MOSFETs with a high Φ^m,eff of 4.95 eV, a small Vt of −0.15 V, a peak hole mobility of 84 cm²/V・s, and 1000℃RTA thermal stability. For NMOSFET, a low Φ^m,eff of 4.27eV, threshold voltage of 0.14V, and a mobility of 216cm²/V·s are obtained. They are obviously that the processes can be integrated in current technology. On the other hand, we will study hard to decrease EOT by replacing the high-κgate dielectrics in the future. The threshold voltages of devices are needed to decrease, and avoid the Fermi-Level pinning. However, the research of this work proved that this is an effective way to meet the ITRS roadmap after 2008.

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[3-8] M. Koyama, Y. Kamimuta, T. Ino, A. Kaneko, S. Inumiya, K. Eguchi, M. Takayanagi, and A. Nishiyama, “Careful examination on the asymmetric Vfb shift problem for Poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the Poly-Si interface with small EOT expense”, IEDM Tech. Dig., pp. 499–502, 2004.

[3-9] H. B. Michaelson, “The work function of the elements and its periodicity”, J. Appl.

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[4-1] H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P. J. Tobin, D. C. Gilmer, D.

Triyoso, M. E. Ramón, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. I.

Hegde, R. Noble, M. Jahanbani, C. El Chemali, and B. E. White, “Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal stack,” IEDM Tech. Dig., pp. 821–824, 2004.

[4-2] C. S. Park, B. J. Cho, L. J. Tang, and D. L. Kwong, “Substituted aluminum metal gate on high-κ dielectric for low work-function and Fermi-level pinning free,” in IEDM Tech. Dig., pp. 299–302, 2004.

[4-3] D. S. Yu, K. C. Chiang, C. F. Cheng, A. Chin, C. Zhu, M. F. Li, and D. L. Kwong,

“Fully silicided NiSi : Hf/LaAlO3/ Smart-Cut-Ge-On-Insulator n-MOSFETs with high

electron mobility”, IEEE Electron Device Lett., vol. 25, no. 8, pp. 559–561, Aug. 2004.

[4-4] C. Y. Lin, M. W. Ma, A. Chin, Y. C. Yeo, C. Zhu, M. F. Li, and D. L. Kwong, “Fully silicided NiSi gate on La2O3 MOSFETs”, IEEE Electron Device Lett., vol. 24, no. 5, pp.

348–350, May 2003.

[4-5] A. Veloso, K. G. Anil, L. Witters, S. Brus, S. Kubicek, J.-F. de Marneffe, B. Sijmus, K.

Devriendt, A. Lauwers, T. Kauerauf, M. Jurczak, and S. Biesemans, “Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs”, in IEDM Tech. Dig., pp. 855–858, 2004.

[4-6] S. J. Rhee, C. S. Kang, C. H. Choi, C. Y. Kang, S. Krishnan, M. Zhang, M. S. Akbar, and J. C. Lee, “Improved electrical and material characteristics of hafnium titanate multi-metal oxide n-MOSFETs with ultra-thin EOT (∼ 8 Å) gate dielectric application,” in IEDM Tech. Dig., pp. 837–840, 2004.

Vita

姓名：黃俊哲 性別：男

出生年月日：民國 73 年 8 月 15 日 籍貫：台灣省台南縣

住址：台南縣佳里鎮安西里安西 56-32 號

住址：台南縣佳里鎮安西里安西 56-32 號

在文檔中 金屬矽化物-高介電常數介電質-半導體場效應電晶體之電性研究 (頁 36-0)