• 沒有找到結果。

The proposed selectable multi-output DC-DC converter which utilizes charge pumps in thesis can only be fabricated with the high voltage process to exceed the required voltage level. And the output voltage VDD is directly from the input voltage source. Furthermore, the output voltage is changed with the input voltage without regulation. The future works of the thesis is to design multi-stage charge pumps which can operate under the low voltage process and can exceed high output voltage at the same time. The negative to positive charge pump can be added into the circuits to help the power efficiency when delivering the VDD voltage level to the output terminal. The regulation circuit for the charge pumps can be added in the future to regulate the output voltage while the input supply voltage is changing.

References

[1] F. Goodenough, “Low Dropout Linear Regulators,” Electronic Design, pp. 65-77, May 13, 1996.

[2] Robert W. Erickson and Dragan Maksimovic, Fundamentals of Power Electronics, 2nd ed., Norwell, MA: Kluwer Academic Publishers, 2001

[3] K. Sawada, Y. Sugawara, and S. Masui, “An on-chip high-voltage generator circuit for EEPROM’s with a power supply voltage below 2V,” in Symp. VLSI Circuits Dig. Tech.

Papers, 1995, pp. 75-76.

[4] T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A.

Sato, J. Yugami, H. Kume, and K. Kimura, “Bitline clamped sensing multiplex and accurate high voltage generator forquarter-micron flash memories,” IEEE J. Solid-State Circuits, vol. 31, pp. 1590–1600, Nov. 1996

[5] Y. Nakagome, et al., ”An experimental 1.5-V 64 Mb DRAM,” IEEE J. Solid-State Circuits, vol. 26, pp. 465-472, April 1991.

[6] M. M. Ahmadi and G. Jullien, “A full CMOS voltage regulating circuit for bioimplantable applications,” in Midwest Symp. Circuits Syst., 2005, vol. 2, pp. 988-991.

[7] Dickson, J. “On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique.” IEEE Journal of Solid-State Circuits, Vol. 11, No 6, pp. 374-378, June 1976.

[8] T. Tanzawa and T. Tanaka, “A dynamic analysis of the Dickson charge pump circuit,”

IEEE J. Solid-State Circuits, vol. 32, pp. 1231-1240, Aug. 1997.

[9] A. Cabrini, L. Gobbi, and G. Torelli, “Theoretical and experimental analysis of Dickson charge pump output resistance,” in Proc. IEEE Int. Symp. Circuits Syst., 2006, pp.

2749-2752.

[10] Jongshin Shin, et al., “A new charge pump without degradation in threshold voltage due to body effect [memory applications],” IEEE J. Solid-State Circuits, vol. 35, pp.

1227-1230, Aug. 2000.

[11] A. Umezawa, et al., “A 5-V-only operation 0.6-µm flash EEPROM with row decoder scheme in triple-well structure,” IEEE J. Solid-State Circuits, vol. 27, pp. 1540-1545, Nov. 1992.

[12] L. Mensi, et al., “A new integrated charge pump architecture using dynamic biasing of pass transistors,” in Proc. European Solid-State Circuits Conf., 2005, pp. 85-88.

[13] C. Lauterbach, W. Weber, and D. Romer, “Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps,” IEEE J. Solid-State Circuits, vol. 35, pp. 719-723, May 2000.

[14] Lin, H., N. Chen, and J. Lu. “Design of modified four-phase CMOS charge pumps for low-voltage flash memories.” Journal of Circuits, System, and Computers, Vol. 11, No. 4, pp.393-403,2002.

[15] Pan, et al. “Four phase charge pump operable without phase overlap with improved efficiency.” U.S. patent 7,030,683.

[16] Wu, J. T. and L. K. Chang. “MOS charge pumps for low-voltage operation.” IEEE Journal of Solid-State Circuits, Vol. 33, No. 4, April 1998

[17] Tsang, B. and E. Ng. “Switched capacitor DC-DC converters: Topologies and applications.” www.ocf.berkeley.edu/~eng/classes/EE290cPresentation.ppt.

[18] Wu, J. T. and Chang, K. L. “Low supply voltage CMOS charge pumps,”

www.ics.ee.nctu.edu.tw/~jtwu/publications/pdf/97vlsi-cp.pdf.

[19] M. M. Ahmadi and G. Jullien, “A new CMOS charge pump for low voltage applications,” in IEEE Int. Symp. Circuits Syst., 2005, vol. 5, pp. 4261-4264.

[20] Lon-Kou Chang and Chih-Huei Hu, “High efficiency MOS charge pumps based on exponential-gain structure with pumping gain increase circuits,” IEEE Tran. Power Electronics, vol. 21, pp. 826-831, May 2006.

[21] Ming-Dou Ker, Shih-Lun Chen, and Chia-Shen Tsai, “Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes,” IEEE J.

Solid-State Circuits, vol. 41, pp. 1100-1107, May 2006.

[22] Khoman Phang and D. A. Johns, “A 1V 1mW CMOS Front-End with on-chip Dynamic Gate Biasing for a 75Mb/s Optical Receiver,” IEEE Int. Solid-State Circuits Conf. Dig.

Tech. Papers, pp. 218-219, Feb. 2001.

[23] Y. Moisiadis, I. Bouras, and A. Arapoyanni, “A CMOS charge pump for low voltage operation,” Proc. IEEE Int. Symp. Circuits Syst., 2000, vol. 5, pp. 577-580.

[24] Hoi Lee and P. K. T. Mok, “Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler,” IEEE J. Solid-State Circuits, vol. 40, pp. 1136-1146, May 2005.

[25] TianRui Ying, Wing-Hung Ki, and Mansun Chan, “Area-efficient CMOS charge pumps for LCD drivers,” IEEE J. Solid-State Circuits, vol. 38, pp. 1721-1725, Oct. 2003.

[26] Kyeong-Sik Min, et al., “CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits,” IEEE Int. Symp. Circuits Syst., 2002, vol. 5, pp. V-545 - V-548.

[27] Lin, H., H. K. Chang, and C. S. Wong. “Novel high positive and negative pumping circuits for low supply voltage.” IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 238-241, May 20-June 2, 1999.

[28] Naso, et al. “Negative-voltage charge pump with feedback control.” U.S. Patent 5,168,174.

[29] Jinbo, T., et al. “A 5-V-only 16-Mb flash memory with sector erase mode.” IEEE Journal of Solid-State Circuits, Vol. 27, pp. 1547-1553, 1992.

[30] Atsumi, S., et al. “A 16-Mb Flash EEPROM with a new self-data-refresh sheme for a sector erase operation.” IEEE Journal of Solid-State Circuits, Vol. 29, pp. 461-469, 1994 [31] Y. E. Tsiatouhas, “A stress-relaxed negative voltage-level converter,” IEEE J.

Transactions on Ckts. & Sys, vol 54, no. 3, March 2007

[32] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999.

[33] T. Ying, W. H. Ki, and M. Chan, “Area-efficient CMOS charge pumps for LCD drivers,”

IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1721–1725, Oct. 2003.

[34] W. H. Ki, F. Su and C. Y. Tsui, “Charge redistribution loss consideration in optimal charge pump design,” IEEE Int’l Symp. On Ckts. & Sys., Kobe, Japan, pp. 1895-1898, May 2005.

[35] F. Su, W. H. Ki, and C. Y. Tsui, “High efficiency cross-coupled doubler with no reversion loss,” IEEE Int’l Symp. On Ckts. & Sys., May 2006.

[36] Alan Hastings, “The Art of Analog Layout,” 2nd ed, Prentice Hall, 2001.

相關文件