Dynamic CTS Charge Pump

The above-mentioned static CTS charge pump has a critical drawback, the reverse leakage current. In order to fix the defect, a dynamic CTS charge pump [17] [18] is presented in Fig. 18. Each stage in the dynamic CTS charge pump adds an NMOS transistor and a PMOS transistor to control the gate voltage of the charge transfer transistor. In the first stage, an NMOS MN0 transistor and a PMOS MP0 transistor are added to control the gate of the charge transfer transistor M₀. The PMOS M_P0 controls the gate of M₀ connected to a higher voltage potential at node n2 from the next stage to fully turn on M0 while transferring the charge to the next stage. And in the next phase where the charge transfer transistor M₀ must be turned off, the NMOS transistor MN0 will take the responsibility to control the gate of M0. The gate of M₀ is connected to a lower voltage potential at node V_DD and insure that M₀ is turned off completely to prevent the reverse leakage current. Although the extra NMOS and PMOS will increase the size of the chip, the gain of the charge pump can be raised and the efficiency

can be improved. potential. But during the previous phase, the gate of M_D4 is not higher enough to turn on M_D4 to charge the capacitor C5 due to the heavy load at the output. The node n5 will not be higher enough to fully turn on pass transistor M₃. To solve this problem, an ameliorated circuit of the dynamic CTS charge pump is shown in Fig. 19. A bootstrap circuit including two transistors and two capacitors is added to the final stage. This addition circuit is added to ensure that the pass transistor of the final stage can be fully turned on correctly. It uses a pair of cross-coupled NMOS M_B1 and M_B2 to charge the capacitors, and ensure that the source of the NMOS MB1 is at a higher voltage potential.

VDD

Fig. 19 Dynamic CTS charge pump with an extra level shifter

There are some improvement researches based on above-mentioned circuits. Such as the charge pump implemented by utilizing PMOS transistors [19]. Design and analysis of the output stage to improve the gain and efficiency of the charge pump [20]. Extra branch added to turn on each other [21].

2.2.6 Favrat Charge Pump

The above-mentioned CST charge pumps have improved voltage gain and efficiency.

But there is still some deficiencies in the CTS charge pump, such as the gate-oxide reliability for low-voltage operation in CMOS process [21]. Each transistor in the CTS charge pump needs to endure 2V_DD voltage. When using a low voltage process and 2V_DD exceeds the process’s maximum voltage, the transistors might breakdown and don’t function as you want.

To solve this problem, a structure called cross-coupled charge pump is proposed.

V

^DD

Fig. 20 Cross-coupled charge pump

The cross-coupled charge pump is shown in Fig. 20. The cross-coupled is proposed in the past for DRAM applications [5]. The cross-coupled charge pump uses two different phases charge pumps. The pass transistors of one charge pump are controlled by the other charge pump in the cross-coupled structure. By doing so, the control circuits can be reduced.

In the Fig. 20, while the left side charge pump is charging capacitor C1 through ML1 and MB2, the right side charge pump is pumping the output to higher voltage through M_R2 and M_B3. The ripple of the charge pump can be reduced by applying cross-coupled structure. Because of the two charge pumps is connected together and operate at different phase. And there are two transistors sharing the stresses in each stage, therefore each transistor sustains only the voltage

∆V. Hence, it decreases the risks of break through or breakdown in transistors. The output transistors ML2 and MR2 in the cross-coupled charge pump shown in Fig. 20 run into a problem that the bulk nodes of them are possibly not connected to the highest voltage. To

overcome this problem, a more efficiency cross-coupled charge pump is proposed by Pierre

Fig. 21 Favrat charge pump

The Favrat charge pump differs from the conventional cross-coupled charge pump at the output stage. An extra capacitor CH and extra transistors ML3 and MR3 are added to the circuit to solve the problem in cross-coupled charge pump. The capacitor C_H will be charged to the highest voltage 2VDD through ML3 and MR3. The bulk terminals of the PMOS pass transistors are connected to capacitor C_H and push it to the highest voltage 2V_DD. By doing so, the turn on resistors RON of the PMOS pass transistors will be reduced and the gain and efficiency of the Favrat charge pump can be extended. There are a number of improved charge pumps proposed on the basis of Favarat charge pump. The voltage doubler which is designed to operate at low voltage proposed in [22]. The reduction of the leakage current and conduction

loss in the cross-coupled charge pump and improves the power efficiency [23] [24]. The structure proposed in [25] to reduce the chip area. The body effect eliminating technique utilizing triple-well process [26].

2.3 Negative Charge Pump

The charge pumps mentioned above are all positive charge pumps. The positive charge pumps boost the input voltage to a higher voltage scale which exceeds the source voltage from power supply. If the voltage can be boosted to a higher level, the voltage can be lowered to a lower level too. In modern IC design, the negative voltage which is lower than the ground level is needed. Such as on a DRAM chipset, for the sake of reducing the background leakage current, a negative voltage which is lower than the ground level is utilized to bias the p-substrate instead utilizing the ground voltage level.

2.3.1 Conventional Negative Charge Pump

A conventional negative charge pump is shown in Fig. 22. It is a k-stage 2-phase negative charge pump [27]-[29]. Compare with the positive Dickson charge pump as shown in Fig. 14, the NMOS in the positive Dickson charge pump has been changed to the PMOS in the negative charge pump. The NWELL of the PMOS in the negative charge pump is connected to the most positive voltage per stage. And the source voltage of the first stage in the negative charge pump is connected to ground instead of V_DD in the positive charge pump.

clk clkb

M

¹

n

¹

M

²

n

²

n

^k

M

^k+1

V

^OUT

C

¹

C

²

Fig. 22 Conventional k-stage 2-phase negative charge pump

In Fig. 22, the PMOS pass transistors are connected in diode fashion. The operations of the negative charge pump will be given in this paragraph. At the beginning of the pump, the input clock clk is at high as a voltage and the diode connected pass transistor M1 is turned on and the positive charge from the pump output node n₁ of the first stage will be removed and transfers it to the ground node. And in the next phase, clk is pulled low. Since charge is carried away from node n₁ in the previous phase, the voltage level stored in the capacitor C₁ will make the output node n1 voltage a negative level. At the same time, the clock clkb is high and turns on the pass transistor M₂ and the positive charge on n₂ will be removed and transfer to n1. And the next clock phase, clkb is pulled low and node n2 is boosted to a lower negative voltage. The current direction is going through from output node to the input node just opposite of the positive charge pump. The output voltage of the k-stage negative charge pump as shown in Fig. 22 is give by Equation 14.

2.3.2 Negative Charge Pump Utilize Triple

Well Technology

The above-mentioned negative charge pump has the threshold voltage problem [30]. As shown in the Equation 14, the bigger the threshold voltage is, the lower the output voltage can achieve. Therefore if we want to increase the output voltage and the efficiency of the negative charge pump, the threshold voltage of the pass transistors must be reduced. The above-mentioned conventional negative charge pump utilize PMOS as its pass transistor. The bulk terminal of the PMOS transistor in a standard CMOS process must be connected to the highest voltage of the chip. And when it comes to a negative charge pump, the threshold voltage is due to the voltage VSB across source and bulk. The source voltage of the transistor in a negative charge pump might be a negative voltage lower than the ground level, and the bulk of PMOS transistor is connected to the highest voltage. It makes VSB high and causes the threshold voltage to be large. The large threshold voltage leads to the decrease of the output voltage. So if we want to increase the voltage gain of the negative charge pump, wee need to decrease the threshold voltage V_t. To decrease the threshold voltage, it can be done by reducing the source to bulk voltage VSB.

p-substrate PWELL

NWELL NWELL

Deep NWELL Gate

Fig. 23 Deep NWELL n-type transistor profile

The source to bulk voltage VSB must be minimized to reduce the threshold voltage. The NWELL of the PMOS transistor needs to be connected to a higher voltage such as V_clk of the input voltage level. But in a negative charge pump, because of the negative output voltage, an approach to reduce V_SB is to switch NWELL potential down to the ground level. By doing so, the threshold voltage Vt can be reduced due to the reduction of the source to bulk voltage VSB. Though this approach can reduce V_SB, but when the stage increases and the output voltage goes to a more negative voltage, the VSB is still too large. Therefore if we want to further reduce V_SB, we need the help from the process technology. A deep NWELL NMOS transistor is introduced in the triple well process technology as shown in Fig. 23. In a normal CMOS process, the NMOS is processed directly on top of p-substrate. If the source of a normal NMOS is boosted to a negative voltage potential, latch-up issues could arise due to the junction forward biasing. A deep NWELL NMOS adds an extra well called deep NWELL as shown in Fig. 23. It will isolate a PWELL from p-substrate. If we connect p-substrate and the extra PWELL together, it is just like a normal NMOS. But with the additional PWELL, the bulk of NMOS can be connected to negative voltage potential. Since the source and bulk of

NMOS can both be connected to negative voltage, source to bulk voltage VSB can be greatly reduced. Therefore the threshold voltage V_t is reduced.

clk clkb

M

¹

M

²

M

k

V

OUT

n

1

n

2

n

k

C

1

C

2

clkb C

^k

Fig. 24 k-stage 2-phase negative charge pump with a deep NWELL transistor

With the help of the triple well process technology, a negative charge pump utilizing deep NWELL NMOS transistors is shown in Fig. 24. The bulk and source is butted together to eliminate the body effect. The operation of the negative charge pump in Fig. 24 is the same as above-mentioned conventional negative charge pump.

Chapter 3

The Description and Analysis of the Proposed Circuit

3.1 Selectable Multi-Output DC-DC Converters

In some applications, it needs different voltage sources to supply a single node of the chip. Such as the power sources for LCD panels, they need different voltage scale to charge and discharge the liquid crystal capacitors. When we have only one supply voltage scale, we need different DC-DC power converters with different output voltage scales. Among the DC-DC power converters, inductive switching converters need external components as inductors and charge pumps need external components as capacitor. The external component capacitors occupy smaller chip area than the inductors. The amount of external components will increase while we have different DC-DC converters in our chip. Therefore, if we want to reduce the chip area, the external component size must be minimized. The conventional selectable multi-output DC-DC converter utilizes inductive switching converters which occupies larger chip area. The proposed selectable multi-output DC-DC converter utilizes charge pumps as its power converters will reduced the chip area and cost.

3.1.1 Conventional Structure

As mentioned above, the conventional structure of selectable multi-output DC-DC converter uses inductive switching converters as its DC-DC converters. Suppose that the output node needs four voltages, we need four inductive switching converters to supply the different voltage. At least four inductors are needed and they will occupy a large chip area.

Inductive

Fig. 25 Conventional structure of a selectable multi-output converter

As shown in Fig. 25, it is the structure of a selectable multi-output converter. It uses inductive switching converters as its DC-DC power converters. In Fig. 25, there are four

voltages for output switching, VDD, 2VDD, VDD/2 and the ground. The voltage potentials VDD

and ground are directly supplied by the input power supply, the other two voltage potentials 2VDD and VDD/2 need two inductive switching converters to generate. The structure can be extended if the output needs more different voltage potentials.

3.1.2 Proposed Structure

The above-mentioned conventional selectable multi-output DC-DC converter which utilizes inductive switching DC-DC converters demands large chip area. The control circuits, feedback loop circuits and compensation circuits of the inductive switching DC-DC converters also enlarge the size of the conventional structure. The applications that need a negative voltage potential lower than the ground level mentioned before can’t use the conventional structure. Because the inductive switching DC-DC converter can only generate voltages higher or lower than the input voltage, negative voltage lower than the ground is unavailable. Therefore, we propose a new structure of the selectable multi-output DC-DC converter. The proposed structure is shown in Fig. 26. As you can see in Fig. 26, the DC-DC power converters of the proposed selectable multi-output DC-DC converter is replaced by charge pumps. Charge pumps need no feedback and compensation circuits in the applications that do not need accurate output voltage such as LCD panel gate drivers, charging and discharging of the liquid crystal capacitors and flash memories. The replacement of charge pump can reduce the chip area and the cost. And one of the great contribution is that charge pump can generate negative voltage potential which is lower than the ground level.

Cross-Coupled

Fig. 26 Selectable multi-output DC-DC converter utilize charge pumps

The proposed structure as shown in Fig. 26 has four voltages 2VDD, VDD, -VDD and ground for selection. The voltages V_DD and ground are directly supplied by the input power source. The voltage 2VDD is generated by an improved cross-coupled charge pump which will be introduced in the next section. And the negative voltage –V_DD is generated by a cross-coupled negative charge pump which will be discussed in detail in the following sections. As you can see from Fig. 26, there are four switches separately controlled by four control circuits to select the output voltage. There is only one voltage delivered to the output at one time. You can select the voltage arbitrarily as you want to decide which voltage is delivered to the output at the mean time.

3.2 Improved Charge Pump

In this section the cross-coupled charge pump is discussed in detail. The shoot-though current loss may occur in a cross-coupled structure. The shoot-though current will lead to the reduction of voltage gain and efficiency. The shoot-though current here is the current flow from output to input. For a charge pump which boosts the input voltage to a higher level, the current should flow from input supply to output node. Therefore the shoot-though current is a reversion loss which we do not want it to appear. An improve structure of the cross-coupled charge pump will be proposed to reduce the shoot-though current loss. The more the shoot-though current loss can be reduced, the higher gain and efficiency can be achieved.

3.2.1 Shoot-Though Current Loss

In the cross-coupled charge pump such as the Favrat charge pump, there is a loss called shoot-though current loss. It is due to the control of the pass transistors during switching. As shown in Fig. 27, the voltage transition at the node V₁ and V₂ can not be controlled during switching. The shoot-though currents will occur on pass transistors ML1, ML2, MR1 and MR2

which are controlled by node V₁ and V₂ during switching. The currents I₁ and I₂ are the shoot-through currents which arise in pass transistors ML1 and MR1. And the currents I3 and I4

are the shoot-through currents which arise in pass transistors M_L2 and M_R2. Because the cross-coupled charge pump is a symmetric structure, therefore the shoot-through current is generated each half cycle in similar way.

V^DD

Fig. 27 Shoot-though current generation mechanism in Favrat charge pump

Fig. 27 shows the shoot-through current generation mechanism. The voltages V1 and V2

produce shoot-through current in four different ways. Voltages V₁ and V₂ are the control of the pass transistors ML1, ML2, MR1 and MR2 and they are switched between VDD and 2VDD. Let’s see the generation of the soot-through current I₁, it is due to the leakage from pass transistor ML1. During the switching where V1 increased from VDD to 2VDD and V2 decreased from 2V_DD to V_DD, at the transition in the initial phase of clock signal where

2 1 tn 1 DD

V − ≥ V V and V > V

(14)

Vtn is the threshold voltage of pass transistors ML1 and MR1. Under this condition, the first shoot-through current occurs and flow from node 1 through M_L1 to the input power supply VDD. The second shoot-through current is generated in a similar way as the symmetry of the cross-coupled structure. Shoot-through current I₂ flows from node 2 through M_R1 to the input power supply voltage when

1 2 tn 1 DD

V − V ≥ V and V > V

(15)

AS shown in Fig. 27, the third and fourth shoot-through currents leak from output node the input power supply. This occurs when pass transistor pairs M_L1 and M_L2, M_R1 and M_R2 are simultaneously conducted, respectively.

V

^DD

Fig. 28 The occurrence of the shoot-though current during switching

As shown in Fig. 28, The duration of the shoot-through currents I1 and I2 are the blue regions. And the red regions are the duration that shoot-through currents I₃ and I₄ occur. I₃ occurs when ML1 and ML2 are simultaneously conducted. ML2 is turned on when

2

2

_{DD tp DD}

2

_tp

V ≤ V − V and V > V

(16)

Based on equation (14), the minimum input power supply voltage V_DD to turned on transistor ML1 during the turning on of the transistor ML2 is given by

( )

max 2 , 2 2

DD tp tp tn tp tn

V ≥ V V + V = V + V

(17)

The red regions where simultaneous conduction occurs in Fig. 28 increases with the input supply voltage VDD. Therefore, the higher the input supply voltage is, the larger the region of simultaneous conduction is. It will lead to larger power loss and poor power efficiency.

3.2.2 Proposed Charge Pump with Loss Reduction Technique

From the discussion in previous section, we want to develop an efficient structure of cross-coupled charge pump to reduce the shoot-through current during switching and the reversion loss. The proposed cross-coupled charge pump circuit is shown in Fig. 29.

V^DD

Fig. 29 Proposed cross-coupled charge pump with loss reduction technique

As shown in Fig. 29, in the proposed structure, two transistors (M_L4, M_R4) and two resistors (R1, R2) are added into the circuit. Transistors ML4 and MR4 are controlled by an extra level shifter to ensure the proper turning on and off. The principle of operation of the

As shown in Fig. 29, in the proposed structure, two transistors (M_L4, M_R4) and two resistors (R1, R2) are added into the circuit. Transistors ML4 and MR4 are controlled by an extra level shifter to ensure the proper turning on and off. The principle of operation of the

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