Future Work

Some aspects need to be improved below:

1. In the quad-bands frequency synthesizer design, the power of quad-bands signals should be increased to above -10dBm for practical telecommunication system.

Common drain structure isn’t suitable for large output power design, since common drain amplifier is intrinsically a power loss structure. The quad-bands output buffer structure should be modified. Common source output buffer is preferred because it provides power gain rather power loss.

2. The high frequency dividers in quad-bands frequency synthesizer design should be modified to provide more balanced output waveform.

3. In the integer-N frequency synthesizer design, the high frequency divide-by-2 circuit is connected to a buffer. This buffer cause signal voltage swing degradation. This buffer should be removed to increase signal voltage swing.

4. The charge pump in this thesis is a current mismatching circuit. The mismatching current will results in reference spurious noise and distort signal spectrum. A new charge pump structure has been designed and will integrate to frequency synthesizer in future designs.

5. High efficient frequency detector research is going on to complete the new all-digital frequency synthesizer.

Reference

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Publication List

1. Kuo-Hua Cheng, Cheng-Hung Chen, Po-Da Chen and Christina F. Jou, “A 20.5-mW, Fast-Switching Integer-N Frequency Synthesizer of 5.2GHz WLANs “, has been accepted by International Symposium on Communications and Information Technologies 2004 (ISCIT 2004), but not published due to economic problem.

2. Cheng-Hung Chen, Wei-Cheng Lien and Christina F. Jou, “A High-Integration, Quad Application Bands Σ∆ Fraction-N Frequency Synthesizer in 0.18-µm Standard CMOS Process”, has been submitted to Asia-Pacific Microwave Conference 2005.