Chapter 3 802.11a Integer-N Frequency Synthesizer
3.9 Measurement
3.9.2 Measurement V.S. simulation results
We perform open loop measurement first. The measured DC currents are 13mA for VCO and output buffer, 7mA for frequency divider. Measured DC current fits the simulation FF corner (11.6mA for VCO and buffer, 7mA for divider). Apply spectrum analyzer to measure voltage controlled oscillator output signal power, phase noise and tuning range. The measured output signal power is -26dBm, while the simulation is -20dBm. The measurement result is shown in Fig.3-21. Measured frequency tuning range is 4.6-5.25 GHz, while simulation result of FF corner is 5.23-5.88 GHz. The measured frequency is about 630MHz lower than simulation. The measure result is shown in Fig.3-22. Measured phase noise is -104.33dBc/Hz @1MHz (-54.33 -10log105=-104.33 dBc/Hz @1MHz), while the simulation result is -105dBc/Hz
@1MHz. The phase noise performance is quite close to simulation results and shown in Fig.3-23.
Fig.3-22 Tuning range measurement
Fig.3-23 Phase noise measurement
The frequency synthesizer didn’t lock to the wanted frequency. The problem may results from 2 main reasons. First, the VCO signal swings are not sufficient to push frequency dividers. The measured signal is 6dBm less than simulation. In this design, low power consumption is our design guide. Each circuit is designed to consume
signals were not designed to have large power output. The simulated VCO signal swing is 250mV. The fist divide-by-2 circuit will function if the input signal swing is large than 200mV. 6dB power loss means voltage is degrade by a factor of 2, which means the measured signal swing is only 125mV. Since VCO output signal swing is only 125mV, the divider is unable to function. Second, at the design step of high frequency divide-by-2 circuit, the loading and parasitic effect is very serious. To deal with this problem, we utilized a common drain buffer amplifier. Although the loading and parasitic problems have been solved, the divider output voltage swing is even smaller than VCO output signals. The buffer amplifier consumes DC power and voltage swing, makes system harder to design. To examine the parasitic problem, we use Caliber extraction tools to extract the parasitic capacitances and resistances. The parasitic capacitance of the first divide-bu-2 circuit is 20fF. This parasitic capacitance should be taken into account in the simulation step. By careful consideration, the common buffer amplifier should be eliminated to increase system stability and functionality. This work will be redesigned with no divider buffer amplifier and higher VCO output power.
Chapter 4
An 8-bit AFC Voltage Controlled Oscillator
In this chapter, a high frequency resolution voltage controlled oscillator (VCO) design will be discussed. PMOS varactors are used to achieve 8-bits frequency resolution. This circuit is a step stone to an all-digital complete integration frequency synthesizer design. By designing a high frequency resolution VCO and using a digital coding method to control VCO varactor banks and VCO control voltage, the dream of whole-new all-digital frequency synthesizer architecture will come true. In this new structure, traditional loop filter, used to be implemented off-chip, will be omitted. This new structure will help to increase RF system integration and speed up frequency settling time by several times.
4.1 Proceeding on All-Digital Frequency Synthesizer
4.1.1 Background
Traditionally, the loop filter of frequency synthesizer is an off-chip circuit due to large capacitances and resistances. For SOC application, this will definitely cause problem. In order to integrate loop filter into chip, we propose an all-digital frequency synthesizer architecture.
In the voltage controlled oscillator, each varactor bank code tuning range covers neighboring varactor bank codes by 50%. Therefore, overall tuning range of VCO is:
( )
1
2
n 1 *0.5BW = +⎡⎣ − ⎤⎦ , where ƒ is average tuning range of each varactor bank f code. 802.11a application specifies a usable band from 5.15GHz to 5.35GHz.
Consider process variation, a 600MHz VCO tuning range is sufficient. Substitute BW=600MHz into above expression, the average varactor tuning range ƒ will be 4.67MHz.
The center frequency tolerance in 802.11a specification is ±20ppm. If center frequency is 5.25GHz, the allowable frequency shifting is ±105KHz. In an 8-bits resolution VCO, average varactor bank code tuning range is 4.67MHz. If we design the control voltage of VCO to have more than 6-bits resolution, the 802.11a specification can be met. We conclude that a 14-bits all-digital frequency synthesizer is practical for 802.11a application. More than that, if we adopt dichotomy logic to design frequency synthesizer comparison mechanism, after 14 decisions system will lock at wanted frequency. Take reference frequency = 10MHz for example, every 0.1µs can determine a bit. Total frequency settling time will be only 14*0.1=1.4µs.
Compare to traditional frequency synthesizer settling time of 40µs, this new structure shows a great potential.
4.1.2 Proposed Architecture [21]
The 14 bits should be divided into 2 parts, 8 bits for VCO bank coarse tuning, another 6 bits is left for VCO control voltage fine tuning. Because the VCO is the most important component in frequency synthesizer, it must be proven before been integrated into all-digital frequency synthesizer. The proposed new frequency
the frequency detector that can discriminate which of reference signal or divider signal has higher frequency in a few signal pulses. At first, VCO control voltage is connected to Vref. After first eight comparisons, the 8 VCO varactor banks will be set.
Then VCO control voltage is switched to DAC output signal to perform frequency fine tuning. In six more frequency comparisons, the frequency synthesizer will lock at wanted frequency.
Fig.4-1 Proposed new all-digital frequency synthesizer architecture
4.1.3 Frequency Detector Design [22][23]
The analog frequency detector is shown in Fig.4-2. It is composed of two quadrature mixers and two low pass filters. The circuit principle is as following:
1 2 a 1 2
By observing Va and Vb, we can tell which of the incoming signal has higher frequency.
Fig.4-2 Analog frequency detector
Next, we try to form a digital type frequency detector. The two quadrature mixers is replaced by two DFFs. The four ANDs will generates the discrimination signals AB’C, A’BC’, AB’C’ and A’BC. The discrimination signals conclude all possible combinations about whether Div leads or Ref leads. After JKFF, frequency detector outputs the discrimination results. “H” states Div is slower than Ref, “L” states Div is faster than Ref. “S” means that these two signals have same frequency.
Fig.4-3 Digital frequency detector
Fig.4-3 is further modified to a balanced structure, shown in Fig.4-4, to increase frequency discrimination range.
D
Fig.4-4 Modified balance digital frequency detector
Although this frequency detector can discriminate frequency precisely, the discrimination speed is too slow if the incoming signals don’t differ too much in frequency. This problem troubles us a lot, since the all-digital frequency synthesizer depend on this circuit to shorten frequency settling time. A phase synchronizer may be needed to solve this problem. With the help of phase synchronizer, we can discriminate frequency in only one reference clock. Fig.4-5 illustrates the function of a phase equalizer in this frequency detector design.
Ref
Fig.4-5 Function of phase synchronizer to aid frequency detector design
4.2 8 bits VCO Architecture [24][25][26]
Since the average tuning range of each varactor bank code is only 4.67MHz, the varactor model provided by TSMC is not suitable in this design. In this design, we implement these varactors by PMOS with Drain, Source and Bulk are shorted together.
The PMOS varactor layout is shown in Fig.4-6[27]. The tuning characteristic of PMOS varactor is shown in Fig.4-7.
Fig.4-6 PMOS varactor layout
VCO is the core circuit in the frequency synthesizer. In most RF design, we use LC-tank oscillator instead of ring oscillator for better phase noise. For image cancellation, we hope VCO can provide quadrature phase output signal. There are three ways to generate quadrature signals: divide-by-two circuit [28]; RC-polyphase network [29]; and two VCOs cross connect with each other [30]. Using divide-by-two circuit needs to design a VCO operate at the double frequency of original frequency. A VCO with RC-polyphase network consumes less power than others, but RC-polyphase is a signal power hungry circuit. For accurate quadrature phase signal and large output signal power reasons, we design two VCOs differentially connect to each other to generate quadrature signal. The whole schematic of the 8-bits frequency resolution quadrature VCO is shown in Fig.4-8. The architecture of cross-coupled pairs adopts both NMOS and PMOS transistors to enhance negative conductance and LC-resonator to include the resonance frequency band.
4.3 Measurement
4.3.1 Measurement consideration
The PCB (printed circuit board) layout and practical FR4 PCB circuit conjunction with SMA connectors for this work are shown in Fig.4-9 and Fig4.10, respectively. The quadrature voltage controlled oscillator signal line width on the PCB must be designed 50Ω for impedance matching. The PCB also preserves additional space for DC blocking and bypassing capacitors. The chip is adhered to PCB and all I/O pads are bonded onto PCB via bond-wires. The die photograph is shown in Fig.4-11.
Fig.4-9 PCB layout of 8-bit voltage controlled oscillator
Fig.4-10 8-bit voltage controlled oscillator practical FR4 PCB measurement circuit
Fig.4-11 Die photo of 8-bits voltage controlled oscillator
4.3.2 Measurement V.S. Simulation Results
To measure the DC current consumption, we sweep the bias voltage of the VCO core current source from 0V to 1V, and measure the consumption current. Fig.4-12 shows the DC current consumption of 8-bits voltage controlled oscillator. The measurement result shows that the chip consumes about 6mA less than TT corner and 2mA less than SS corner. This result tells that chip doesn’t feet in the 6 corner cases (FF, FT, FS, TT, TS, SS), and the measurement results would be greatly violated the simulation results.
Fig.4-12 Current consumption, simulation V.S. Measurement
The quadrature outputs are connected to the spectrum analyzer to measure signal spectrum, output power, tuning range and phase noise. Setting resolution bandwidth to 100KHz, frequency span to 10MHz, the measured phase noise is -101dBc/Hz
@1MHz ( -51 -10log105=-101 dBc/Hz @1MHz).
The tuning range measurement is separated into two parts. First, setting control voltage to 0.9V and measure the VCO tuning range form bank codes 00000000 to 00011111. Fig.4-13 shows the bank code frequency tuning range measurement results V.S. simulation results. In Fig.4-13, the measured frequency tuning curve is down shifted by about 200MHz, since the measured DC current is below SS case. The 8-bits voltage controlled oscillator has linear frequency tuning behavior from 00000000 to 00001000, but breaks down at code 00010000 and 00100000. The nonlinear frequency tuning results from the large size PMOS varactor model isn’t correct and process variation.
Fig.4-13 Vctr=0.9V, bank code V.S. oscillation frequency
Second part, fix the control voltage to 1.8V, measure the frequency tuning curve of varactor bank code control voltage V.S. oscillation frequency. Fig.4-14 shows the SS corner each bank tuning curve simulation results. The tuning range is binary weighted. Fig.4-15 shows bank 0 to bank 4 tuning range measurement results. Bank 0 to Bank 3 has binary weighted relation. But Bank 4 didn’t double Bank 3 tuning range!
To examine this problem, we compare the Bank4 to Bank 7 tuning range simulation V.S. measurement results, shown in Fig.4-16 to Fig.4-19, respectively. In Fig.4-17 to Fig.4-19, the measured tuning curve didn’t follow the simulation curve anymore.
Fig.4-14 Bank tuning range simulation results
Fig.4-15 Bank tuning range measurement results
Fig.4-17 Vc5 measured tuning range
Fig.4-18 Vc6 measured tuning range
Fig.4-19 Vc7 measured tuning range
We then summary the simulation results in Tab.10.
Tab.10 Measurements summary
Parameter TT SS Meas.
Supply Voltage 1.8V 1.8V 1.8V
DC Current 15.5mA 12mA 9.95mA
Phase Noise @1MHz -108dBc/Hz -107dBc/Hz -101dBc/Hz
Linear Tuning Varactors 8 8 4
Center Frequency 5.24GHz 5.07GHz 4.645GHz
Tuning Range 4.94~5.54GHz 4.77~5.37GHz
4.61~4.68GHz (4 bits) Average Code Word
Tuning Range
4.67MHz 4.67MHz 4.38MHz
(4 bits)
4.3.3 Discussion
Although this chip is only partial work, some aspects should be noted:
z The process variation is very serious in this work. A DC current 2mA smaller than SS core simulation results makes circuit hardly to oscillate at stable frequency since the -gm value is due to DC current.
z The work shows using varactors to increase frequency resolution is a practical method, since small size varactor tuning is achieved.
z The large size PMOS varactor could be substituted by the MOS_VAR provided by TSMC, since the component is more reliable at high frequency.
since an On-OFF switching behavior is guaranteed. But the steady oscillation condition should be considered more careful.
4.4 Future Works
The frequency detector reach is still going on. Once a high efficient, accurate frequency detector has been done, this new all-digital frequency synthesizer architecture could be completed. A high speed, high resolution DAC is needed to increase system frequency resolution and settling time. The all-digital frequency synthesizer is designed on the purposes of increasing system integration and shortening frequency settling time without any off-chip comportments.
Chapter 5
Conclusion and Future Work
5.1 Conclusion
This thesis contents three design works. This first work is high integration multi-bands Σ∆ fraction-N frequency synthesizer in TSMC 0.18µm CMOS. The second work is 802.11a integer-N frequency synthesizer in TSMC 0.25µm CMOS.
The third is 8-bit AFC voltage controlled oscillator in TSMC 0.18µm CMOS. All these three circuits have been fabricated through CIC. These circuit design concepts, simulation results, measurement data have been discussed in detail.
5.1.1 High integration quad-bands frequency synthesizer
A novel frequency division technique to integrate multi-band frequency synthesizer circuit design has been discussed in this thesis. This technique reduces chip dimension without scarifying phase noise and frequency resolution performances.
The 802.11a/b/g and GSM/DCS1800 quad-bands frequency synthesizers are perfectly combined in single chip. A 12-bit Σ∆ modulator helps increasing frequency resolution to satisfy GSM/DCS1800 200KHz channel bandwidth specification. To further reduce chip area, a register is used to load all digital control bits and voltage controlled oscillator bank control bits. The chip dimension is only 1.61mm2, half the dimension of other compared dual-band frequency synthesizer designs [1][4].
5.1.2 802.11a integer-N frequency synthesizer
In 802.11a application, the integer-N frequency synthesizer architecture is most commonly used. Since the 802.11a channel bandwidth is 20MHz, much higher than other application, the reference can be chosen as high as 10MHz to fasten frequency settling time. In order to lower power consumption, only one dual modulus frequency divider (÷8/9) is used in the work. A pulse-swallow counter is designed to control the dual modulus frequency divider in a period of 32 reference clocks. Reference frequency is 10MHz. Synthesized frequency is from 5.18GHz to 5.34GHz, 20MHz frequency step. Using MATLAB to design loop filter is a practical approach. The MATLAB step and bode functions helps designer efficiently simulate frequency synthesizer close loop settling time and open loop phase margin. The MATLAB program only takes minutes to simulate frequency synthesizer, while ELDO transient analysis takes almost a week!
5.1.3 All-digital frequency synthesizer
We have proposed new all-digital frequency synthesizer architecture. According to the 802.11a frequency tolerance of ±20ppm, at least 14-bit frequency resolution digital frequency resolution can satisfy system specification. The 14-bits are separated in two parts: 8-bit for varactor bank coarse tuning, 6-bit for control voltage fine tuning.
Once the designing problem of high efficient frequency detector has been solved, the new frequency synthesizer will promote RF frequency synthesizer integration and frequency settling time. The 8-bit frequency resolution voltage controlled oscillator measurement has been completed. Through this thesis, the research of high frequency
resolution voltage controlled oscillator by using PMOS varactor banks has been proven.
5.2 Future Work
Some aspects need to be improved below:
1. In the quad-bands frequency synthesizer design, the power of quad-bands signals should be increased to above -10dBm for practical telecommunication system.
Common drain structure isn’t suitable for large output power design, since common drain amplifier is intrinsically a power loss structure. The quad-bands output buffer structure should be modified. Common source output buffer is preferred because it provides power gain rather power loss.
2. The high frequency dividers in quad-bands frequency synthesizer design should be modified to provide more balanced output waveform.
3. In the integer-N frequency synthesizer design, the high frequency divide-by-2 circuit is connected to a buffer. This buffer cause signal voltage swing degradation. This buffer should be removed to increase signal voltage swing.
4. The charge pump in this thesis is a current mismatching circuit. The mismatching current will results in reference spurious noise and distort signal spectrum. A new charge pump structure has been designed and will integrate to frequency synthesizer in future designs.
5. High efficient frequency detector research is going on to complete the new all-digital frequency synthesizer.
Reference
[1] Magoon, R.; Molnar, A.; Zachan, J.; Hatcher, G. and Rhee, W., “A Single-Chip Quad-Band (850/900/1800/1900 MHz) Direct Conversion GSM/GPRS RF Transceiver with Integrated VCOs and Fractional-N Synthesizer”, IEEE Journal of Solid-State Circuits, vol.37, pp.1710 - 1720, Dec. 12, 2002.
[2] Duvivier, E.; Puccio, G.; Cipriani, S.; Carpineto, L.; Cusinato, P.; Bisanti, B.;
Galant, F.; Chalet, F.; Coppola, F.; Cercelaru, S.; Vallespin, N.; Jiguet, J.-C.;
Sirna, G., “A fully integrated zero-IF transceiver for GSM-GPRS quad-band application”, IEEE Journal of Solid-State Circuits, vol.38, pp. 2249 - 225, Dec.
2003.
[3] Rogers, J.W.M., Cavin, M., Dai, F. and Rahn, D., “A △ Σ Fractional-N Frequency Synthesizer with Multi-Band PMOS VCOs for 2.4 and 5GHz WLAN Applications”, European Solid-State Circuits, pp. 651 - 654, Sept. 16-18, 2003.
[4] Wei-Zen Chen; Jia-Xian Chang; Ying-Jen Hong; Meng-Tzer Wong; Chien-Liang Kuo, “A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-/spl mu/m digital CMOS process”, IEEE Journal of Solid-State Circuits, vol.39, pp. 234 – 237, Jan. 2004.
[5] Rogers, J.W.M.; Dai, F.F.; Cavin, M.S.; Rahn, D.G., “A multiband /spl Delta//spl Sigma/ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC”, IEEE Journal of Solid-State Circuits, vol.40, pp. 678 – 689, March 2005.
[6] Zargari, M.; Terrovitis, M.; Jen, S.H.-M.; Kaczynski, B.J.; MeeLan Lee; Mack, M.P.; Mehta, S.S.; Mendis, S.; Onodera, K.; Samavati, H.; Si, W.W.; Singh, K.;
Tabatabaei, A.; Weber, D.; Su, D.K.; Wooley, B.A., “A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN”, IEEE Journal of Solid-State Circuits, vol.39, pp. 2239 – 2249, Dec. 2004.
[7] M. W. Hwang, J. T. Hwang, and G. H. Cho, “Design of high speed CMOS prescaler”, Proceedings of the Second IEEE Asia Pacific Conference, pp. 87-90, 28-30 Aug. 2000.
[8] Magoon, R. and Molnar, A., “RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation”, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.
23 – 26, Jun. 2-4, 2002.
[9] J. N.Wells, “Frequency Synthesizers,” U.S. Patent 4,609,881, Sep. 1986.
[10] B. Miller and R. Conley, “A multiple modulator fractional divider,” in Proc. 44th Annu. Frequency Control Symp., May 1990, pp. 559–568.
[11] T. A. Riley, M. Copeland, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May 1993.
[12] T. W. Rhee, B. Song, and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order △Σ modulator,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1453–1460, Oct. 2000.
[13] Hamid R. Rategh, Thomas H. Lee,” Multi-GHz Frequency Synthesizers &
dividsion”, Kluwer Academic Publishers, 2002.
[14] Gwong-Wai Cheng, “A 5.25GHz Fully Integrated CMOS Quadrature Voltage-Controlled Oscillator”, Thesis of Master’s degree, Institute of communication, NCTU, Taiwan, ROC, Jun 2002.
[15] Sander L.J. Gierkink, Salvatore Levantino, Robert C. Frye, Vito Boccuzzi, “A Low-Phase Noise 5GHz Quadrature CMOS VCO using Common-Mode Inductive Coupling”, ESSCIRC, 2002.
pp. 117 – 120, June 1999.
[17] Foroudi, N., Kwasniewski, T.A., “CMOS high-speed dual-modulus frequency divider for RF frequency synthesis”, IEEE Journal of Solid-State Circuits, pp.93 – 100, Vol. 30, Feb. 1995.
[18] Wennekers, P.,” Dual-modulus frequency dividers with minimum gate count”, Electronics Letters, pp.1198 – 1199, Vol. 30, July 1994.
[19] Mano, M., Digital Design: Second Edition, Prentice-Hall Inc., USA, 1991.
[20] Sulaiman, M.S. and Khan, N., “A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer,” IEEE International Conference on Semiconductor Electronics, pp. 77-81, December 2002.
[21] Han-il Lee; Je-Kwang Cho; Kun-Seok Lee; In-Chul Hwang; Tae-Won Ahn;
Kyung-Suc Nah; Byeong-Ha Park, “A Σ-∆ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications”, IEEE Journal of Solid-State Circuits, Vol.
Kyung-Suc Nah; Byeong-Ha Park, “A Σ-∆ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications”, IEEE Journal of Solid-State Circuits, Vol.