Chapter 2 Highly Integrated Quad-Bands Σ∆ Fractional-N
2.8 Conclusion and comparison
Since quad-bands frequency synthesizer has not yet been promoted, we take two dual-bands frequency synthesizers for comparison, as in Tab.7.
Tab.7 Multi-bands frequency synthesizer comparison
This Work 【3】【5】 【4】
Technology 0.18um CMOS 0.5um SiGe
BiCMOS 0.35um CMOS
Power supply 1.8V 2.75V 2V
Current Consumption 58mA 36mA 40mA
Supported Application
802.11a/b/g GSM/DCS
802.11a/b/g
Japan 2.4GHz 802.11a/b/g VCO Phase Noise -114dBc/Hz
@1MHz
-120dBc/Hz
@1MHz
-114dBc/Hz
@5MHz
Reference Frequency 16MHz 40MHz N/A NO. of Accumulator Bits 12 bits 6bits 10+6 bits
Die area 1.61mm2 3.22mm2 3.52 mm2
Multi-system is getting more and more attention recently. In this chapter, we have demonstrated using frequency division technique to design a multi-bands frequency synthesizer. This technique is also practical for single-band frequency synthesizer design. The chip dimension can be saved without scarifying frequency resolution and phase noise performance by designing oscillator at double or triple frequency. The register design also helps designer to save chip dimension when several chip control bits are needed.
Chapter 3
802.11a Integer-N Frequency Synthesizer
The most popular structures for RF frequency synthesizer are fractional-N frequency synthesizer and integer-N frequency synthesizer. Fractional-N structure can synthesize fractional frequency of reference frequency, thus its frequency resolution is much higher than integer-N structure does. Since fractional frequency can synthesized, the reference frequency of fraction-N frequency synthesizer can be choose higher than required frequency resolution to shorten frequency settling time. Unfortunately, fractional-N structure depends on accumulator carrier to control frequency division number. The carrier signal is periodic produced, causing spur noise close wanted frequency. To suppress the spur noise, a complicated modulator is required which makes fractional-N structure much complicated than integer-N structure. Although the integer-N frequency synthesizer can only synthesize integer multiple of reference frequency, the division number is constant in every reference period. The spur noise of integer-N structure is much minor than fractional-N structure. If frequency resolution is not the main factor of frequency synthesizer (ex: 20MHz for 802.11a/b/g WLANs system), integer-N structure is a good choice since the spectrum purity is much clear than fraction-N structure. The comparison of these two frequency synthesizer structures is listed in Tab.8.
Tab.8 Frequency synthesizer structures performances comparison
Parameter Fractional-N Integer-N
Frequency Resolution Fine Coarse
Settling Time Fast Middle
Spurious Noise Poor Good
Complexity High Low
Power Consumption Middle Low
3.1 Architecture [13]
In this chapter, we will demonstrate an 802.11a pulse-swallow integer-N frequency synthesizer design. Circuit block diagram is shown in Fig.3-1. The reference frequency is 10MHz. A pulse-swallow counter is designed to control the dual-modulus divider (8/9). Except the loop filter, every block is designed on chip.
Fig.3-1 802.11a pulse-swallow integer-N frequency synthesizer architecture
3.2 QVCO Design [14][15]
In this chapter we adopt the differentially and complementary cross coupled pairs to generate low phase noise, symmetric and quadrature signal outputs. The
architecture is shown in Fig.3-2. The use of NMOS and PMOS complementary cross coupled pairs offering better rise and fall time symmetry, which results in low up-conversion of 1/f noise and other low frequency noise sources. The complementary structure also provides higher transconductance than all NMOS pairs making circuits much easier to start-up.
P0
Fig.3-2 Quadrature voltage controlled oscillator architecture
3.3 High speed Frequency Divider [16]
In this design, we adopt DFF operation principle to achieve divide-by-2 circuit.
The block diagram is shown in Fig.3-3(a). The DFF2 could be replaced by a delay device used to store Q1 value and flip DFF1 value at next trigger edge. At high frequency, digital logic DFF won’t work precisely. Analog DFF must be designed to attain this high frequency divide-by-2 circuit design. The DFF is shown in Fig.3-3(b).
（a） （b）
Fig.3-3（a）Block diagram of divide-by-2 circuit （b）Analog structure of DFF
The cross signal lines in DFF circuit should be layout carefully. Parasitic capacitance and resistance may cause circuit malfunction. We should take these parasitic effect into consider when simulating circuit performance. Fig.3-4 is the transient simulation result of inputting 5.5GHz, 100mV amplitude sine waves to circuit. Circuit will function at 4-6GHz. Minimum acceptable signal amplitude is 80mV.
Fig.3-4 Transient simulation result of inputting 5.5GHz, 100mV amplitude sine waves
3.4 Dual-modulus frequency divider [17][18]
For low power application, the NOR gates of DMFD are combined to D-type flip-flops, circuit shown in Figure.3-5(a). The DMFD architecture is also shown in Figure.3-5(b). Because DMFD uses two D-type flip-flops, it consumes more power than a single divide-by-2 circuit. Since the 4 outputs of these two DFFs are connected to each other, the parasitic capacitance is pretty large. The layout of DMFD should be laid in a high density way. Using Calibre extraction tool, the parasitic capacitance for each DMFD output signal line is about 30fF. The parasitic capacitance should be taken into account at simulation step.
Vdd
3.5 Pulse-Swallow Counter [19][20]
The pulse-swallow counter is used to control dual-modulus division (8/9). It is composed of a loading and resetting counter and a channel detection circuit. The counter initially counts up from 0 to the input code (e.g. 6:00110), then counts down from 28 to input code makes a period of 32. The operation principle will be discussed in detail below.
3.5.1 Loading and Resetting Counter
The counter consists of 5 JKFFs with each J and K shorted together individually.
UD is a control signal that determines the counting mechanism. As UD=High, counter counts up. As UD=Low, counter counts down. The counter diagram is shown in Fig.3-6.
Initially, UD=High, counter counts up from 0. As A1~A5 equal to channel input codes, UD will change to Low, and counter counts down from 28 (by setting the 3rd to 5th JKFF to High). As A1~A5 equal to channel input codes again, UD will change to High, and counter counts up from 0. Because this counter needs two comparison states (examine whether A1~A5 equal to channel codes or not), one loading state and one resetting state, the loading number is chosen to be 28, not 32! The complete counter structure is shown in Fig.3-7.
Fig.3-6 Loading and resetting counter
Fig.3-7 Timing diagram of loading and resetting counter
3.5.2 Pulse-Swallow Counter
The complete pulse-swallow counter is shown in Fig.3-8. The 5 counter output bits (A1~A5) are compared to channel input codes (Ch1~Ch5). RL is connected to the JKFF with J, K shorted together. Only when A1~A5 equal Ch1~Ch5, RL will be High.
Since RL=High, JKFF will flip its value and change UD state. Notice that UD has a duty circle that is programmed by Ch1~Ch5. For Ch1~Ch5=00100, UD will keep at high for 6 CLK pulses. IF Ch1~Ch5=00110, UD will keep at high for 8 CLK pulses.
Fig.3-8 Complete pulse-swallow counter architecture
Fig.3-9 Timing diagram of pulse-swallow counter
3.6 PFD and Charge Pump design
The phase frequency detector (PFD) type can be separated to analog and digital.
For input signal is at several hundreds MHz order, analog PFD is preferred. In the RF frequency synthesizer, the signal frequency will be scaled down by prescalar and digital frequency divider. Since the divider output frequency is scaled down to only tens MHz, digital PFD is most used in RF frequency synthesizer. The digital PFD is
shown in Fig.3-9. There is one serious problem with this tri-state PFD: dead zone, as depicted in Fig.3-11. This problem results from charging time of charge pump. When reference signal is almost in-phase with divider output signal, the pulse duration produced by PFD isn’t long enough to turn on charge pump, causing this small phase mismatch undetectable. To solve this problem, a delay circuit is induced before DFF reset pin to increase PFD pulse duration. The delay time should be long enough to turn on charge pump.
Fig.3-10 Tri-state phase frequency detector (PFD)
Fig.3-11 Dead zone problem of PFD
The purpose of charge pump is to transform the phase mismatch detected by PFD to a charging current. To achieve a high voltage output range at the charge pump, the transistor size of the current mirror transistors (M1-M11) must be chosen carefully.
Also an accurate layout of the charge pump is important to improve the matching of the positive and negative current to avoid mismatch currents. Mismatch currents
emission in RF transmitter. We implement two additional transistors (M12, M14) to guarantee in case of switching the transistors M13 and M15, their sources are already precharged. Above reduces current peaks during the switching time and suppressing the spurious tones, too. The charge pump structure is shown in Fig.3-12.
Fig.3-12 Charge pump architecture
3.7 Loop filter design
The loop filter is very important in frequency synthesizer design. We expect the loop bandwidth can be high enough for fast locking behavior. Additionally, loop bandwidth should be low to suppress spurious noise results from PFD and charge pump switching. Since tradeoff exists in the loop filter design, and loop bandwidth should be chosen carefully. For system stability consideration, the phase margin should be designed about 50 degrees.
Fig.3-13 4th order Loop filter architecture
Consider all the requirements above; the 4th order loop filter architecture is adopted in this chapter. Fig.3-13 shows the 4th order loop filter architecture. The loop filter transfer function is:
( )
1 2Locations of poles, zeros and loop bandwidth determines frequency synthesizer settling time, spurious noise and phase margin. The frequency difference of ωz to K should equal to the frequency difference of ωp1 to K for largest phase margin performance. According to theory and experiment, the poles, zeros, loop bandwidth and reference frequency allocation diagram is depicted in Fig.3-14.
After the locations of poles, zeros and loop bandwidth are determined; we derived all the resistance and capacitance values below:
1 1
, should be kept large to bypass spurious noise!
p
K =9.57 A/rad, K =2429.5Mrad/V, =62.83rad/s, N=520 : : :K: =640:64:16:4:1
Compute the resistances and capacitance values according to the above expression and Fig.3-14. Then we apply MATLAB step function and bode plot function to simulate frequency synthesizer close loop transient settling time and open loop phase margin. The MATLAB simulation results are shown in Fig.3-15. Because the resistances and capacitances are quite large comparing to on-chip resistances and capacitances, the loop filter is designed off-chip by microwave devices.
(a)
(b)
Fig.3-15 MALAB simulation results (a) transient analysis (b) bode plot
3.8 Synthesizer simulation results
CH5~CH1=00010, synthesizer locks at 5.18GHz in 40µs. Fig.3-17 shows 5.18GHz spectrum simulation results. Output power is -20.7dBm. The frequency synthesizer performances are summarized in Tab.9.
Ch5~Ch1=00000 Frequency=5.14GHz Settling time=40us
Ch5~Ch1=00010 Frequency=5.18GHz Settling time=40us
Fig.3-16 Frequency synthesizer transient simulation results
Tab.9 802.11a integer-N frequency synthesizer performances summary Parameter Simulation Results Technology TSMC 0.25µm CMOS
Application 802.11a Synthesizer
Architecture Integer-N pulse-swallow Channel Control Bit 5 bits
Phase Noise -106 dBc/Hz @1MHz Reference Frequency 10 MHz
Settling Time 40µs Output Power -20.7 dBm Power Consumption 20.44 mW
3.9 Measurement Results
3.9.1 Measurement Consideration
The PCB (printed circuit board) layout and practical FR4 PCB circuit conjunction with SMA connectors for this work are shown in Fig.3-18 and Fig.3-19, respectively. The voltage controlled oscillator signal line width on the PCB must be designed 50Ω for impedance matching. The PCB also preserves additional space for DC blocking and bypassing capacitors. The chip is adhered to PCB and all I/O pads are bonded onto PCB via bond-wires. The die photograph is shown in Fig.3-20.
Fig.3-18 PCB layout of 5GHz frequency synthesizer
Fig.3-19 5GHz frequency synthesizer practical FR4 PCB measurement circuit
Fig.3-20 Die photo of 5GHz frequency synthesizer
3.9.2 Measurement V.S. Simulation Results
We perform open loop measurement first. The measured DC currents are 13mA for VCO and output buffer, 7mA for frequency divider. Measured DC current fits the simulation FF corner (11.6mA for VCO and buffer, 7mA for divider). Apply spectrum analyzer to measure voltage controlled oscillator output signal power, phase noise and tuning range. The measured output signal power is -26dBm, while the simulation is -20dBm. The measurement result is shown in Fig.3-21. Measured frequency tuning range is 4.6-5.25 GHz, while simulation result of FF corner is 5.23-5.88 GHz. The measured frequency is about 630MHz lower than simulation. The measure result is shown in Fig.3-22. Measured phase noise is -104.33dBc/Hz @1MHz (-54.33 -10log105=-104.33 dBc/Hz @1MHz), while the simulation result is -105dBc/Hz
@1MHz. The phase noise performance is quite close to simulation results and shown in Fig.3-23.
Fig.3-22 Tuning range measurement
Fig.3-23 Phase noise measurement
The frequency synthesizer didn’t lock to the wanted frequency. The problem may results from 2 main reasons. First, the VCO signal swings are not sufficient to push frequency dividers. The measured signal is 6dBm less than simulation. In this design, low power consumption is our design guide. Each circuit is designed to consume
signals were not designed to have large power output. The simulated VCO signal swing is 250mV. The fist divide-by-2 circuit will function if the input signal swing is large than 200mV. 6dB power loss means voltage is degrade by a factor of 2, which means the measured signal swing is only 125mV. Since VCO output signal swing is only 125mV, the divider is unable to function. Second, at the design step of high frequency divide-by-2 circuit, the loading and parasitic effect is very serious. To deal with this problem, we utilized a common drain buffer amplifier. Although the loading and parasitic problems have been solved, the divider output voltage swing is even smaller than VCO output signals. The buffer amplifier consumes DC power and voltage swing, makes system harder to design. To examine the parasitic problem, we use Caliber extraction tools to extract the parasitic capacitances and resistances. The parasitic capacitance of the first divide-bu-2 circuit is 20fF. This parasitic capacitance should be taken into account in the simulation step. By careful consideration, the common buffer amplifier should be eliminated to increase system stability and functionality. This work will be redesigned with no divider buffer amplifier and higher VCO output power.
Chapter 4
An 8-bit AFC Voltage Controlled Oscillator
In this chapter, a high frequency resolution voltage controlled oscillator (VCO) design will be discussed. PMOS varactors are used to achieve 8-bits frequency resolution. This circuit is a step stone to an all-digital complete integration frequency synthesizer design. By designing a high frequency resolution VCO and using a digital coding method to control VCO varactor banks and VCO control voltage, the dream of whole-new all-digital frequency synthesizer architecture will come true. In this new structure, traditional loop filter, used to be implemented off-chip, will be omitted. This new structure will help to increase RF system integration and speed up frequency settling time by several times.
4.1 Proceeding on All-Digital Frequency Synthesizer
4.1.1 Background
Traditionally, the loop filter of frequency synthesizer is an off-chip circuit due to large capacitances and resistances. For SOC application, this will definitely cause problem. In order to integrate loop filter into chip, we propose an all-digital frequency synthesizer architecture.
In the voltage controlled oscillator, each varactor bank code tuning range covers neighboring varactor bank codes by 50%. Therefore, overall tuning range of VCO is:
( )
1
2
n 1 *0.5BW = +⎡⎣ − ⎤⎦ , where ƒ is average tuning range of each varactor bank f code. 802.11a application specifies a usable band from 5.15GHz to 5.35GHz.
Consider process variation, a 600MHz VCO tuning range is sufficient. Substitute BW=600MHz into above expression, the average varactor tuning range ƒ will be 4.67MHz.
The center frequency tolerance in 802.11a specification is ±20ppm. If center frequency is 5.25GHz, the allowable frequency shifting is ±105KHz. In an 8-bits resolution VCO, average varactor bank code tuning range is 4.67MHz. If we design the control voltage of VCO to have more than 6-bits resolution, the 802.11a specification can be met. We conclude that a 14-bits all-digital frequency synthesizer is practical for 802.11a application. More than that, if we adopt dichotomy logic to design frequency synthesizer comparison mechanism, after 14 decisions system will lock at wanted frequency. Take reference frequency = 10MHz for example, every 0.1µs can determine a bit. Total frequency settling time will be only 14*0.1=1.4µs.
Compare to traditional frequency synthesizer settling time of 40µs, this new structure shows a great potential.
4.1.2 Proposed Architecture [21]
The 14 bits should be divided into 2 parts, 8 bits for VCO bank coarse tuning, another 6 bits is left for VCO control voltage fine tuning. Because the VCO is the most important component in frequency synthesizer, it must be proven before been integrated into all-digital frequency synthesizer. The proposed new frequency
the frequency detector that can discriminate which of reference signal or divider signal has higher frequency in a few signal pulses. At first, VCO control voltage is connected to Vref. After first eight comparisons, the 8 VCO varactor banks will be set.
Then VCO control voltage is switched to DAC output signal to perform frequency fine tuning. In six more frequency comparisons, the frequency synthesizer will lock at wanted frequency.
Fig.4-1 Proposed new all-digital frequency synthesizer architecture
4.1.3 Frequency Detector Design [22][23]
The analog frequency detector is shown in Fig.4-2. It is composed of two quadrature mixers and two low pass filters. The circuit principle is as following:
1 2 a 1 2
By observing Va and Vb, we can tell which of the incoming signal has higher frequency.
Fig.4-2 Analog frequency detector
Next, we try to form a digital type frequency detector. The two quadrature mixers is replaced by two DFFs. The four ANDs will generates the discrimination signals AB’C, A’BC’, AB’C’ and A’BC. The discrimination signals conclude all possible combinations about whether Div leads or Ref leads. After JKFF, frequency detector outputs the discrimination results. “H” states Div is slower than Ref, “L” states Div is faster than Ref. “S” means that these two signals have same frequency.
Fig.4-3 Digital frequency detector
Fig.4-3 is further modified to a balanced structure, shown in Fig.4-4, to increase frequency discrimination range.
D
Fig.4-4 Modified balance digital frequency detector
Although this frequency detector can discriminate frequency precisely, the discrimination speed is too slow if the incoming signals don’t differ too much in frequency. This problem troubles us a lot, since the all-digital frequency synthesizer depend on this circuit to shorten frequency settling time. A phase synchronizer may be needed to solve this problem. With the help of phase synchronizer, we can discriminate frequency in only one reference clock. Fig.4-5 illustrates the function of a phase equalizer in this frequency detector design.
Ref
Fig.4-5 Function of phase synchronizer to aid frequency detector design
4.2 8 bits VCO Architecture [24][25][26]
Since the average tuning range of each varactor bank code is only 4.67MHz, the varactor model provided by TSMC is not suitable in this design. In this design, we implement these varactors by PMOS with Drain, Source and Bulk are shorted together.
The PMOS varactor layout is shown in Fig.4-6[27]. The tuning characteristic of PMOS varactor is shown in Fig.4-7.
Fig.4-6 PMOS varactor layout
VCO is the core circuit in the frequency synthesizer. In most RF design, we use LC-tank oscillator instead of ring oscillator for better phase noise. For image cancellation, we hope VCO can provide quadrature phase output signal. There are three ways to generate quadrature signals: divide-by-two circuit [28]; RC-polyphase network [29]; and two VCOs cross connect with each other [30]. Using divide-by-two circuit needs to design a VCO operate at the double frequency of original frequency. A VCO with RC-polyphase network consumes less power than others, but RC-polyphase is a signal power hungry circuit. For accurate quadrature phase signal and large output signal power reasons, we design two VCOs differentially connect to each other to generate quadrature signal. The whole schematic of the 8-bits frequency resolution quadrature VCO is shown in Fig.4-8. The architecture of cross-coupled pairs adopts both NMOS and PMOS transistors to enhance negative conductance and
VCO is the core circuit in the frequency synthesizer. In most RF design, we use LC-tank oscillator instead of ring oscillator for better phase noise. For image cancellation, we hope VCO can provide quadrature phase output signal. There are three ways to generate quadrature signals: divide-by-two circuit [28]; RC-polyphase network [29]; and two VCOs cross connect with each other [30]. Using divide-by-two circuit needs to design a VCO operate at the double frequency of original frequency. A VCO with RC-polyphase network consumes less power than others, but RC-polyphase is a signal power hungry circuit. For accurate quadrature phase signal and large output signal power reasons, we design two VCOs differentially connect to each other to generate quadrature signal. The whole schematic of the 8-bits frequency resolution quadrature VCO is shown in Fig.4-8. The architecture of cross-coupled pairs adopts both NMOS and PMOS transistors to enhance negative conductance and