Chapter 1 Introduction
1.2 Thesis organization
This thesis discusses a high-integration multi-band Σ∆ fractional-N frequency synthesizer fabricated by TSMC 0.18µm CMOS process and an 802.11a integer-N frequency synthesizer. Finally, propose a new all-digital frequency synthesizer architecture that would not require loop filter.
Chapter 2 introduces a 0.18µm CMOS, high integration frequency synthesizer that use only one voltage controlled oscillator to combined 802.11a/b/g and GSM/DCS1800 frequency synthesizer in single chip.
Chapter 3 introduces a 0.25µm CMOS, 802.11a integer-N frequency synthesizer architecture, building blocks and simulation results.
Chapter 4 introduces a new topology of frequency synthesizer that can omit off-chip loop filter and speeds up locking time. The 8-bit voltage controlled oscillator has been fabricated in TSMC 0.18µm CMOS technology.
Finally, chapter 5 gives the conclusions of the above three circuit designs and future work.
Chapter 2
Highly Integrated Quad-Bands Σ∆
Fractional-N Frequency Synthesizer
System integration is an important trend in modern electronic communication products [1][2][3][4][5][6]. The most famous product is the GSM mobile phone integrated with GPRS function which enables mobile phone the internet function.
This is indeed a great idea to make our lives better. Another important integration is the wireless local area network (WLAN) integration. Under this trend, the relationship between notebook and mobile phone gets closer, which means that the mobile system would be eventually integrated with the WLAN system. However, these two main systems differ in too many aspects, such as channel bandwidth, central frequency, data rates, etc.; this integration doesn’t come to the market. In this chapter, we will discuss and design an 802.11a/b/g, GSM, DCS1800 quad-bands frequency synthesizer integration using frequency division and fractional-N Σ∆ modulation methods. The chip is fabricated in TSMC 0.18µm CMOS process.
2.1 Background
Multi-bands frequency synthesizer has attracted a lot of attention recently. There are two methods to design this multi-bands circuit: multi-bands VCO, frequency doubling or diving. We will discuss both below.
1. A Single-Chip Quad-Band (850/900/1800/1900MHz) Direct Conversion GSM/GPRS RF Transceiver with Integrated VCOs and Fractional-N Synthesizer [1]
Circuit block diagram is shown in Fig.2-1.The voltage controlled oscillator is designed to oscillate between 1245MHz to 1650MHz. The voltage controlled oscillator output signals first pass a buffer amplifier. Then signals will proceed by divide-by-3 and multiply-by-2 circuit to generate triple-bands signals. Circuit performances are summarized in Tab.1. The multi-bands signals generation method is very similar to this thesis.
PFD CP
Fig.2-1 Quad-Bands (850/900/1800/1900MHz) frequency synthesizer block diagram
Tab.1 Quad-bands (850/900/1800/1900MHz) frequency synthesizer performances summary
Parameter Performance
Tuning Range 1250~1650MHz
Frequency Resolution 3Hz
Locking Time（<100ppm） 175µs
Phase Noise @100KHz -106dBc/Hz Phase Noise @400KHz -124dBc/Hz
Phase Noise @3MHz -141dBc/Hz
Biasing Currrent 28mA
2. A △Σ Fractional-N Frequency Synthesizer with Multi-Band PMOS VCOs for 2.4 and 5GHz WLAN Applications [3]
Circuit block diagram is shown in Fig.2-2. Design two voltage controlled oscillator (2.4GHz, 5GHz). By switching these two oscillators, we can attain dual-bands frequency synthesizer design. Because two oscillators are required, the chip dimension is much larger than the former, but the dual-bands signals have greater output power due to directly output from oscillator. The circuit performances are summarized in Tab.2.
Fig.2-2 Dual-bands (2.4GHz, 5GHz) frequency synthesizer block diagram
Tab.2 Dual-bands (2.4GHz, 5GHz) frequency synthesizer performances summary
Parameter Performance High Frequency Tuning Range 4.93~5.35GHz
Middle Frequency Tuning Range 4.47~4.91GHz Low Frequency Tuning Range 3.52~3.87GHz
Phase Noise -120dBc/Hz @1MHz
In Band Noise -93dBC/Hz
Loop Corner Frequency 150KHz
Reference Frequency 40MHz
Channel Resolution 1MHz
Reference Spur Noise -56dBc
2.2 System Integration
2.2.1 System Specifications
In this chapter, we try to integrate 802.11a/b/g and GSM/CS1800 frequency synthesizer. Three system specifications that frequency synthesizer concerned about are frequency band, channel bandwidth and phase noise. They are listed in Tab.3 (a).
Tab.3 (a) Each System specifications Frequency Band
802.11b/g 2400~2483 MHz 10 MHz -110@1MHz
DCS1800 1710~1785 MHz 1805~1880 MHz 200 KHz -116@600KHz GSM900 890~915 MHz 935~960 MHz 200 KHz -121@600KHz
In order to generate quad-bands signals, we adopt frequency division method.
The 802.11a signal is outputted directly from the voltage controlled oscillator.
802.11b/g signal is outputted from a divide-by-2 circuit. DCS1800 signal is outputted from a 50% divide-by-3 circuit. GSM signal is outputted from a 50% divide-by-6 circuit. The specifications of each application after integration are summarized in Tab.3 (b).
Tab.3 (b) System specifications after integrating to 5GHz Frequency Band
DCS1800 5.130~5.355 GHz 5.415~5.640 GHz 600 KHz -116@1.8MHz GSM900 5.340~5.490 GHz 5.610~5.760 GHz 1200 KHz -121@3.6MHz
2.2.2 Phase Noise Considerations
In a perfect frequency divider, signal phase noise after division will be improved as described in Fig.2-3. Based on the frequency division theory, signal skirt would be narrower after division. If the divider is well-designed, signal phase noise will get about 6dB better from a divide-by-2 circuit and 9dB better from a divide-by-3 circuit.
In this chapter, the voltage controlled oscillator phase noise simulation results is shown in Fig.2-4. By the perfect divider theorem and the phase noise simulation result, we can expect the quad-bands signal phase noise performance would meet the system specification, summarized in Tab.4. From the above comparison, we can conclude that designing oscillator at higher frequency then scaled the frequency down is a good choice. The chip dimension could be smaller because the inductance is smaller than lower frequency. Besides that, circuit phase noise performance will also satisfy the system specification.
Fig.2-3 Signal spectrum description after division 1MHz
2MHz
1MHz 6dB
Fig.2-4 Voltage controlled oscillator phase noise simulation results
Tab.4 Phase noise comparison, system specifications vs. simulation Application System Spec. Simulation
802.11a -110 dBc/Hz @1MHz -114 dBc/Hz @1MHz 802.11b/g -110 dBc/Hz @1MHz -121 dBc/Hz @1MHz DCS1800 -116 dBc/Hz
@600KHz
-120 dBc/Hz
@600KHz
GSM -121 dBc/Hz
@600KHz
-127 dBc/Hz
@600KHz
2.2.3 Frequency Considerations and Channel Code Allocations
From Tab.3 (b), the tuning range of voltage controlled oscillator (VCO) must cover from 4.8GHz to 5.8GHz. The tuning range of voltage controlled oscillator is about 20%, which will make system unstable because the oscillator is too sensitive. In
this thesis, we separate this 1GHz tuning range into 6 sections by designing 3 varactors in the voltage controlled oscillator. Tab.5 shows the frequency bands of each application after integrating to 5GHz vs. VCO varactor bank codes allocation. Since these varactors determine the oscillation frequency, they are the most important factor about the success of this quad-bands frequency synthesizer. The tuning range of VCO is shown in Fig.2-5.
Tab.5 System frequency bands after integration vs. varactor bank
Application Frequency Bands After Integration Varactor Bank Code
802.11a 5.15~5.35 GHz 3
802.11b/g 4.80~4.97 GHz 2
DCS1800 TX：5.130~5.355 GHz RX：5.415~5.640 GHz 3、5 GSM900 TX：5.340~5.490 GHz RX：5.610~5.760 GHz 4、6
Fig.2-5 VCO each bank codes tuning range simulation results
2.3 Quad-Bands Frequency Synthesizer Architecture
Consider that 802.11a/b/g channel bandwidth (20MHz) is much larger than GSM/DCS1800 (200 KHz) system; we decided to separate these two systems into two paths. Circuit block diagram is shown in Fig.2-6. By design two Σ∆ modulators and use a switch, we can implement a quad-bands frequency synthesizer. But a problem exists in this architecture: because the 1.8GHz divider is connected to a 1.8GHz output buffer amplifier and a divide-by-2 circuit, the loading effect may cause the 50% divide-by-3 circuit malfunction!
Fig.2-6 Quad-bands frequency synthesizer architecture
In order to make system more stable, we must minimize the loading effects of the 50% divide-by-3 circuit. We modified the quad-bands frequency synthesizer architecture as in Fig.2-7. Reader may find out that the 50% divide-by-3 circuit doesn’t connect to divide-by-2 circuit anymore, thus the loading effect is lessened and system becomes more stable. Although 802.11a/b/g channel bandwidth differs from GSM/DCS1800 a lot, we can use the fine resolution Σ∆ modulator of GSM/DCS1800
to replace the coarse resolution of 802.11a/b/g Σ∆ modulator. The architecture of Fig.2-7 is single path architecture, so that the integration of system is improved. To attain fine resolution of GSM/DCS1800, the Σ∆ modulator is composed of 12-bit accumulator. The reference frequency is chosen to be 16MHz under the tradeoff of spur noise suppression and fast settling time.
Fig.2-7 Modified quad-bands frequency synthesizer architecture
2.4 50% Divide by 3 Circuit [1][8]
Traditional frequency divider is based on positive edge trigger or negative edge trigger architecture, thus output signal has even period of input signal. To design a 50% divide-by-odd circuit, the trigger structure should be modified. Based on this idea, we should design a new DFF that has a new control signal: θ, to change the DFF trigger mechanism. When θ=H, circuit is positive edge trigger. When θ=L, circuit is negative edge trigger. The structure of this new DFF is shown in Fig.2-8.
Fig.2-8 Trigger mechanism changeable DFF structure
By cascading N-stages DFF, we can design 50% divide-by-N circuit, no matter N is odd or even. In this thesis, we cascade 3-stage DFF, and let neighboring stage differ by 60 degrees. Timing diagram is shown in Fig.2-9.
Fig.2-9 Timing diagram of 50% divide-by-3 circuit
Observing the control signals of each DFF, we summary the control signals below:
D1/θ1 D2/θ2 D3/θ3 Q3’/Q2 Q1/Q3’ Q2/Q1’
After we derived out each DFF control signals, the complete 50% divide-by-3 circuit is shown in Fig.2-10.
Fig.2-10 Complete divide-by-3 circuit structure
Fig.2-11 shows the simulation result of inputting 5.8GHz, amplitude 100mV sine wave to divide-by-3 circuit. The operation frequency of this circuit is 5-6GHz;
minimum acceptable signal amplitude is 80mV which is quite satisfaction to this quad-bands frequency synthesizer design.
Fig.2-11 Input 5.8GHz, 100mV amplitude signal simulation result
2.5 3
rdΣ∆ Modulator [9][10][11][12]
Because the channel bandwidth of GSM/DCS1800 is quite narrow, we use fractional-N structure in this quad-bands frequency synthesizer for faster settling without scarifying frequency resolution. Fractional-N architecture is based on accumulator carrier to control fraction division. Unfortunately, the carrier signal is a periodic signal which will cause intolerant spur noise close to signal wanted. To suppress the spur noise, we use a Σ∆ modulator to modulate the carrier signal.
The mono-type of Σ∆ modulator is shown in Fig.2-12. The Σ∆ modulator is composed of an integrator and a differentiator. After the differentiator, the quantization noise has been suppressed. The practical 1st Σ∆ modulator is shown in Fig.2-13. It explains that after a Σ∆ modulator, the quantization noise will be shaped by (1-Z-1). Some modification has been made to simplify the 1st Σ∆ modulator.
Fig.2-14 shows a modified 1st Σ∆ modulator structure. In Fig.2-14, 1st Σ∆ modulator is accomplished by an accumulator.
Fig.2-12 Σ∆ modulator Mono-type
1
Fig.2-13 Basic type of Σ∆ modulator
1
Fig.2-14 Modified 1st Σ∆ modulator
In order to transform more quantization noise to high frequency, we decide to use 3rd Σ∆ modulator. The 3rd Σ∆ modulator structure is shown in Fig.2-15. The output signal is:N Z
[ ] . [ ] (1 =
f Z+ −
z−1 3) ×
q Za[ ]
, which means that quantization noise, quantization noise, qa[Z], has been shaped to q Ze[ ] (1 = −
z−1 3) ×
q Za[ ]
. The noise transfer function therefore is:( )
Assume power spectral density of quantization noise is
( ) 12 1
output phase mismatch power spectra density would be:( ) ( )
When close to center frequency, the phase mismatch power spectra density is:
( ) ( )
The spectrum is shown in Fig.2-16, which shows that quantization noise has been efficiently suppressed.
（a）
f Sθe
k
（b）
Fig.2-16（a）Noise shaping of 3rd Σ∆ modulator （b）Suppression of 3rd Σ∆ modulator to in-band quantization noise
In this thesis, we adopt MASH-1-1-1 3rd Σ∆ modulator. The integrators of Fig.2-15 are replaced by 1st Σ∆ modulator to make system more stable. The complete structure is shown in Fig.2-17. Practical 3rd Σ∆ modulator structure is also shown in Fig.2-18, which uses accumulators to replace integrators.
1
Z-1
12 bits 12 bits 12 bits
Fig.2-18 Practical 3rd Σ∆ modulator architecture
The 3rd Σ∆ modulator architecture is shown in Fig.2-14. To attain the 200 KHz frequency resolution of GSM/DCS1800 system, the accumulator is based on 12-bit.
Since the reference frequency is 16MHz, the frequency resolution of each system is:
Application Frequency Resolution 802.11a 16M÷212 = 3.9 KHz
802.11b/g 16M÷211 = 7.8KHz DCS1800 16M÷212 *3= 11.7 KHz
GSM 16M÷212*6 = 23.4 KHz
The frequency resolution could be further increases by increasing the accumulator bits.
Since the accumulator is a cascaded structure, signal delay is very critical in this design.
2.6 Whole System Simulation Results
Use ELDO simulation tool to simulate circuit close-loop behavior. The 5.18GHz locking curve of VCO control voltage is shown in Fig.2-19. System enters locking state in 15µs, and stable locking in 30µs. Buffer output signal is shown in Fig.2-20.
Signal swing is 520mV. Then apply FFT function to Fig.2-20, result shown in Fig.2-21. Fig.2-21 shows that circuit is locked at 5.18GHz and output power is -12.4dBm.
Fig.2-19 Transient curve of VCO control voltage
Fig.2-20 Buffer output signal transient analysis
Fig.2-21 5.18GHz FFT simulation result
2.6.2 2.401GHz Simulation Results
The 2.401GHz locking curve of VCO control voltage is shown in Fig.2-22.
System enters locking state in 15µs, and stable locking in 30µs. Buffer output signal is
shown in Fig.2-23. Signal swing is 250mV. Then apply FFT function to Fig.2-23, result shown in Fig.2-24. Fig.2-24 shows that circuit is locked at 2.401GHz and output power is -21.5dBm.
30us
Fig.2-22 Transient curve of VCO control voltage
250mV
Fig.2-24 2.401GHz FFT simulation result
2.6.3 1.726GHz Simulation Results
The 1.726GHz locking curve of control voltage of VCO is shown in Fig.2-25.
System enters locking state in 15µs, and stable locking in 30µs. Buffer output signal is shown in Fig.2-26. Signal swing is 260mV. Then apply FFT function to Fig.2-26, result shown in Fig.2-27. Fig.2-27 shows that circuit is locked at 1.726GHz and output power is -17.2dBm.
Fig.2-25 Transient curve of VCO control voltage
260mV
Fig.2-26 Buffer output signal transient analysis
Fig.2-27 1.726GHz FFT simulation result
2.6.4 900.2MHz Simulation Results
The 900.2MHz locking curve of control voltage of VCO is shown in Fig.2-28.
System enters locking state in 15µs, and stable locking in 30µs. Buffer output signal is shown in Fig.2-29. Signal swing is 150mV. Then apply FFT function to Fig.2-29, result shown in Fig.2-30. Fig.2-30 shows that circuit is locked at 900.2MHz and output power is -22.1dBm.
Fig.2-28 Transient curve of VCO control voltage
Fig.2-29 Buffer output signal transient analysis
Fig.2-30 900.2MHz FFT simulation result
2.6.5 Simulation Results Summary
Tab.6 Highly integrated quad-bands frequency synthesizer performance summary
Parameter Performance Technology 0.18 um CMOS
Supported Application 802.11a/b/g、GSM/DCS1800 Power Supply 1.8 V
-114.26 dBc/Hz @1.0MHz -119.98 dBc/Hz @1.8MHz -121.05 dBc/Hz @2.0MHz VCO Phase Noise (TT)
-126.48 dBc/Hz @3.6MHz VCO Bank Control Bits 3 bits
No. of Accumulator Bits 12 bits Reference Frequency 16 MHz
Die Area 1.61 mm2
2.7 Chip Layout
Many frequency synthesizer designers suffer from large chip dimension because the Σ∆ modulator have lots of control signals that need to be input outside from the chip. Try to allocate a pad to each control bit may cause the chip size becomes extremely large. The troubled designer could consider designing a register for all digital control bits. The register is composed of a series of cascading DFFs, architecture shown in Fig.2-31. The Data is controlled by a switch, while Bot is controlled by a botton.
D Q D Q D Q D Q D Q
Data Bot
B0 B1 B2 B10 B11
Fig.2-31 Register architecture
The quad-bands frequency synthesizer chip layout is shown in Fig2-32. The pad number has been reduced because two registers were used to load VCO varactor control bits and Σ∆ modulator control bits. Chip dimension is 1.45mm*1.114mm.
VCO
1.8GHz Digital
2.4GHz 900MHz
2.8 Conclusion and Comparison
Since quad-bands frequency synthesizer has not yet been promoted, we take two dual-bands frequency synthesizers for comparison, as in Tab.7.
Tab.7 Multi-bands frequency synthesizer comparison
This Work 【3】【5】 【4】
Technology 0.18um CMOS 0.5um SiGe
BiCMOS 0.35um CMOS
Power supply 1.8V 2.75V 2V
Current Consumption 58mA 36mA 40mA
Supported Application
802.11a/b/g GSM/DCS
802.11a/b/g
Japan 2.4GHz 802.11a/b/g VCO Phase Noise -114dBc/Hz
@1MHz
-120dBc/Hz
@1MHz
-114dBc/Hz
@5MHz
Reference Frequency 16MHz 40MHz N/A NO. of Accumulator Bits 12 bits 6bits 10+6 bits
Die area 1.61mm2 3.22mm2 3.52 mm2
Multi-system is getting more and more attention recently. In this chapter, we have demonstrated using frequency division technique to design a multi-bands frequency synthesizer. This technique is also practical for single-band frequency synthesizer design. The chip dimension can be saved without scarifying frequency resolution and phase noise performance by designing oscillator at double or triple frequency. The register design also helps designer to save chip dimension when several chip control bits are needed.
Chapter 3
802.11a Integer-N Frequency Synthesizer
The most popular structures for RF frequency synthesizer are fractional-N frequency synthesizer and integer-N frequency synthesizer. Fractional-N structure can synthesize fractional frequency of reference frequency, thus its frequency resolution is much higher than integer-N structure does. Since fractional frequency can synthesized, the reference frequency of fraction-N frequency synthesizer can be choose higher than required frequency resolution to shorten frequency settling time. Unfortunately, fractional-N structure depends on accumulator carrier to control frequency division number. The carrier signal is periodic produced, causing spur noise close wanted frequency. To suppress the spur noise, a complicated modulator is required which makes fractional-N structure much complicated than integer-N structure. Although the integer-N frequency synthesizer can only synthesize integer multiple of reference frequency, the division number is constant in every reference period. The spur noise of integer-N structure is much minor than fractional-N structure. If frequency resolution is not the main factor of frequency synthesizer (ex: 20MHz for 802.11a/b/g WLANs system), integer-N structure is a good choice since the spectrum purity is much clear than fraction-N structure. The comparison of these two frequency synthesizer structures is listed in Tab.8.
Tab.8 Frequency synthesizer structures performances comparison
Parameter Fractional-N Integer-N
Frequency Resolution Fine Coarse
Settling Time Fast Middle
Spurious Noise Poor Good
Complexity High Low
Power Consumption Middle Low
3.1 Architecture [13]
In this chapter, we will demonstrate an 802.11a pulse-swallow integer-N frequency synthesizer design. Circuit block diagram is shown in Fig.3-1. The reference frequency is 10MHz. A pulse-swallow counter is designed to control the dual-modulus divider (8/9). Except the loop filter, every block is designed on chip.
Fig.3-1 802.11a pulse-swallow integer-N frequency synthesizer architecture
3.2 QVCO Design [14][15]
In this chapter we adopt the differentially and complementary cross coupled pairs to generate low phase noise, symmetric and quadrature signal outputs. The
architecture is shown in Fig.3-2. The use of NMOS and PMOS complementary cross coupled pairs offering better rise and fall time symmetry, which results in low up-conversion of 1/f noise and other low frequency noise sources. The complementary structure also provides higher transconductance than all NMOS pairs making circuits much easier to start-up.
P0
Fig.3-2 Quadrature voltage controlled oscillator architecture
3.3 High speed Frequency Divider [16]
In this design, we adopt DFF operation principle to achieve divide-by-2 circuit.
The block diagram is shown in Fig.3-3(a). The DFF2 could be replaced by a delay device used to store Q1 value and flip DFF1 value at next trigger edge. At high frequency, digital logic DFF won’t work precisely. Analog DFF must be designed to attain this high frequency divide-by-2 circuit design. The DFF is shown in Fig.3-3(b).
（a） （b）
Fig.3-3（a）Block diagram of divide-by-2 circuit （b）Analog structure of DFF
The cross signal lines in DFF circuit should be layout carefully. Parasitic capacitance and resistance may cause circuit malfunction. We should take these parasitic effect into consider when simulating circuit performance. Fig.3-4 is the transient simulation result of inputting 5.5GHz, 100mV amplitude sine waves to circuit. Circuit will function at 4-6GHz. Minimum acceptable signal amplitude is 80mV.
Fig.3-4 Transient simulation result of inputting 5.5GHz, 100mV amplitude sine waves
3.4 Dual-modulus frequency divider [17][18]
For low power application, the NOR gates of DMFD are combined to D-type flip-flops, circuit shown in Figure.3-5(a). The DMFD architecture is also shown in Figure.3-5(b). Because DMFD uses two D-type flip-flops, it consumes more power than a single divide-by-2 circuit. Since the 4 outputs of these two DFFs are connected to each other, the parasitic capacitance is pretty large. The layout of DMFD should be laid in a high density way. Using Calibre extraction tool, the parasitic capacitance for
For low power application, the NOR gates of DMFD are combined to D-type flip-flops, circuit shown in Figure.3-5(a). The DMFD architecture is also shown in Figure.3-5(b). Because DMFD uses two D-type flip-flops, it consumes more power than a single divide-by-2 circuit. Since the 4 outputs of these two DFFs are connected to each other, the parasitic capacitance is pretty large. The layout of DMFD should be laid in a high density way. Using Calibre extraction tool, the parasitic capacitance for