Future works

The frequency detector reach is still going on. Once a high efficient, accurate frequency detector has been done, this new all-digital frequency synthesizer architecture could be completed. A high speed, high resolution DAC is needed to increase system frequency resolution and settling time. The all-digital frequency synthesizer is designed on the purposes of increasing system integration and shortening frequency settling time without any off-chip comportments.

Chapter 5

Conclusion and Future Work

5.1 Conclusion

This thesis contents three design works. This first work is high integration multi-bands Σ∆ fraction-N frequency synthesizer in TSMC 0.18µm CMOS. The second work is 802.11a integer-N frequency synthesizer in TSMC 0.25µm CMOS.

The third is 8-bit AFC voltage controlled oscillator in TSMC 0.18µm CMOS. All these three circuits have been fabricated through CIC. These circuit design concepts, simulation results, measurement data have been discussed in detail.

5.1.1 High integration quad-bands frequency synthesizer

A novel frequency division technique to integrate multi-band frequency synthesizer circuit design has been discussed in this thesis. This technique reduces chip dimension without scarifying phase noise and frequency resolution performances.

The 802.11a/b/g and GSM/DCS1800 quad-bands frequency synthesizers are perfectly combined in single chip. A 12-bit Σ∆ modulator helps increasing frequency resolution to satisfy GSM/DCS1800 200KHz channel bandwidth specification. To further reduce chip area, a register is used to load all digital control bits and voltage controlled oscillator bank control bits. The chip dimension is only 1.61mm2, half the dimension of other compared dual-band frequency synthesizer designs [1][4].

5.1.2 802.11a integer-N frequency synthesizer

In 802.11a application, the integer-N frequency synthesizer architecture is most commonly used. Since the 802.11a channel bandwidth is 20MHz, much higher than other application, the reference can be chosen as high as 10MHz to fasten frequency settling time. In order to lower power consumption, only one dual modulus frequency divider (÷8/9) is used in the work. A pulse-swallow counter is designed to control the dual modulus frequency divider in a period of 32 reference clocks. Reference frequency is 10MHz. Synthesized frequency is from 5.18GHz to 5.34GHz, 20MHz frequency step. Using MATLAB to design loop filter is a practical approach. The MATLAB step and bode functions helps designer efficiently simulate frequency synthesizer close loop settling time and open loop phase margin. The MATLAB program only takes minutes to simulate frequency synthesizer, while ELDO transient analysis takes almost a week!

5.1.3 All-digital frequency synthesizer

We have proposed new all-digital frequency synthesizer architecture. According to the 802.11a frequency tolerance of ±20ppm, at least 14-bit frequency resolution digital frequency resolution can satisfy system specification. The 14-bits are separated in two parts: 8-bit for varactor bank coarse tuning, 6-bit for control voltage fine tuning.

Once the designing problem of high efficient frequency detector has been solved, the new frequency synthesizer will promote RF frequency synthesizer integration and frequency settling time. The 8-bit frequency resolution voltage controlled oscillator measurement has been completed. Through this thesis, the research of high frequency

resolution voltage controlled oscillator by using PMOS varactor banks has been proven.

5.2 Future Work

Some aspects need to be improved below:

1. In the quad-bands frequency synthesizer design, the power of quad-bands signals should be increased to above -10dBm for practical telecommunication system.

Common drain structure isn’t suitable for large output power design, since common drain amplifier is intrinsically a power loss structure. The quad-bands output buffer structure should be modified. Common source output buffer is preferred because it provides power gain rather power loss.

2. The high frequency dividers in quad-bands frequency synthesizer design should be modified to provide more balanced output waveform.

3. In the integer-N frequency synthesizer design, the high frequency divide-by-2 circuit is connected to a buffer. This buffer cause signal voltage swing degradation. This buffer should be removed to increase signal voltage swing.

4. The charge pump in this thesis is a current mismatching circuit. The mismatching current will results in reference spurious noise and distort signal spectrum. A new charge pump structure has been designed and will integrate to frequency synthesizer in future designs.

5. High efficient frequency detector research is going on to complete the new all-digital frequency synthesizer.

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Publication List

1. Kuo-Hua Cheng, Cheng-Hung Chen, Po-Da Chen and Christina F. Jou, “A 20.5-mW, Fast-Switching Integer-N Frequency Synthesizer of 5.2GHz WLANs “, has been accepted by International Symposium on Communications and Information Technologies 2004 (ISCIT 2004), but not published due to economic problem.

2. Cheng-Hung Chen, Wei-Cheng Lien and Christina F. Jou, “A High-Integration, Quad Application Bands Σ∆ Fraction-N Frequency Synthesizer in 0.18-µm Standard CMOS Process”, has been submitted to Asia-Pacific Microwave Conference 2005.