It has been investigated that, for the SCR devices, different triggering methods and layout parameters would have different triggered voltage. Based on this characteristic, for the SCR-based transient detection circuit, it is possible to realize the transient-to-digital converter by using the different types of SCR device and without the noise filter networks. This would save more chip area and avoid the leakage problem for MOS capacitors in deep-submicron technology.
For the transient-to-digital converter, the voltage interval between two adjacent digital codes should be increased to further distinguish the different ESD voltages. For example, the detection level could be enhanced to meet the test level specified in the IEC 61000-4-2 standard. Furthermore, simulations of frequency response with different noise filter are shown in Fig. 5.1.
(a) (b)
Fig. 5.1 Frequency simulation results of noise filters (a) noise filters and (b) linear plot.
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And compared with the measurement results, Fig. 5.2 shows relationship between the bandwidth of the noise filters and test voltages.
(a) (b)
(c)
Fig. 5.2 Relationship between the bandwidth of the noise filters and test voltages (a) system-level ESD, (b) EFT, and (c)TLU.
On the other side, the frequency of the system-level ESD voltages should be further analyzed. The linear relation between ESD zapping voltages and digital codes should be improved by optimizing the noise filter networks.
Due to the transient disturbance under system-level ESD tests, the proposed on-chip transient-to-digital converter can detect the ESD-induced voltage variation on the power and ground lines. Nevertheless, the quantity of ESD-induced voltage variation is strongly
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dependent on the impedance of the EUT. The detection range of on-chip transient-to-digital converter would be influenced by this condition. For advanced applications, the on-chip transient-to-digital converter should be designed to detect ESD-induced current variation of power and ground lines under system-level ESD zapping condition.
In system application, the on-chip transient-to-digital converter can be cooperated with power-on reset circuits and operating firmware to provide a hardware/firmware co-design solution for system-level ESD protection. After firmware receives different digital codes as ESD index, different recover procedures can be executed and finally reset the output voltage levels of on-chip transient-to-digital converter as initial state for detecting next system-level ESD events. Therefore, the IC products can achieve the “class B” system-level ESD specification at least. Besides, in order to avoid transient disturbance coupling on reset pad, the modified transient-to-digital converter without reset function should be further investigated.
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Publication List
(A) Referred Journal Papers:
[1]. M.-D. Ker, W.-Y. Lin, and C.-C. Yen, “SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance,”
submitted to IEEE Trans. Electromagn. Compat., 2011. (SCI, EI, Impact Factor : 1.294)
(B) International Conference Papers:
[1]. M.-D. Ker, W.-Y. Lin, C.-C. Yen, C.-M. Yang, T.-Y. Chen, and S.-F. Chen,
“Protection design against system-level ESD transient disturbance on display panels,” in Proc. Asian-Pacific Int. Symp. Electromagn. Compat. (APEMC), 2010, pp. 445-448.
[2]. M.-D. Ker, W.-Y. Lin, C.-C. Yen, C.-M. Yang, T.-Y. Chen, and S.-F. Chen, “New transient detection circuit for electrical fast transient (EFT) protection design in display panels,” in Proc. IEEE Int. Conf. Integr. Circuit Design and Technology (ICICDT), 2010, pp. 51-54.
[3]. M.-D. Ker, W.-Y. Lin, C.-C. Yen, C.-M. Yang, T.-Y. Chen, and S.-F. Chen,
“On-chip ESD detection circuit for system-level ESD protection design,” in Proc.
IEEE Int. Conf. Solid-State and Integrated Circuit Technology (ICSICT), 2010, pp.
1584-1587.
[4]. W.-Y. Lin and C.-C. Yen, “New transient detection circuit to detect system-level ESD disturbance for automatic recovery operation in display panels,” in 2010 AMD Technical Forum, 2010.
[5]. C.-C. Yen, W.-Y. Lin, M.-D. Ker, C.-M. Yang, S.-F. Chen, and T.-Y. Chen, “New transient detection circuit to detect ESD-induced disturbance for automatic recovery design in display panels,” in 6th Int. Conf. Design and Technology of Integrated Systems (DTIS), 2011, in press.
[6]. C.-C. Yen, M.-D. Ker, W.-Y. Lin, C.-M. Yang, and T.-Y. Chen, “On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance,” in 13th Int. Conf. Electrostatics, 2011.
[7]. C.-C. Yen, W.-Y. Lin, and M.-D. Ker, “Transient-to-digital converter to detect electrical fast transient (EFT) disturbance for system protection design,” in Proc.
IEEE Int. Conf. Integr. Circuit Design and Technology (ICICDT), 2011.
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(C) Local Conference Papers:
[1]. W.-Y. Lin, C.-C. Yen, M.-D. Ker, C.-M. Yang, T.-Y. Chen, and S.-F. Chen, “New ESD transient detection circuit against system-level transient disturbance in TFT LCD panels,” in Electronic Technology Symposium, 2010.
[2]. 林宛彥、顏承正、柯明道、蔡青霖、楊哲明、陳東暘、陳世範, “應用於系統 層級靜電放電防護設計之新式暫態偵測電路,” in Proc. Taiwan ESD Conference, 2010, pp. 42-45.
[3]. M.-D. Ker, W.-Y. Lin, C.-C. Yen, C.-L. Tsai, S.-F. Chen, and T.-Y. Chen,
“Transient-to-digital converter to detect system-level ESD-induced disturbance in display panel,” accepted by VLSI Design/CAD Symposium, 2011.
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簡歷 (Vita)
姓 名：林宛彥
學 歷：
私立聖功女子高級中學 (91 年 9 月~94 年 6 月)
國立交通大學電子物理系 (94 年 9 月~98 年 2 月)
國立交通大學電子研究所碩士班 (98 年 2 月~100 年 9 月)
比利時天主教魯汶大學電機碩士班 (99 年 9 月~100 年 6 月)
研究所修習課程：
類比積體電路 吳介琮教授
數位積體電路 黃 威教授
積體電路之靜電放電防護設計特論 柯明道教授
計算機結構 劉志尉教授
類比濾波器設計 蔡嘉明教授
功率積體電路設計 陳科宏教授
奈米電子元件 荊鳳德教授
半導體物理及元件(一) 陳衛國教授
永久地址: 高雄市岡山區明得街 105 號 Email： [email protected]