Transient-Induced Latchup (TLU) Test

To evaluate the system-level ESD immunity of a single IC inside the equipment under test (EUT), a component-level transient-induced latchup (TLU) measurement setup was reported with the following two advantages [20]. First, the TLU immunity of a single IC can be evaluated by the measured voltage and current waveforms through the oscilloscope.

Second, with the ability of generating an underdamped sinusoidal voltage, it can accurately simulate how an IC inside the EUT is disturbed by the ESD-generated transient disturbance during the system-level ESD test. Fig. 3.7 illustrates such a component-level TLU measurement setup. A charging capacitance of 200pF is used to store the charges as the TLU-triggering source, VCharge, and then the stored charges are discharged to the device under test (DUT) through the relay. The underdamped sinusoidal voltage generated by TLU measurement is similar to the transient voltage on the power pins of CMOS ICs under the system-level ESD tests, whether polarity (positive or negative) of the ESD voltage is.

Moreover, a small current-limiting resistance of 5  is recommended to protect the DUT from electrical-over-stress (EOS) damage during the high-current (low-impedance) latching state.

The supply voltage of 3.3 V is used as VDD and the trigger source is directly connected to DUT through the relay in the TLU measurement setup.

Fig. 3.7 Measurement setup for transient-induced latchup (TLU) [20].

~ 29 ~

Figs. 3.8(a) and 3.8(b) show the measured VDD, VOUT1, and VOUT2 transient voltage waveforms of the on-chip SCR-based transient detection circuit under the TLU tests with VCharge of +9 V and -1 V, respectively. As shown in Fig. 3.8(a), under the TLU test with VCharge

of +9 V, VDD begins to increase rapidly from 3.3 V with positive-going underdamped sinusoidal voltage waveform. During the TLU test, VOUT1 and VOUT2 are influenced simultaneously by the positive-going underdamped sinusoidal voltage coupled to VDD power line. After the TLU test with the VCharge of +9 V, the output voltage VOUT1 of the proposed transient detection circuit is changed from 3.3 V to 1.2 V, which is equal to the SCR holding voltage. Through two-inverter buffer stage, VOUT2 of the proposed detection circuit is pulled down to 0 V. In Fig. 3.8(b), under the TLU test with VCharge of -1 V, VDD begins to decrease rapidly from 3.3 V with negative-going underdamped sinusoidal voltage waveform. During this TLU test, VOUT1 and VOUT2 are influenced simultaneously by the negative-going underdamped sinusoidal voltage coupled to VDD power line. After the TLU test with the VCharge of -1 V, the VOUT2 of the proposed transient detection circuit also transits from 3.3 V to 0 V.

From the TLU test results, the proposed on-chip SCR-based transient detection circuit can successfully memorize the occurrence of electrical transients. With positive or negative underdamped sinusoidal voltages coupled to VDD power line, the output voltage (VOUT2) of the proposed on-chip SCR-based transient detection circuit can be changed from logic “1” to logic “0” after TLU tests.

~ 30 ~

(a) (b)

Fig. 3.8 Measured VDD, VOUT1, and VOUT2 waveforms on the on-chip SCR-based transient detection circuit under TLU tests with the VCharge of (a) +9 V and (b) -1 V.

3.4.2. System-Level ESD Test

In IEC 61000-4-2, two test modes have been specified, which are the air-discharge and contact-discharge test mode. In the case of contact discharge test mode, the sharp discharge tip is used to simulate the mechanical ESD damage on the EUT. The contact discharge is applied to the conductive surfaces of the EUT (direct application) or to the coupling planes (indirect application). Contact discharge is further divided into direct discharge to the system under test, and indirect discharge to the horizontal or vertical coupling planes. Fig. 3.9 shows the measurement setup of the system-level ESD test standard with indirect contact-discharge test mode. The measurement setup of system-level ESD test consists of a wooden table on the grounded reference plane (GRP). In addition, an insulation plane is used to separate the EUT from the horizontal coupling plane (HCP). The HCP are connected to the GRP with two 470 k resistors in series [6]. When the ESD gun zaps the HCP, the electromagnetic interference (EMI) coming from ESD gun will be coupled into all CMOS ICs inside EUT. The power lines of CMOS ICs inside EUT will be disturbed by the ESD-coupled energy.

~ 31 ~

Fig. 3.9 Measurement setup for system-level ESD test with indirect contact-discharge test mode [6] to evaluate the detection function of the on-chip SCR-based transient detection circuit.

With such measurement setup, the circuit function of the proposed detection circuit after system-level ESD tests can be evaluated. By monitoring the oscilloscope, the transient responses on power lines of CMOS ICs can be recorded and analyzed. Before each system-level ESD test, the initial output voltages (VOUT1 and VOUT2) of the proposed detection circuit are all reset to 3.3 V. After each system-level ESD test, the output voltages (VOUT1 and VOUT2) are monitored to check their final voltage levels. Thus, the function of the proposed detection circuit can be evaluated under system-level ESD tests.

The measured VDD, VOUT1, and VOUT2 waveforms of the proposed detection circuit under system-level ESD test with the ESD voltage of +0.35 kV zapping on the HCP are shown in Fig. 3.10(a). VDD begins to rapidly increase from the normal voltage level of 3.3 V.

Meanwhile, VOUT1 and VOUT2 begin to change under such a high-energy ESD stress. During the fast transient disturbance, VDD, VOUT1, and VOUT2 are influenced simultaneously. Finally, VOUT1 is pulled down to 1.2 V. Through buffer stages, VOUT2 of the proposed detection circuit transits from 3.3 V to 0 V.

The measured VDD, VOUT1, and VOUT2 waveforms of the proposed detection circuit under system-level ESD test with the ESD voltage of -0.2 kV zapping on the HCP are shown in Fig.

~ 32 ~

3.10(b). During the ESD-induced transient disturbance, VDD begins to decrease rapidly from the original voltage level of 3.3 V. Finally, the output voltage (VOUT2) of the proposed transient detection circuit is changed from 3.3 V to 0 V.

Therefore, the new proposed on-chip SCR-based transient detection circuit can successfully detect the electrical transients under system-level ESD tests with positive or negative ESD voltages.

(a) (b)

Fig. 3.10 Measured VDD, VOUT1, and VOUT2 transient voltage waveforms of the on-chip SCR-based transient detection circuit under system-level ESD tests with ESD voltage of (a) +0.35 kV and (b) -0.2 kV.

3.4.3. Electrical Fast Transient (EFT) Test

The measurement setup for EFT test combined with attenuation network is shown in Fig.

3.11. EFT generator is connected to the DUT with VDD of 3.3 V through the attenuation network. In order to simulate the degraded EFT-induced transient disturbance on CMOS ICs inside the microelectronic products, the attenuation network with -40 dB degradation is used in this work. The amplitude of EFT-induced transients can be adjusted by the attenuation network.

~ 33 ~

Fig. 3.11 Measurement setup for EFT test combined with attenuation network [9].

Figs. 3.12(a) and 3.12(b) show the measured VDD, VOUT1, and VOUT2 transient responses of the proposed detection circuit under the EFT tests with input EFT voltages of +750 V and -400 V, respectively. As shown in Fig. 3.12(a), under the EFT test with positive voltage of +750 V, VDD begins to increase rapidly from 3.3 V with positive exponential voltage pulse.

During the EFT test, VOUT1 and VOUT2 are influenced simultaneously by the positive exponential voltage pulse coupled to VDD power line. After the +750-V EFT test, the output voltage VOUT1 (VOUT2) of the proposed detection circuit transits from 3.3 V to 1.2 V (0 V). In Fig. 3.12(b), under the EFT test with negative voltage of -400 V, VDD begins to decrease rapidly from 3.3 V with negative exponential voltage pulse. After the EFT test, the output voltage VOUT2 of the proposed detection circuit transits from logic “1” to logic “0”.

From the EFT test results shown in Figs. 3.12(a) and 3.12(b), either positive or negative EFT voltages coupled to VDD power line, the output voltage (VOUT2) of the proposed detection circuit can be changed from 3.3 V to 0 V. Therefore, the new proposed on-chip SCR-based transient detection circuit can successfully memorize the occurrence of EFT-induced exponential pulse transient disturbance.

~ 34 ~

(a) (b)

Fig. 3.12 Measured VDD, VOUT1, and VOUT2 waveforms on the on-chip SCR-based transient detection circuit under EFT tests with (a) +750-V and (b) -400-V EFT voltages combined with attenuation network.

3.5. Summary

A new on-chip SCR-based transient detection circuit to detect system-level electrical transient disturbance has been implemented in a 0.18-m CMOS process with 3.3-V devices.

By using P_STSCR device and RC-delay circuit, the proposed detection circuit is designed to detect fast electrical transients during the system-level ESD or EFT tests. Experimental results in silicon chip have successfully verified that the proposed detection circuit can successfully memorize the occurrence of electrical transients under system-level ESD or EFT tests. From the previous research, it is reasonable that with hardware/firmware co-design method, the output state of the proposed on-chip SCR-based transient detection circuit can be used as the firmware index to provide an effective solution against the system malfunction caused by system-level electrical transient disturbance.

~ 35 ~

Chapter 4

Design of On-Chip Transient-to-Digital Converter

4.1. Background

In the previous work [21], on-chip transient-to-digital converter with on-chip noise filters and RC-based transient detection circuit has been designed and fabricated. It has been investigated that the noise filter networks can enhance susceptibility of CMOS ICs to system-level ESD-induced transient disturbance by decoupling, bypassing, or absorbing ESD-induced voltage and energy. With different types of noise filter, the higher order noise filter located between the power and ground lines can provide better bypassing ability to reduce the ESD-induced energy coupled on power lines of CMOS ICs. As shown in Fig. 4.1, the previous on-chip noise filter (1) composed of two resistors and one 10-pF capacitor is used in previous transient-to-digital converter. However, as the technology and the CMOS process scaling down, the large 10-pF capacitor used in the noise filter not only occupies large area but also induces gate leakage current leakage which is not tolerable in deep sub-micron CMOS circuit design. Therefore, to solve these kinds of problems, in this chapter, a new transient-to-digital converter designed with novel type of noise filter and the CR-based transient detection circuit has been proposed and investigated under TLU, EFT, and system-level ESD tests. Under system-level ESD tests, the detection circuit with high-order noise filter would need more ESD coupling energy to change the output logic state; on the other side, the detection circuit with low-order noise filter would be more sensible to ESD disturbance and easily change the output logic state from logic “1” to logic “0”.

~ 36 ~

Fig. 4.1 The previous transient-to-digital converter [21].

With these design concepts of transient-to-digital converter, the positive and the negative fast electrical transient voltages under system-level tests can be converted to digital codes by different on-chip noise filter designs. By using the proposed on-chip transient-to-digital converter, the ESD voltage zapped into the CMOS ICs inside the microelectronics product can be quantified as digital codes under system-level ESD tests. Moreover, the output digital codes can be further co-designed with the firmware system to execute total or partial system recovery procedures.

4.2. New On-Chip CR-Based Transient Detection Circuit

4.2.1. Circuit Implementation

Fig. 4.2 shows the new proposed on-chip CR-based ESD detection circuit. The CR-based

~ 37 ~

circuit structure is designed to realize the transient detection function. The NMOS (Mnr) is used to provide the initial reset function to set the initial voltages at node VOUT and node VA

as 1.8 V with the VDD of 1.8 V in a 0.13-µm CMOS process. In Fig. 4.2, the node VG is biased at VSS during the normal operating condition. Under the system-level ESD stress with an overshooting ESD voltage, the node VG will be coupled with positive voltage. Then, the NMOS device (Mn1) can be turned on by the overshooting ESD voltage to pull down the voltage level at the node VA. Therefore, the logic level stored at the node VA can be changed from logic “1” to logic “0” to memorize the ESD-induced transient disturbance. With the buffer inverters, the output voltage is finally changed from 1.8 V to 0 V to detect the occurrence of system-level ESD events. Furthermore, by different combination design of R1

and R2, the ESD energy coupled to node VG can be adjusted. Therefore, the minimum ESD voltage to cause transition at the output (VOUT) of the proposed detection circuit can be designed by this resistive voltage divider technique.

  Fig. 4.2 The new proposed on-chip CR-based transient detection circuit.

4.2.2. HSPICE Simulation

It has been investigated that the underdamped sinusoidal voltage waveform has been observed on power line of CMOS IC during the system-level ESD stress. Therefore, a sinusoidal time-dependent voltage source given by

~ 38 ~

( ) 0 _asin(2 (  _d)) exp( (   _d) _a)

V t V V f t t t t D , (2)

is used to simulate ESD-induced transient disturbance coupled on the power lines of the proposed detection circuit. With the proper parameters (including the applied voltage amplitude Va, initial dc voltage V0, damping factor Da = 2x10⁷ s^-1, frequency f = 50 MHz, and time delay td = 300 ns), the underdamped sinusoidal voltage can be used to simulate the electrical transient waveforms under system-level ESD tests.

The simulated VDD and VOUT waveforms of the proposed detection circuit with a positive-going (negative-going) underdamped sinusoidal voltage on VDD line are shown in Fig.

4.3(a) (Fig. 4.3(b)). The positive-going underdamped sinusoidal voltage with amplitude of +3 V (-3 V) is used to simulate the coupling ESD transient noise under the system-level ESD test.

From the simulated waveforms, VDD begins to increase (decrease) rapidly from 1.8 V. VOUT

also acts with a positive-going (negative-going) underdamped sinusoidal voltage waveform during the simulated system-level ESD events on VDD line. After this disturbance duration, VDD returns to its normal voltage level of 1.8 V and the output state (VOUT) of the detection circuit is changed from 1.8 V to 0 V, as shown in Fig. 4.3(a) (Fig. 4.3(b)). As a result, the detection circuit can detect the occurrence of simulated ESD-induced electrical transients.

(a) (b)

Fig. 4.3 Simulated VDD and VOUT waveforms of the new proposed on-chip CR-based transient detection circuit under system-level ESD test with (a) positive-going, and (b) negative-going, underdamped sinusoidal voltages.

~ 39 ~

To confirm the minimum Va voltage, an exponential time-dependent voltage source with rise/fall time constant parameters is used to simulate the EFT-induced transient disturbance on the power lines of CMOS ICs. The rising edge of the exponential voltage pulse is expressed as

, when td1≤t≤td2. (3)

The falling edge of the exponential voltage pulse is expressed as

, when t≥td2. (4)

With the proper parameters such as rise (fall) time constant 1 (2), rise (fall) delay time td1

(td2), initial DC voltage value V1, and exponential pulse voltage V2, the exponential voltage source can be constructed to simulate the EFT-induced disturbance under EFT tests as shown in Fig. 4.4.

Fig. 4.4 The specific time-dependent exponential pulse waveform applied on the power lines to simulate the disturbance under EFT zapping.

Furthermore, with increasing resistor ratio of R1/R2, the ESD energy coupled to node VG

will be decreased and the minimum ESD amplitude (≡Va(min)) to cause transition of proposed

2 1 2

~ 40 ~

detection circuit will be increased. Simulation results show that, when R1 equals to 0 k and R2 equals to 50 k, minimum Va voltage to stimulate the detection circuit to transit output from logic high to logic low equals to +3 V, as shown in Fig. 4.5(a). When R1 increases its value to 45 k and R2 decreases to 5 k, minimum Va voltage for circuit transition would increase to +9 V, as shown in Fig. 4.5(b). As a result, the minimum amplitude of simulated EFT pulse to cause circuit transition would be different with different combination in resistive voltage divider techniques, as shown in TABLE XI.

(a) (b)

Fig. 4.5 CR-based transient detection circuit (a) without and (b) with resistor divider.

TABLE IX Simulation results of the minimum EFT amplitude corresponding to different resistor combinations used in resistive voltage divider.

R1 R2 The minimum amplitude of EFT pulse to cause transition of detection circuit

0 k 50 k +3 V

15 k 35 k +4 V

25 k 25 k +5 V

35 k 15 k +6 V

45 k 5 k +9 V



~ 41 ~

4.3. Experimental Results

The proposed detection circuit has been designed and fabricated in a 0.13-m CMOS process. The fabricated chip for transient disturbance tests is shown in Fig. 4.6. The silicon area of the proposed on-chip CR-based detection circuit is 245 m x 155 m.

Fig. 4.6 Chip photo of the new proposed on-chip CR-based transient detection circuits fabricated in a 0.13-m CMOS process.

4.3.1.. Transient-Induced Latchup (TLU) Test

Fig. 4.7 depicts such a component-level transient-induced latchup (TLU) measurement setup on display system. Figs. 4.8(a) and 4.8(b) show the measured VDD and VOUT transient responses of the proposed detection circuit under the TLU test with VCharge of +200 V and -200 V, respectively. As shown in Fig. 4.8(a), under the TLU test with VCharge of +200 V, VDD

begins to increase rapidly from 1.8 V with positive-going underdamped sinusoidal voltage waveform. During the TLU test, VOUT is influenced simultaneously with positive-going underdamped sinusoidal voltage coupled to VDD power line. After the TLU test with the VCharge of +200 V, the output voltage (VOUT) of the proposed detection circuit can transit from 1.8 V to 0 V. In Fig. 4.8(b), under the TLU test with VCharge of -200 V, VDD begins to decrease rapidly from 1.8 V with negative-going underdamped sinusoidal voltage waveform. During

~ 42 ~

the TLU test, VOUT is influenced simultaneously with negative-going underdamped sinusoidal voltage coupled to VDD power line. After the TLU test with the VCharge of -200 V, the output voltage (VOUT) of the proposed detection circuit can transit from 1.8 V to 0 V.

From the TLU test results, the proposed detection circuit can successfully memorize the occurrence of electrical transients coupled on power line of display system. With positive or negative underdamped sinusoidal voltages coupled to 1.8-V power line, the output voltages (VOUT) of the proposed detection circuit can both change from logic“1” to logic“0” after TLU tests.

Fig. 4.7 Measurement setup for transient-induced latchup (TLU) test on display panel.

~ 43 ~

(a) (b)

Fig. 4.8 Measured VDD and VOUT waveforms on the new proposed CR-based transient detection circuit under TLU tests with VCharge of (a) +200 V, and (b) -200 V.

4.3.2. System-Level ESD Test

Fig. 4.9 shows the measurement setup of the system-level ESD test standard with air-discharge test mode in a display system. When the ESD gun is approaching the EUT, the electromagnetic interference (EMI) coming from ESD gun will be coupled into all CMOS ICs inside EUT. The power lines of CMOS ICs inside EUT will be disturbed by the ESD-coupled energy.

Fig. 4.9 Measurement setup for system-level ESD test with air discharge test mode. [6]

~ 44 ~

With such a measurement setup shown in Fig. 4.9, the circuit function of the proposed detection circuit after system-level ESD tests can be evaluated. Before each system-level ESD test, the initial output voltage (VOUT) of the proposed detection circuit is reset to 1.8 V. After each system-level ESD test, the output voltage (VOUT) level is monitored to check the final voltage level and to verify the detection function.

The measured VDD and VOUT waveforms of the proposed detection circuit under system-level ESD test with the ESD voltage of +4 kV are shown in Fig. 4.10(a). VDD begins to increase rapidly from the normal voltage of +1.8 V. Meanwhile, VOUT is disturbed under such a high-energy ESD stress. During the period with positive-going ESD-induced electrical transient disturbance, VDD and VOUT are influenced simultaneously. Finally, the output voltage (VOUT) of the proposed detection circuit transits from 1.8 V to 0 V. Therefore, the proposed detection circuit can sense the positive-going electrical transient on the power line and

The measured VDD and VOUT waveforms of the proposed detection circuit under system-level ESD test with the ESD voltage of +4 kV are shown in Fig. 4.10(a). VDD begins to increase rapidly from the normal voltage of +1.8 V. Meanwhile, VOUT is disturbed under such a high-energy ESD stress. During the period with positive-going ESD-induced electrical transient disturbance, VDD and VOUT are influenced simultaneously. Finally, the output voltage (VOUT) of the proposed detection circuit transits from 1.8 V to 0 V. Therefore, the proposed detection circuit can sense the positive-going electrical transient on the power line and