4.4.1. Circuit Implementation
The new proposed on-chip transient-to-digital converters composed of two circuit blocks, the on-chip noise filter and the CR-based transient detection circuit blocks. In order to reduce capacitor size used in noise filter (1), as shown in Fig.4.1, the current amplification technique in proposed active clamp has been investigated [22]. The active clamp circuit is shown in Fig.
4.13. A current mirror with current-gain device width ratio of N is used to multiply the capacitance (C1). The current through the node Vx is multiplied N+1 times, thus allowing the capacitor C1 to increase by a factor of N+1 to achieve desired RC1 time constant. Numerical computation shows the same result as following:
( 1) By using current amplification concept in Fig. 4.13, the 3-pF capacitor designed with current mirror circuit can be used to replace 10-pF capacitor in noise filter (1). Therefore, with different device width ratio of MN2 over MN1 (≡N), different equivalent capacitance used in noise filters were implemented to bypass or absorb the electrical transient disturbance energy.
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Fig. 4.13 Schematics of the active clamp [22].
Using HSPICE tool and the parameters mentioned in equation (2), when VDD was disturbed by underdamped sinusoidal voltages, the ESD-induced energy coupled on power lines can be different with different current-gain device width ratios. Simulation results are shown in Fig. 4.14. The device width ratio in Fig. 4.14(a) equals to 1 (=1:1), whereas that in Fig. 4.14(b) is 8 (=1:8). When the amplitude of zapping underdamped sinusoidal voltages is 9 V, the peak-to-peak amplitude of transient waveform coupled on Fig. 4.14 (a) (Fig. 4.14 (b)) can be decreased to 12.7 V (11.8 V). Simulation results show that when the current-gain device width ratios increase, the effective capacitance between power lines can be increased due to current magnification. Above all, the transient-to-digital converter consists of four different noise filters and four CR-based transient detection circuits with resistive voltage divider. Therefore, for 4-bit transient-to-digital converter design, the energy coupled into power line of each detection circuit can be different by combining four different current-gain device width ratios.
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(a) (b)
Fig. 4.14 Simulation results of the noise filters with different MN2 over MN1 device ratios of (a) 1:1 and (b) 1:8.
The schematic of the proposed 4-bit transient-to-digital converter is shown in Fig. 4.15.
Four different noise filters (2) with 3-pF on-chip capacitor and four different current amplifier designs are used to provide noise filter function under TLU, EFT, and system-level ESD tests.
For four current amplifiers, the current-gain device width ratios are ranging from 1:1 to 1:8.
The CR-based detection circuit with four different resistive voltage divider designs can adjust ESD level to cause output signal transition in advance. Therefore, with resistive voltage divider and capacitance multiplier techniques, the detection circuit combined novel noise filter design can decrease the suppressed ESD-induced energy coupled on power lines of CMOS ICs and adjust the minimum amplitude to trigger transition of CR-based detection circuit. When the ESD disturbance happened, the outputs of four CR-based transient detection circuits would be influenced simultaneously, but the transient disturbance affected on the power lines of each detection circuit is different owing to the different current-gain device width ratios and R1/R2 resistor ratios. By suppressing transient disturbance coupled on internal power lines into different levels, the four detection circuit would have different output voltage responses. Therefore, the system-level ESD-induced energy can be further converted into digital codes and correspond to different quantities of ESD stresses coupling into the CMOS ICs under system-level ESD tests.
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Fig. 4.15 Schematic of the proposed 4-bit transient-to-digital converters.
4.4.2. Experimental Results
The layout of proposed on-chip 4-bit transient-to-digital converter is consisted of four unit cells of CR-based detection circuit and different on-chip noise filter networks. The silicon area is 600 m x 600 m, as shown in Fig. 4.16.
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Fig. 4.16 Chip photo and layout of the proposed 4-bit transient-to-digital converter realized in a 0.13-m CMOS process. (This project is supported by Himax Technologies Inc.)
System-level ESD gun, TLU, and EFT tests were used to verify the circuit performance of the proposed on-chip 4-bit transient-to-digital converter. The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of on-chip transient-to-digital converter under system-level ESD with positive ESD voltage of +0.7 kV are shown in Fig. 4.17 (a). When the power and ground lines of transient-to-digital converter are affected by ESD stress under system-level ESD test, VOUT1, VOUT2, VOUT3 and VOUT4 are influenced simultaneously. Due to the different noise suppression by on-chip noise filters and the required noise amplitude enhancement by resistive voltage divider, VOUT1 is changed from 1.8 V to 0 V, and VOUT2, VOUT3, and VOUT4 are still kept at 1.8 V. Therefore, for the proposed converter, +0.7-kV system-level ESD zapping can be successfully converted into digital code “1110.”
The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of on-chip transient-to-digital converter under system-level ESD with positive ESD voltage of +0.8 kV are shown in Fig.
4.17 (b). When the power and ground lines of transient-to-digital converter are affected by ESD stress under system-level ESD test, VOUT1, VOUT2, VOUT3, and VOUT4 are influenced at the same time. VOUT1 and VOUT2 are changed from 1.8 V to 0 V, and VOUT3 and VOUT4 are still kept their initial voltage of 1.8 V. Therefore, +0.8-kV system-level ESD zapping can be
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successfully converted into digital code “1100.”
The measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of on-chip transient-to-digital converter under system-level ESD with positive ESD voltage of +1.0 kV are shown in Fig.
4.17 (c). When the power and ground lines of transient-to-digital converter are affected by ESD stress under system-level ESD test, VOUT1, VOUT2, VOUT3, and VOUT4 are influenced simultaneously. VOUT1, VOUT2, and VOUT3 are changed from 1.8 V to 0 V and VOUT4 are still kept at initial voltage of 1.8 V. Therefore, +1.0-kV system-level ESD zapping can be successfully converted into digital code “1000.”
Furthermore, the measured VOUT1, VOUT2, VOUT3, and VOUT4 waveforms of on-chip transient-to-digital converter under system-level ESD with positive ESD voltage of +1.3 kV are shown in Fig. 4.17 (d). When the power and ground lines of transient-to-digital converter are affected by ESD stress under system-level ESD test, VOUT1, VOUT2, VOUT3, and VOUT4 are influenced simultaneously. VOUT1, VOUT2, VOUT3, and VOUT4 are all changed from 1.8 V to 0 V.
Therefore, the +1.3-kV system-level ESD zapping can be successfully converted into digital code “0000.”
The measured VOUT1, VOUT2, VOUT3, and VOUT4 voltage waveforms of the proposed transient-to-digital converter under system-level ESD test with ESD voltage of -0.2 kV are shown in Fig. 4.18(a). During the fast transient of ESD stress, all transient detection circuits are affected by ESD-induced transient disturbance coupled on VDD line. Finally, VOUT1 transits from logic “1” to logic “0” while VOUT2, VOUT3, and VOUT4 are still kept at logic “1” states.
Therefore, the -0.2-kV system-level ESD zapping can be successfully converted into digital code “1110.”
Similarly, under system-level ESD tests with ESD voltages of -0.3 kV, -0.6 kV, and -1.1 kV, the transferred digital codes generated by proposed 4-bit transient-to-digital converter are
“1100,” “1000,” and “0000”, as shown in Figs. 4.18(b)-(d). Similarly, the same trends of the digital code transformation have been observed under TLU tests and EFT tests. When the
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transient disturbed energy goes larger, the output of the transient-to-digital can transfer into the codes of “1110,” “1100,” “1000,” to “0000” in order. Measurement results of TLU (EFT) tests with positive and negative voltage levels are shown in Fig. 4.19 and Fig. 4.20 (Fig. 4.21 and Fig. 4.22), respectively. The completed measured results of transient-to-digital converter under system-level ESD test, TLU test, and EFT test are listed in TABLE XI. From the measurement results, the detection and response time of the proposed converter is about 300 ns.
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(a) (b)
(c) (d)
Fig. 4.17 Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient waveforms under positive system-level ESD tests with ESD voltage of (a) +0.7 kV, (b) +0.8 kV, (c) +1.0 kV, and (d) +1.3 kV.
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(a) (b)
(c) (d)
Fig. 4.18 Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient waveforms under negative system-level ESD tests with ESD voltage of (a) -0.2 kV, (b) -0.3 kV, (c) -0.6 kV, and (d) -1.1 kV.
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(a) (b)
(c) (d)
Fig. 4.19 Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient waveforms under positive TLU tests with VCharge of (a) +8 V, (b) +13 V, (c) +16 V, and (d) +25 V.
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(a) (b)
(c) (d)
Fig. 4.20 Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient waveforms under negative TLU tests with VCharge of (a) -8 V, (b) -9 V, (c) -10 V, and (d) -12 V.
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(a) (b)
(c) (d)
Fig. 4.21 Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient waveforms under positive EFT tests with EFT voltage of (a) +400 V, (b) +500 V, (c) +700 V, and (d) +2000 V.
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(a) (b)
(c) (d)
Fig. 4.22 Measured VOUT1, VOUT2, VOUT3, and VOUT4 transient waveforms under negative EFT tests with EFT voltage of (a) -410 V, (b) -450 V, (c) -500 V, and (d) -700 V.
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TABLE XI
Measurement results of digital codes corresponding to transient voltages under system-level ESD, TLU, and EFT tests.
Digital
To perform the hardware/firmware co-design, the digital codes from transient-to-digital converter can be temporarily stored as system recovery index for firmware check. The display system can be programmed to execute different recovery procedures according to different digital codes with the consideration of system recovery time and energy saving.
At the beginning, the output digital code is set as “1111.” When the electrical transients happen, the transient-to-digital converter can detect the occurrence of system-level electrical transient disturbance and transfer the ESD voltage levels into digital codes. At this moment, the firmware index is also changed to initiate system recovery procedure to restore system to a known stable state as soon as possible. According to different digital codes, the firmware can program corresponded system recovery procedures. For example, under system-level ESD test with low ESD voltage zapping, the transferred digital code is “1110” and the firmware can execute partial system recovery procedure in display panel, as shown in Fig. 4.23(a). With high ESD zapping, the transferred digital code is “0000” and the firmware can execute total
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system recovery procedure, as shown in Fig. 4.23(b).
For system initial state setting, the power-on reset circuit can further design into hardware/firmware co-design to set the initial digital code into “1111.” However, there are some mis-triggered conditions for power-on reset circuit. For example, a sudden surge can result in a very short interval between the power-down and power-up transitions. Such short interval of power-off creates difficult situations for some power-on reset circuits to work properly. Therefore, the NAND logic gate circuit can be further added into the hardware/firmware co-design flow. The VOUT1 signal of transient-to-digital converter and the output signal of power-on reset circuit are connected as the input signals of NAND logic gate.
When electrical transient disturbance happens, the system recovery procedure can be still initiated to protect microelectronic display products against the electrical transitions caused by system-level ESD events.
(a)
(b)
Fig. 4.23 Hardware/firmware operation in display panel system during (a) low, and (b) high system-level ESD zapping conditions.
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4.5 Summary
The new proposed on-chip 4-bit transient-to-digital converter composed of noise filter networks and CR-based transient detection circuits has been designed and fabricated in a 0.13-m process with 1.8-V devices. By using on-chip noise filter to reduce the transient disturbance voltage on the power and ground lines of CMOS ICs, the minimum system-level ESD voltage to cause transition at outputs of four transient detection circuits can be adjusted.
From the measurement results, the proposed on-chip transient-to-digital converter can successfully detect and transfer electrical transient energy into digital codes under TLU, EFT, and system-level ESD tests. Furthermore, these output digital codes can be used as the firmware index to execute different auto-recovery procedures of industrial products.
Compared to the previous work shown in Fig. 4.1, the new proposed transient-to-digital converter can reduce the silicon area and still provide the output digital codes corresponding to different ESD-induced/ EFT-induced transient disturbance.
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