Chapter 4 Effects of SiN Capping on NBTI of PMOSFETs
4.1.2 Dynamic NBTI
The conventional NBTI based on static experimental data. During normal
operations of digital circuits, the applied bias to the gate of PMOSFETs in a CMOS
inverter is switched between “high” and “low” voltages. During “low” phase of
PMOSFETs applied bias, the “electric passivation” effect may effectively reduce the
interface traps generated during the “high” phase. The dynamic NBTI (DNBTI) effect
greatly prolongs the lifetime of PMOSFETs operating in a digital circuit, while the
25
conventional static NBTI measurement underestimates the PMOSFET lifetime.
Furthermore, the DNBTI effect is dependent on temperature and gate oxide thickness
[52]. A physical model is proposed for DNBTI that involves the interaction between
hydrogen and silicon dangling bonds [53]. According to this reaction-diffusion theory,
the Δ Vth is attributed to the creation of interface traps as a consequence of
dissociation of Si-H bonds, and subsequent diffusion of the released hydrogen species
towards the gate electrode. In the recovery process, released hydrogen re-passivates Si
dangling bonds [53]. The ΔVth recovery progresses in accordance with the power law
dependency as follows:
n
V =A-B tth
∆ ⋅ , (4-10)
where B/A ratio indicates the ratio of a recovery reaction coefficient to ΔVth just
after NBT stress. This finding has significant impact on the determination of maximum
operation voltage as well as lifetime for future scaling of CMOS devices. Therefore, it is
critically important to investigate NBTI under such dynamic stress conditions.
26 4.2 Experimental Results and Discussion
4.2.1 Static NBTI Characterization
Figure 4.3 shows the results of NBTI stress performed at 25°C with gate overdrive
bias of –3.9 V (VGO = VG - Vth). As can be seen in Fig. 4.3(a), larger change in threshold
voltage shift, ΔVth, is observed in the device with SiN capping layer. The shift curves
show a fractional power-law dependence on time, and the exponential values with
SiN-capping sample are larger than the control sample. According to the classical
reaction-diffusion model, such dependence implies that NBTI is controlled by the
diffusion. From Fig. 4.3(b), the maximum value of transconductance, Gmmax, degrades
gravely in the device with SiN layer. The increase of interface trap density, ΔNit, for
devices with SiN capping layer are larger than that of control case, as shown in Fig.
4.3(c). The exponential value ofΔNit in power-law relationship is higher for devices
with SiN capping. Similar phenomenon is also observed for the generation of oxide
trapped charges, ΔNot, as shown in Fig. 4.3(d).
The above results clearly indicate that the use of PECVD SiN capping may result
in degraded NBTI. Two plausible origins are postulated to explain the worsen NBTI: (1)
Higher density of Si-H bonds at the oxide/Si interface, since the SiN layer contains a
27
large amount of hydrogen species because of the use of SiH4 and NH3 precursor gases;
(2) Higher strain energy stored in the channel. The energy may help trigger the
electrochemical reactions at the interface. This is evidenced by the higher exponent
value of the power-time dependence for devices with SiN capping.
Figure 4.4 shows the results after NBTI stress at 125°C. The trends are similar to
those occurring at 25°C. The devices with SiN-capping have aggravated NBTI issue. It
should be noted that in Fig. 4.4(a), Fig. 4.4(c) and Fig. 4.4(d), nearly saturation inΔVth,
ΔNit andΔNot are observed for the device with SiN capping when the stress time is
longer than 1000 sec. The NBTI is related to the amount of hydrogen species bonded at
the oxide/Si interface, and ∆Nit should eventually saturate when nearly all Si-H bonds
are broken. The disparity between the two splits is postulated to be caused by the local
strain induced in the SiN capping split. The existence of strain weakens the bond
strength of hydrogen species that in turn accelerates the bond-breaking process. Such
phenomenon is not observed in the control devices due to the lack of high strain in the
channel.
Figures 4.5 ~ 4.7 show ΔVth and ΔNit characteristics as a function of time under
different VGO at 25°C for the three splits of samples. ΔVth andΔNit for all cases
increase with increasing stress voltage. The exponential value of ΔVth and ΔNit in
28
power-law relationship are similar under different stress conditions in each split.
Because of ΔNit ∝ Eox1.5, higher VGO can induce larger amount of Nit and degradation.
Figures 4.8 ~ 4.10 illustrate ΔVth and ΔNit evolution under different VGO aging at
125°C for the three splits of samples. The trend for ΔVth at 125°C is similar to the
results at 25°C. However, the exponential value of ΔNit in power-law relationship
decreases with increasing stress bias for the devices with SiN capping. It can be
concluded that larger amounts of SiH bonds are broken by higher stress bias during
early stress aging. Figures 4.11 and 4.12 illustrate the temperature dependence
(Arrehenius plots) of ΔVth, ΔNit andΔNot under 1000 sec stressing. The slope
(activation energy) is larger for the devices with SiN capping.
4.2.2 DNBTI and AC stress
To simulate the switching operation of the device in the CMOS circuits, the gate
voltage during NBTI stress is switched between negative and positive bias for all splits
as shown in Figures 4.13 ~ 4.15. The condition during stress periods was for 125°C,
VGO = –4 V, while that for passivation periods VG was set at several biases. Other
terminals were grounded during the measurement. As can be seen in Figs. 4.13(a),
4.14(a) and 4.15(a), theΔVth, reductions of VG = +1 V during passivation are more
significant than VG = 0 V. We found that the degradation in the stress periods worsens
29
when higher strain is contained in the channel. The trends in interface trap density shift
are similar among the three splits, as shown in Fig. 4.13(b), Fig. 4.14(b) and Fig.
4.15(b), which have weaker dependence on the recover voltage. BecauseΔNit is
proportionate to ΔVth even at different positive biases during DNBT stressing, as
shown in Fig. 4.16(a), Fig. 4.17(a) and Fig. 4.18(a), it can be concluded that ΔVth is
directly affected by ΔNit during entire dynamic stress period. However, it should be
noted that in Fig. 4.16(b), Fig. 4.17(b) and Fig. 4.18(b), the decreases in ΔVth do not
follow the consistent decrease in ΔS, especially for the case with passivation bias VG =
+1 V. It may be due to the electron trapping related to the positive hydrogen charges in
the gate dielectric according to reactions (4-8). The B/A ratio of DNBTI is shown in
Table. 4.1. The recovery reaction coefficients are similar between strained and
unstrained cases.
Furthermore, the frequency dependences of NBT degradation were measured and
shown in Figs. 4.19 to 4.21 with 50% duty cycle. ΔVth and ΔNit are plotted as a
function of frequency, as shown in Fig.4.17. Both ΔVth and ΔNit are strongly
dependent on frequency for devices with SiN capping layer. The results indicate that the
stress under higher AC frequency shows lessΔVth andΔNit degradation. It is due to the
shortened stress time with increased frequency. It results in parts of broken SiH bonds
30
being recovered before entering the next stress state. Interface trap generation would be
contained by increase AC stress frequency and Δ Vth is suppressed indirectly.
Reduction in NBT degradation for strained-channel devices under AC stress is more
significant than the control case, mainly because the amount of broken SiH bonds with
SiN capping layer is larger than the control sample.
31
Chapter 5 Conclusions
5.1 Conclusions
Using poly-SiGe as gate material to fabricate PMOSFETs has numerous
advantages, including reduced gate depletion effect and improved gate sheet resistance.
Compressive PECVD SiN layer could significantly enhance the drive current of PMOS devices at either room or raised operating temperatures (125 °C) due to increase of hole
mobility, as shown in our experiment. The degrees of mobility enhancement are
enlarged as devices geometry is scaled down. Despite this merit, our results also
indicate that the SiN capping may aggravate the NBTI characteristics. A high amount of
hydrogen species contained in the PE-SiN layer as well as the strain energy stored in the
channel may be the culprits for the worsened reliability. The interface trap density
change and threshold voltage shift recover significantly during passivation periods.
We’ve also observed that the strained channel device is influenced strongly by AC stress
frequency.
32
References
[1] K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A.
Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson and M.
Bohr, “Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology”, VLSI Symp. Tech. Dig., pp.50, 2004.
[2] R. Khamankar, H. Bu, C. Bowen, S. Chakravarthi, P.R. Chidambaram, M. Bevan, A. Krishnan, H. Niimi, B. Smith, J. Blatchford, B. Hornung, J.P. Lu, P. Nicollian, B. Kirkpatrick, D. Miles, M. Hewson, D. Farber, L. Hall, H. AlShareef, A.
Varghese, A. Gurba, V. Ukraintsev, B. Rathsack, J. DeLoach, J. Tran, C.
Kaneshige, M. Somervell, S. Aur, C. Machala and T. Grider, “An Enhanced 90nm High Performance Technology with Strong Performance Improvements from Stress and Mobility Increase through Simple Process Changes”, VLSI Symp. Tech.
Dig., pp.162, 2004.
[3] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained silicon MOSFET technology”, IEDM Tech. Dig., pp.23-26, December 2002.
[4] B. H. Lee, A. Mocuta, S. Bedell, H. Chen, D. Sadana, K. Rim, P. O'Neil, R. Mo, K.
Chan, C. Cabral, C. Lavoie, D. Mocuta, A. Chakravarti, R. M. Mitchell, J.
Mezzapelle, F. Jamin, M. Sendelbach, H. Kermel, M. Gribelyuk, A. Domenicucci, K. A. Jenkins, S. Narasimha, S. H. Ku, M. Ieong, I. Y. Yang, E. Leobandung, P.
Agnello, W. Haensch, and J. Welser, “Performance enhancement on sub-70nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D”, IEDM Tech. Dig., pp.946-948, December 2002.
33
[5] C. Ge, C. Lin, C. Ko, C. Huang, Y. Huang, B. Chan, B. Perng, C. Sheu, P. Tsai, L.
Yao, C. Wu, T. Lee, C. Chen, C. Wang, S. Lin, Y. Yeo, and C. Hu,
“Process-strained Si (PSS) CMOS technology featuring 3D strain engineering”, IEDM Tech. Dig., pp.73-76, December 2003.
[6] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K.
Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M.
Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors”, IEDM Tech. Dig., pp.978-980, December 2003.
[7] C. S. Smith, Phys. Rev., Vol. 94, pp.42-49, 1954.
[8] F. Ootsuka, S. Wakahara, K. Ichinose, A. Honzawa, S. Wada, H. Sato, T. Ando, H.
Ohta, K. Watanabe, and T. Onai, “A highly dense, high-performance 130nm node CMOS technology for large scale system-on-a-chip applications”, IEDM Tech.
Dig., pp.575-578, December 2000.
[9] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N.
Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical stress effect of etch-stop Nitride and its impact on deep submicron transistor design”, IEDM Tech.
Dig., pp.247-250, December 2000.
[10] G. Timp, A. Agarwal, F. H. Baumann, T. Boone, M. Buonanno, R. Cirelli, V.
Donnelly, M. Foad, D. Grant, M. Green, H. Gossmann, S. Hillenius, J. Jackson, D.
Jacobson, R. Kleiman, A. Kornblit, F. Klemens, J. T. Lee, W. Mansfield, S.
Moccio, A. Murrell, M. O'Malley, J. Rosamilia, J. Sapjeta, and P. Silverman, “Low leakage, ultra-thin gate oxides for extremely high performance sub-100nm nMOSFETs”, IEDM Tech. Dig., pp.930-932, December 1997.
[11] B. Maiti, P. J. Tobin, V. Misra, R. I. Hegde, K. G. Reid, and C. Gelatos, “High
34
performance 20Å NO oxynitride for gate dielectric in deep sub-quarter micron CMOS technology”, IEDM Tech. Dig., pp.651-654, December 1997.
[12] T. Aoyama, K. Suzuki, H. Tashiro, Y. Tada, and H. Arimoto, “Flat-band voltage shifts in P-MOS devices caused by carrier activation in P+-polycrystalline silicon and boron penetration”, IEDM Tech. Dig., pp.627-630, December 1997.
[13] H. P. Tuinhout, A. H. Montree, J. Schmitz, and P. A. Stolk, “Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors”, IEDM Tech. Dig., pp.631-634, December 1997.
[14] T. King, J. R. Pfiester, and K. C. Saraswat, “A variable-work-function polycrystalline-Si1-xGex gate material for submicrometer CMOS technologies”, IEEE Electron Device Lett., Vol. 12, pp. 533 - 535, October 1991.
[15] D. A. Antoniadis and J. E. Chung, “Physics and technology of ultra short channel MOSFET devices”, IEDM Tech. Dig., pp.21-24, December 1991.
[16] T. King, J. R. Pfiester, J. D. Shott, J. P. McVittie, and K. C. Saraswat, “A polycrystalline-Si1-xGex-gate CMOS technology”, IEDM Tech. Dig., pp.253-256, December 1990.
[17] V. Z. Li, M. R. Mirabedini, R. T. Kuehn, J. J. Wortman, and M. C. Öztürk, “Single gate 0.15µm CMOS devices fabricated using RTCVD in-situ boron doped Si1-xGex gates”, IEDM Tech. Dig., pp.833-836, December 1997.
[18] C. Salm, D. T. van Veen, D. J. Gravesteijn, J. Holleman,and P. H. Woerlee,
“Diffusion and Electrical Properties of Boron and Arsenic Doped Poly-Si and Poly-GexSi1–x (x ~ 0.3) as Gate Material for Sub-0.25 µm Complementary Metal Oxide Semiconductor Applications”, J. Electrochem. Soc., vol.144, pp.3665–3673, 1997.
[19] T. King, J. P. McVittie, K. C. Saraswat, and J. R. Pfiester, “Electrical properties of heavily doped polycrystalline silicon-germanium films”, IEEE Trans. Electron
35 Devices, Vol. 41, pp.228-232, February 1994.
[20] P. Hellberg, S. Zhang, and C. S. Petersson, “Work function of boron-doped polycrystalline SixGe1-x films”, IEEE Electron Device Lett., Vol. 18, pp.456-458, September 1997.
[21] P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, “Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET's”, IEEE Trans.
Electron Devices, Vol. 35, pp.2194-2209, December 1988.
[22] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H.
Iwai, “1.5 nm direct-tunneling gate Oxide Si MOSFET's”, IEEE Trans. Electron Devices, Vol. 43, pp.1233-1242, August 1996.
[23] Shin-ichi Takagi and Mariko Takayanagi, “Experimental Evidence of Inversion-Layer Mobility Lowering in Ultrathin Gate Oxide Metal-Oxide-Semiconductor Field-Effect-Transistors with Direct Tunneling Current”, Jpn. J. Appl. Phys. Vol. 41, pp.2348-2352, 2002
[24] Taizoh Sadoh, Fitrianto, Atsushi Kenjo, Akihiro Miyauchi, Hironori Inoue and Masanobu Miyao, “Mechanism of Improved Thermal Stability of B in Poly-SiGe Gate on SiON”, Jpn. J. Appl. Phys. Vol. 41, pp.2468, 2002
[25] S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y.
Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, and T. Maeda,
“Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs”, IEDM Tech. Dig., pp.
57-60, December 2003.
[26] K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S.
Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P.
Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, “Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs”,
36 IEDM Tech. Dig., pp.47-52, December 2003.
[27] T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, T. Maeda, and S. Takagi, “Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility”, IEDM Tech. Dig., pp.31-34, December 2002.
[28] I. Åberg, O.O. Olubuyide, C. Ní Chléirigh, I. Lauer, D.A. Antoniadis, J. Li, R. Hull and J.L. Hoyt, “Electron and Hole Mobility Enhancements in Sub-10 nm-thick Strained Silicon Directly on Insulator Fabricated by a Bond and Etch-back Technique”, VLSI Symp. Tech. Dig., pp.52, 2004.
[29] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J.
Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S.
Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, “A logic nanotechnology featuring strained-silicon”, IEEE Electron Device Lett., Vol. 25, pp.191-193, April 2004.
[30] W. Zhao, J. He, R. E. Belford, L. Wernersson, and A. Seabaugh, “Partially depleted SOI MOSFETs under uniaxial tensile strain”, IEEE Trans. Electron Devices, Vol. 51, pp.317-323, March 2004.
[31] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, “Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement”, IEDM Tech. Dig., pp. 433 - 436, December 2001.
[32] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS Drive current reduction caused by transistor layout and trench isolation induced stress”, IEDM Tech. Dig., pp.827-830, December 1999.
[33] T. Matsumoto, S. Maeda, H. Dang, T. Uchida, K. Ota, Y. Hirano, H. Sayama, T.
Iwamatsu, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, and T. Nishimura, “Novel SOI wafer engineering using low stress and high mobility CMOSFET with
37
<100>-channel for embedded RF/Analog applications,” IEDM Tech. Dig., pp.663-666, December 2002.
[34] A. Steegen, M. Stucchi, A. Lauwers, and K. Maex, “Silicide induced pattern density and orientation dependent transconductance in MOS transistors”, IEDM Tech. Dig., pp.497-500, December 1999.
[35] S. Maikap, M. H. Liao, F. Yuan, M. H. Lee, C. Huang, S. T. Chang, and C. W.
Liu, ”Package-strain-enhanced device and circuit performance”, IEDM Tech. Dig., pp.233-236, December 2004.
[36] B. M. Haugerud, L. A. Bosworth, and R. E. Belford, “Mechanically induced strain enhancement of metal--oxide--semiconductor field effect transistors”, J. Appl.
phys., Vol.94, pp.4102-4107, 2003
[37] K. Rim, J. Chu, H. Chen, K.A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and H.-S. Wong, “Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs”, VLSI Symp. Tech. Dig., pp.98-99, 2002
[38] M.D.Giles, M.Armstrong, C.Auth, S.M.Cea, T.Ghani, T.Hoffmann, R.Kotlyar, P.Matagne, K.Mistry, R.Nagisetty, B.Obradovic, R.Shaheed, L.Shifren, M.Stettler, S.Tyagi, X.Wang, C.Weber, K.Zawadzki, “Understanding Stress Enhanced Performance in Intel 90nm CMOS Technology”, VLSI Symp. Tech. Dig., pp.118-119, 2004
[39] C. W. Leitz, M. T. Currie, M. L. Lee, Z.-Y. Cheng, D. A. Antoniadis and E. A.
Fitzgerald, “Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal–oxide–semiconductor field-effect transistors”, J. Appl. phys., Vol.92, pp.3745-3751, 2002
[40] M. V. Fischetti, Z. Ren , P. M. Solomon, M. Yang, and K. Rim, “Six-band k·p
38
calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness”, J. Appl. phys., Vol.94, pp.1079-1095, 2003
[41] S. E. Thompson, G. Sun, K. Wu, J. Kim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs”, IEDM Tech. Dig., pp.221-224, December 2004.
[42] J. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M.
Lin, “Band offset induced threshold variation in strained-Si nMOSFETs”, IEEE Electron Device Lett., Vol. 24, pp.568-570, September 2003.
[43] Chenming Hu, “DEVICE CHALLENGES AND OPPORTUNITIES”, VLSI Symp.
Tech. Dig., pp.4-5, 2004
[44] K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P.
Ronsheim, M. Ieong, A. Grill, H.-S. P. Wong, “Strained Si NMOSFETs for High Performance CMOS Technology”, VLSI Symp. Tech. Dig., pp.59-60, 2001
[45] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi,
“The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling”, VLSI Symp. Tech. Dig., pp.73-74, 1999
[46] Shigeo Ogawa, Masakazu Shimaya, and Noboru Shiono, “Interface trape generation at ultrathin SiO2(4-6nm) interfaces during negative-bias temperature aging”, J. Appl. Phys., Vol.77, pp.1137-1148, 1995.
[47] C Svensson, “The Physics of SiO2 and its Interface”, edited by S. T. Pantelides (Pergamon, New York, 1978) p.328
[48] Dieter K. Schroder and Jeff A. Babcock, “Negative bias temperature instability:
Road to cross in deep submicron silicon semiconductor manufacturing”, J. Appl.
Phys., Vol.94, pp.1-18, 2003.
[49] Kjell O. Jeppson and Christer M. Svensson, “Negative bias stress of MOS devices
39
at high electric fields and degradation of MNOS devices”, J. Appl. Phys., Vol.48, p.2004, 1997.
[50] M. Alam, B. Weir and P. Silverman, “The prospect of using thin oxides for silicon nanotransistors”, in proc., Int. Workshop on Gate Insulator, p.10, 2001
[51] S. Mahapatra, M. A. Alam, P. B. Kumar, T. R. Dalei, and D. Saha, “Mechanism of negative bias temperature instability in CMOS devices: Degradation, recovery and impact of nitrogen”, IEDM Tech. Dig., pp.105-108, December 2004.
[52] G. Chen, K. Y. Chuah, M. F. Li, Daniel SH Chan, C. H. Ang, J. Z. Zheng, Y. Jin and D. L. Kwong, “Dynamic NBTI of PMOS transistors and its impact on device lifetime”, Reliability Physics Symposium Proceedings 2003, pp.196-202
[53] Y. Mitani, “Influence of nitrogen in ultra-thin SiON on negative bias temperature instability under AC stress”, IEDM Tech. Dig., pp.117-120, December 2004.
40
Control
sample
SiN 100nm sample
SiN 300nm sample
Passivation Layer
(Capping Layer) TEOS 300nm SiN 100nm + TEOS 300nm
SiN 300nm + TEOS 300nm
Table 2.1 Split table of capping layer structure and thickness
Passivation Voltage B/A
0V 0.29 Control
+1V 0.32 0V 0.27 SiN 100nm
+1V 0.29 0V 0.29 SiN 300nm
+1V 0.33
Table 4.1 B/A ratio of devices with different capping layers, at different passivation voltages during DNBTI stress
41
Fig. 2.1 Schematic cross section of the local strained channel PMOSFET
Fig. 2.2 TEM micrographs of device with channel length 0.55 µm
SiN
Source Drain
TEOS
Gate
42
Fig. 2.3 Configuration for (a) gate-to-substrate, (b) gate-to-channel capacitance measurements
Fig. 2.4 Bias configuration of NBTI stressing
n-substrate
p+ p+
p+
Gate
n-substrate
p+ p+
p+
Gate
G G
B B S/D
S/D
(a) (b)
n-substrate p+
Source
p+
Drain p+
Gate VG<0
43
Fig. 2.5 Measurement setup in our charge pumping experiment Switch
HP 4156
GPIB n-substrate
p+
Source
p+
Drain p+
Gate
h+ e
-HP 81110A Pulse Generator
44
CMOS Performance Impact Direction of
Strain Change* NMOS PMOS
X Improve Degrade
Y Improve Improve
Z Degrade Improve
* Strain change = Increased tensile or decreased compressive strain
Fig. 3.1 Schematic illustration for 3D process-induced strain components [43].
Drain
Gate
Ex Ey Ez
Source
Gate Silicide
Process-induced Strain
45 (a)
(b)
(c)
Fig. 3.2 (a) Splitting of 6-fold degenerate conduction band in unstrained and biaxial tensile strained Si inversion layers [44]. (b) Schematic diagram of the valence bands in unstrained and strained Si layers [40]. (c) Splitting of light hole band and heavy hole band with biaxial and uniaxial strains in low electric field (solid line) and high electric field (dash line) [41].
∆6 ∆4
Low Field High Field Low Field High Field Unstrain Strain
Biaxial Strain Uniaxial Strain
46
Fig. 3.3 Cumulative probability distribution of sheet resistance of poly-Si and poly-SiGe films. Both with thickness of 150nm, implanted with B implant (dose 3e15cm-2, 8KeV) and anneal at 900°C 30sec.
Sheet Resistance (Ω/sq)
100 200 300 400 500 600
Cumulative Probability (%)
10 30 50 70 90
Poly-Si Gate
Poly-SiGe Gate
47
Fig. 3.4 Output characteristics of devices with poly-Si and poly-SiGe gates at 25°C and VG -Vth= 0 ~ -2 V, step= -0.4 V, W/L= 10µm/1µm.
Drain Voltage (V)
-2.0 -1.5
-1.0 -0.5
0.0
Drain Current ( µA/ µm)
-160 -140 -120 -100 -80 -60 -40 -20 0
Poly-SiGe Gate
Poly-Si Gate
48
Fig. 3.5 Capacitance of devices with poly-Si and poly-SiGe gates. (W/L= 50µm/50µm)
Gate Voltage (V)
-2 -1 0 1 2
Capacitance ( µF/cm
2)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Poly-Si Gate Poly-SiGe Gate
49
Fig. 3.6 Comparison of hole mobility among different gate materials measured by split-CV method.
Effective Field (MV/cm)
0.0 0.2 0.4 0.6 0.8 1.0
Mobility (cm
2/Vs)
0 50 100 150 200 250
Poly-Si gate
Poly-SiGe gate
Universial mobility
50 (a)
(b)
Fig. 3.7 Output characteristics of different capping layers at (a) 25°C (b) 125°C and VG-Vth= 0 ~ -2 V, step= -0.4 V, W/L=10 µm/0.55µm.
Drain Current ( µA/ µm)
-160
51 (a)
(b)
Fig. 3.8 Subthreshold characteristics of devices with different capping layers at (a)25°C (b)125°C and VD= -0.05 V, -2 V, W/L= 10µm/0.55µm.
52 (a)
(b)
Fig. 3.9 Transconductance for devices with different capping layers at (a)25°C (b)125°C and VD= -0.05 V, W/L= 10µm/0.55µm.
53
Fig. 3.10 Measured CV profile for devices with different capping layers at 25°C, W/L= 50µm/50µm.
Voltage (V)
-2 -1 0 1 2
Capacitance ( µF/cm
2)
0.0 0.2 0.4 0.6 0.8 1.0
Control
SiN 100nm
SiN 300nm
54 (a)
(b)
Fig. 3.11 Saturation current (VD= -2V, VG -Vth= -2V) enhancement of different SiN thickness as a function of channel length at (a) 25°C (b) 125°C
Fig. 3.11 Saturation current (VD= -2V, VG -Vth= -2V) enhancement of different SiN thickness as a function of channel length at (a) 25°C (b) 125°C