Chapter 3 Electrical Characteristics of Locally Strained PMOSFETs with Poly-SiGe
3.4 Effects of the Strain
The stress from PE-SiN layer was first examined by probing blanket monitor
sample deposited on Si wafers. We confirmed that the stress is compressive and
increases monotonically with increasing thickness. The stress is around –95 MPa for
100 nm SiN. Figures 3.7(a) and 3.7(b) show the output characteristics of PMOSFETs
with the identical geometry at different temperatures. Saturation current increases
monotonically with increasing capping layer thickness. Figures 3.8 (a) and (b) illustrate
18
the Id-Vg characteristics at different temperatures. The transconductance of the devices
exhibits similar trends, as shown in Figs. 3.9 (a) and (b). It should be noted that, in Fig.
3.10, there is no significant difference of the capacitance between unstrained and
strained channel devices. From these results it is inferred that the holes mobility is
improved by SiN capping layer.
Figs. 3.11 (a) and (b) show the percentage increase of the saturation current of the SiN-capping relative to the control devices as a function of channel lengths at 25°C and
125°C, respectively. The enhancement is less pronounced at high temperature owing to
the enhanced phone scattering rate. The mobility enhancement is more significant as
channel length is scaled down. Subthreshold swing of the devices seems not to be
affected by the induced strain, as shown in Figs. 3.12 (a) and (b), even as operated at a raised temperature (125°C).
Figs. 3.13 (a) and (b) show the threshold voltage as a function of channel length.
Fig. 3.14 illustrates the changes in threshold voltage for devices with SiN layer capping relative to that of control devices. For long channel devices (e.g., L > 2 µm), a nearly
constant shift is observed in Fig. 3.14. This phenomenon could be explained by the
reduction in the interface trap density extracted from charge pumping measurements, as
shown in Fig. 3.15. Since the he precursors for SiN deposition are SiH4 and NH3, a large
19
amount of hydrogen species can be introduced during processing and passivate the
interface states. As also can be seen in the figure, the amount of change in threshold
voltage increases with decreasing channel length, especially as channel length is scaled below 1 µm. Such phenomenon is presumably caused by the splitting of valence band
edges by the compressive strain that increases with decreasing channel length.
20
Chapter 4
Effects of SiN Capping on NBTI of PMOSFETs
4.1 Static and Dynamic NBTI
4.1.1 Brief Review of NBTI Mechanisms
For the aggressive scaling of CMOS technologies, an ultra thin gate oxide is
essential to achieve high drive current under lower power operation. The integrity and
reliability of such a thin gate oxide are therefore crucial for ULSI manufacturing.
Recently, negative-bias-temperature instability (NBTI) has been identified as one of the
major reliability concerns for deep sub-micron PMOSFETs [45]. It was observed that a
large number of interface states and positive fixed charges were generated during
negative-bias-temperature stressing (NBTS), resulting in a negative shift in threshold
voltage showing a power-law dependence on stress time:
b
th At
∆V = (4-1)
This phenomenon becomes more significant as gate oxide is scaled down, and may
even become the limiting factor for deep sub-micron p-channel devices. The shift in
threshold voltage and degradation in transconductance have been suggested to be due to
the interfacial electrochemical reactions related to the holes from the channel inversion
21
layer. The exponential value of the power law equation is around 0.25, which could be
explained by the diffusion-controlled electrochemical reactions. Based on the t0.25-like
time evolution, a generalized reaction-diffusion model for interfacial charge formation
based on the trivalent silicon and its hydrogen compounds was proposed [46].
In the Svensson model [47], an interface trap is a trivalent silicon atom with an
unsaturated valence electron (dangling bond) at the Si-SiO2 interface. It is denoted by
Si≡ iSi and acts as an active interface trap. A post-metal-anneal in a forming gas
(typically 10% H2 in N2 ambient) is widely used to passivate the interface dangling
bonds, and introduces a lot of hydrogen-terminated trivalent Si bonds which are
electrically inactive at the actual interface. If the terminated hydrogen is released from
the Si≡ −Si H bond by some dissociation mechanism, the remaining interface
trivalent silicon (dangling bond) is restored as an active interface trap. Various
mechanisms have been proposed for the dissociation process.
High electric fields can dissociate the silicon-hydrogen bond, according to the
model [48]
0
3 3
Si ≡SiH →Si ≡Sii+H , (4-2)
where H0 is a neutral interstitial hydrogen atom or atomic hydrogen. Recent
first-principle calculations show that the positively charged hydrogen or proton H+ is the
22
only stable charge state of hydrogen at the interface, and that H+ reacts directly with the
SiH to form an interface trap, according to the reaction [47]:
3 3 2
Si ≡SiH+H+ →Si ≡Sii+H . (4-3)
The SiH is polarized in this model such that the mobile positive H+ migrates
towards the negatively charged dipole region in the SiH molecule. The H+ atom then
reacts with the H- to form H2, leaving behind a positively charges Si dangling bond.
A different model considers the interaction of SiH with “hot holes” or holes near or
at the Si/SiO2 interface [46]. Dissociation involving holes is given by
3 3
Si ≡SiH+h+ →Si ≡Sii+H+. (4-4)
Fig. 4.1 is a schematic view of reaction-diffusion model for Nit generation.
The fixed charge (Qf) also contributes to threshold voltage shift near the SiO2/Si
interface. Qf is a by-product of trivalent Si defect in the oxide, generated with the
reaction
0
3 3
O ≡SiH+h+ →O ≡Si++H (4-5)
As discussed in Ref. 46, the interface trap density (Nit) and fixed oxide charge
density (Nf) are shown to increase as:
23
here C and C’ are appropriate constant values, Eox is electric field in the oxide, Tox
is oxide thickness and aging time t. Ogawa et al. [46] found that the generation of fixed
oxide charges is independent of oxide thickness, but is inversely proportional to oxide
thickness for interface trap generation. This suggests that NBTI is worse for thinner
oxide, but this phenomenon is not always observed and highly dependent on the process
conditions.
The stable interface traps are only formed if by-product species, X, diffuses away
from the interface into the oxide bulk.
diffusion
interface bulk
X ⎯⎯⎯⎯→X (4-8)
while “X” could be H-related species.
As proved by Jeppson and Svensson [49], the observed t0.25 behavior of the
interface trap generation suggests the generation process is diffusion controlled. Nit
buildup equals the total number of released H species. Hole-assisted reaction breaks
interfacial SiH bonds, resulting in Nit generation:
n
it N X
∆N = (D t)S , (4-9)
where Dx is the diffusion coefficient of X in the oxide, time exponent n depends on
the type of H species trapped and released in the oxide bulk [50].
The model that has often been invoked to explain the t0.25 dependence of the trap
24
generation rates is only partially correct [46]. In fact, there may exist six regimes of the
reaction-diffusion model for Nit generation [51] as shown in Fig. 4.2. During the early
stress stage, the generation of interface states and hydrogen species is limited by the
dissociation rate (regime1, Nit ~ t1). Then, the process enters the quasi-equilibrium
regime (regime2, Nit ~ t0) immediately. After some stress time, the transport of
hydrogen species limits the dissociation process (regime3, Nit ~ t0.25). However, the
reaction-controlled regime could directly merge into the diffusion-controlled regime.
The rate of ΔNit changes after H diffusion front reaches the SiO2/poly interface. Either
H absorption into poly ensures faster H removal and higher rate of ΔNit (regime4) or H
reflection from poly would result in ΔNit saturation (regime5). Finally, ΔNit should
eventually saturate when all SiH bonds are broken (regime6).
4.1.2 Dynamic NBTI
The conventional NBTI based on static experimental data. During normal
operations of digital circuits, the applied bias to the gate of PMOSFETs in a CMOS
inverter is switched between “high” and “low” voltages. During “low” phase of
PMOSFETs applied bias, the “electric passivation” effect may effectively reduce the
interface traps generated during the “high” phase. The dynamic NBTI (DNBTI) effect
greatly prolongs the lifetime of PMOSFETs operating in a digital circuit, while the
25
conventional static NBTI measurement underestimates the PMOSFET lifetime.
Furthermore, the DNBTI effect is dependent on temperature and gate oxide thickness
[52]. A physical model is proposed for DNBTI that involves the interaction between
hydrogen and silicon dangling bonds [53]. According to this reaction-diffusion theory,
the Δ Vth is attributed to the creation of interface traps as a consequence of
dissociation of Si-H bonds, and subsequent diffusion of the released hydrogen species
towards the gate electrode. In the recovery process, released hydrogen re-passivates Si
dangling bonds [53]. The ΔVth recovery progresses in accordance with the power law
dependency as follows:
n
V =A-B tth
∆ ⋅ , (4-10)
where B/A ratio indicates the ratio of a recovery reaction coefficient to ΔVth just
after NBT stress. This finding has significant impact on the determination of maximum
operation voltage as well as lifetime for future scaling of CMOS devices. Therefore, it is
critically important to investigate NBTI under such dynamic stress conditions.
26 4.2 Experimental Results and Discussion
4.2.1 Static NBTI Characterization
Figure 4.3 shows the results of NBTI stress performed at 25°C with gate overdrive
bias of –3.9 V (VGO = VG - Vth). As can be seen in Fig. 4.3(a), larger change in threshold
voltage shift, ΔVth, is observed in the device with SiN capping layer. The shift curves
show a fractional power-law dependence on time, and the exponential values with
SiN-capping sample are larger than the control sample. According to the classical
reaction-diffusion model, such dependence implies that NBTI is controlled by the
diffusion. From Fig. 4.3(b), the maximum value of transconductance, Gmmax, degrades
gravely in the device with SiN layer. The increase of interface trap density, ΔNit, for
devices with SiN capping layer are larger than that of control case, as shown in Fig.
4.3(c). The exponential value ofΔNit in power-law relationship is higher for devices
with SiN capping. Similar phenomenon is also observed for the generation of oxide
trapped charges, ΔNot, as shown in Fig. 4.3(d).
The above results clearly indicate that the use of PECVD SiN capping may result
in degraded NBTI. Two plausible origins are postulated to explain the worsen NBTI: (1)
Higher density of Si-H bonds at the oxide/Si interface, since the SiN layer contains a
27
large amount of hydrogen species because of the use of SiH4 and NH3 precursor gases;
(2) Higher strain energy stored in the channel. The energy may help trigger the
electrochemical reactions at the interface. This is evidenced by the higher exponent
value of the power-time dependence for devices with SiN capping.
Figure 4.4 shows the results after NBTI stress at 125°C. The trends are similar to
those occurring at 25°C. The devices with SiN-capping have aggravated NBTI issue. It
should be noted that in Fig. 4.4(a), Fig. 4.4(c) and Fig. 4.4(d), nearly saturation inΔVth,
ΔNit andΔNot are observed for the device with SiN capping when the stress time is
longer than 1000 sec. The NBTI is related to the amount of hydrogen species bonded at
the oxide/Si interface, and ∆Nit should eventually saturate when nearly all Si-H bonds
are broken. The disparity between the two splits is postulated to be caused by the local
strain induced in the SiN capping split. The existence of strain weakens the bond
strength of hydrogen species that in turn accelerates the bond-breaking process. Such
phenomenon is not observed in the control devices due to the lack of high strain in the
channel.
Figures 4.5 ~ 4.7 show ΔVth and ΔNit characteristics as a function of time under
different VGO at 25°C for the three splits of samples. ΔVth andΔNit for all cases
increase with increasing stress voltage. The exponential value of ΔVth and ΔNit in
28
power-law relationship are similar under different stress conditions in each split.
Because of ΔNit ∝ Eox1.5, higher VGO can induce larger amount of Nit and degradation.
Figures 4.8 ~ 4.10 illustrate ΔVth and ΔNit evolution under different VGO aging at
125°C for the three splits of samples. The trend for ΔVth at 125°C is similar to the
results at 25°C. However, the exponential value of ΔNit in power-law relationship
decreases with increasing stress bias for the devices with SiN capping. It can be
concluded that larger amounts of SiH bonds are broken by higher stress bias during
early stress aging. Figures 4.11 and 4.12 illustrate the temperature dependence
(Arrehenius plots) of ΔVth, ΔNit andΔNot under 1000 sec stressing. The slope
(activation energy) is larger for the devices with SiN capping.
4.2.2 DNBTI and AC stress
To simulate the switching operation of the device in the CMOS circuits, the gate
voltage during NBTI stress is switched between negative and positive bias for all splits
as shown in Figures 4.13 ~ 4.15. The condition during stress periods was for 125°C,
VGO = –4 V, while that for passivation periods VG was set at several biases. Other
terminals were grounded during the measurement. As can be seen in Figs. 4.13(a),
4.14(a) and 4.15(a), theΔVth, reductions of VG = +1 V during passivation are more
significant than VG = 0 V. We found that the degradation in the stress periods worsens
29
when higher strain is contained in the channel. The trends in interface trap density shift
are similar among the three splits, as shown in Fig. 4.13(b), Fig. 4.14(b) and Fig.
4.15(b), which have weaker dependence on the recover voltage. BecauseΔNit is
proportionate to ΔVth even at different positive biases during DNBT stressing, as
shown in Fig. 4.16(a), Fig. 4.17(a) and Fig. 4.18(a), it can be concluded that ΔVth is
directly affected by ΔNit during entire dynamic stress period. However, it should be
noted that in Fig. 4.16(b), Fig. 4.17(b) and Fig. 4.18(b), the decreases in ΔVth do not
follow the consistent decrease in ΔS, especially for the case with passivation bias VG =
+1 V. It may be due to the electron trapping related to the positive hydrogen charges in
the gate dielectric according to reactions (4-8). The B/A ratio of DNBTI is shown in
Table. 4.1. The recovery reaction coefficients are similar between strained and
unstrained cases.
Furthermore, the frequency dependences of NBT degradation were measured and
shown in Figs. 4.19 to 4.21 with 50% duty cycle. ΔVth and ΔNit are plotted as a
function of frequency, as shown in Fig.4.17. Both ΔVth and ΔNit are strongly
dependent on frequency for devices with SiN capping layer. The results indicate that the
stress under higher AC frequency shows lessΔVth andΔNit degradation. It is due to the
shortened stress time with increased frequency. It results in parts of broken SiH bonds
30
being recovered before entering the next stress state. Interface trap generation would be
contained by increase AC stress frequency and Δ Vth is suppressed indirectly.
Reduction in NBT degradation for strained-channel devices under AC stress is more
significant than the control case, mainly because the amount of broken SiH bonds with
SiN capping layer is larger than the control sample.
31
Chapter 5 Conclusions
5.1 Conclusions
Using poly-SiGe as gate material to fabricate PMOSFETs has numerous
advantages, including reduced gate depletion effect and improved gate sheet resistance.
Compressive PECVD SiN layer could significantly enhance the drive current of PMOS devices at either room or raised operating temperatures (125 °C) due to increase of hole
mobility, as shown in our experiment. The degrees of mobility enhancement are
enlarged as devices geometry is scaled down. Despite this merit, our results also
indicate that the SiN capping may aggravate the NBTI characteristics. A high amount of
hydrogen species contained in the PE-SiN layer as well as the strain energy stored in the
channel may be the culprits for the worsened reliability. The interface trap density
change and threshold voltage shift recover significantly during passivation periods.
We’ve also observed that the strained channel device is influenced strongly by AC stress
frequency.
32
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