Chapter 2 Device Fabrication and Measurement Setup
2.2 Electrical Characterization and Measurement Setup
Electrical characterizations and static NBTI stressing tests were performed using an
HP 4156 system. DNBTI stressing tests were performed using a Keithley 4200 system.
A precision impedance meter, HP4284, was used for C-V measurements.
Temperature-regulated hot chucks were controlled at temperatures ranging from 25°C to
125°C.
Split C-V method was employed to determinate the holes mobility. The electric
field produced by the gate voltage is express as:
0
8
where Qb and Qn are charge densities in depletion layer and inversion layer, respectively.
The parameter η=1/3 for hole mobility. The gate-to-substrate capacitance (Cgb) and
gate-to-channel capacitance (Cgc) were measured using the configurations illustrated in
Fig. 2.3.
The existence of a gate leakage current may affect the accurate measurement of
drain conductance. To solve this problem, we propose some new approaches as
followed. The channel current is simply given by the average of the source and the drain
currents. For surface carrier concentration evaluation, we have adopted a simple
approach that takes drain voltage effect into account [23].
( ) ( ) 1
The fabricated devices were subjected to bias-temperature-stress (BTS) from 25°C
to 125°C. During the BTS, a negative gate bias (-3.5 V~ -4.3 V) was applied, while
drain/source and substrate were all grounded, as schematically shown in Fig. 2.4.
The interface state density was evaluated using the charge pumping method. In the
characterization, square-wave (f = 1MHz) voltage signals were applied to the gate with
a constant pulse amplitude of 1.5 V, and a varying base voltage to tune the surface
condition from inversion to accumulation. Fig. 2.5 shows the configuration of
9
measurement setup used in the charge pumping experiment. A MOSFET with a gate
area of AG gives the charge pumping current as:
cp G it
I =qA fN (2-5)
Interface trap density could be evaluated by using this equation.
Oxide traps cannot respond to the Icp signal at high frequency and are categorized
as slow traps. The mean interface trapped charge contributes only by ψB as surface
potential is roughly equal to 2ψB. A simple and direct way to deduce oxide trap density
(Not) is to calculate the difference between the measured Δ Vth and the term
contributed by ΔNit from charge pumping results, using the following formula:
, ( ( ))
( )
Don Acc
ot it s B
th
ox ox
q N q N T
V T C C
ψ φ
∆ ∆ −
∆ = − − (2-6)
Therefore, ΔNot during stress cab be calculated and easily determined.
10
Chapter 3
Electrical Characteristics of Locally Strained PMOSFETs with Poly-SiGe gate
3.1 Brief Review of Poly-SiGe Gate Technology
Technical challenges emerge as the critical dimensions of semiconductor devices
are scaled down to the deep-submicron regime in a pursuit of higher levels of
integration and performance. The dual-gate process has replaced the conventional
single-gate process for advanced CMOS fabrication. For dual-gate process, boron
penetration through the gate oxide from the p+-doped gate of PMOSFETs becomes a
major concern. In addition, gate-depletion effect due to insufficient dopant activation at
the gate/dielectric interface becomes more significant as gate oxide thickness is scaled
down, and leads to the degradation of the drive current.
To alleviate the above-mentioned problems, poly-SiGe has been proposed as a
promising alternate gate material to replace the conventional poly-Si gate. First, the
dopant activation in poly-SiGe is better than in poly-Si for p-type gate material. Besides,
the p-type poly-SiGe film has lower resistivity, reduced gate-depletion effect, and
suppressed boron penetration, thanks to the higher dopant activation ratio as comparing
11
to poly-Si film. Mechanism of the improved boron activation is presumably caused by
the local strain compensation due to the difference in atomic radii between Si and B
atoms [24].
When p+ poly-Si is substituted by p+ poly-SiGe as the gate material for the PMOS
device, the change in the gate to semiconductor work-function difference, ΔΦms, can
be approximately calculated as the difference in the energy bandgaps between the two
heavily-doped materials, i.e., ∆Φ =ms EGpoly Si− −EGpoly SiGe− . This is due to the fact that the
position of the conduction band edge of the materials remains essentially unchanged
regardless of the Ge incorporation. For high Ge concentration, a significant amount of
stress contained in the poly-SiGe grains results in an extra reduction of the gate
work-function [19]. In order to retain the threshold voltage at the reference value, one
can change ΔΦms by reducing the channel doping. As a result, hole mobility is
enhanced due to reduction of Coulomb scattering centers in the channel region. The
drive current is thus increased. The subthreshold swing could also be reduced due to
decrease in the depletion layer capacitance, leading to an improved Ion/Ioff ratio. The
reduction of the body factor results in weaker threshold voltage dependence on
variations of the substrate potential.
The dopant activation temperature could be reduced owing to the lower melting
12
point of poly-SiGe film, and this is conducive to reducing the process thermal budget.
The poly-SiGe alloy films also have good compatibility with standard CMOS
processing.
3.2 Brief Review of Strained Si Technology
Rapid growth in the study of implementing strained silicon to the channel has been
witnessed in the past several years. Historically, improvements on MOSFET’s
performance have been attained by shrinking device dimensions. However, the practical
benefit of scaling is compromised as physical and economic limits are being approached,
and novel solutions are being sought. The 2003 ITRS roadmap started to schedule the
mobility enhancement factor by stress controls. Strain improves MOSFET drive current
by altering the band structure of the channel and can therefore enhance performance
even at aggressively scaled channel lengths. Bi-axial and uni-axial strained silicon
technologies are promising for enhancement of CMOS performance [25~30]. For the
case of a silicon layer under bi-axial tensile strain, it is mainly implemented by the
lattice mismatch with an underling relaxed SiGe layer. Note that, to avoid the generation
of high amount of dislocations, thickness of the top strained Si layer must be thinner
than the critical thickness that depends on the Ge content of the underlying relaxed SiGe
13
layer. In contrast, uni-axial strain can be engineered by modifying capping layer
deposition [9][31], shallow trench isolation [32][33], source/drain material [6],
silicidation [34], packing process [35], and so on. Furthermore, the behaviors of carrier
mobility under uni-axial strain depend on the strength of the strain and the orientation.
Electron and hole mobilities respond to the complex three-dimensional mechanical
stress in different, even opposite ways, as shown in Fig. 3.1.
Several different behaviors caused by bi-axial and uni-axial stress were reported,
such as the drop of mobility enhancement at high electric field and threshold voltage
shift. Bi-axial strain improves electron transport more than hole transport, and vice
versa for the perpendicular uni-axial strain. Uni-axial strain can be applied arbitrarily in
any direction relative to the carrier transport direction. Enhancements of carrier mobility
under bi-axial and uni-axial strain were induced by different factors and mechanisms.
For NMOSFETs, recent reports and theoretical calculations indicate that
strained-Si under bi-axial or uni-axial tension should exhibit a higher mobility than bulk
Si. The differences in electronic conduction due to bi-axial and uni-axial strain can be
explained by examining the splitting of the degeneracy at the conduction band edges.
The biaxial tensile strain induces splitting of degeneracy in the triangular potential well
of the MOS inversion layer. This splits the six-fold degenerate Si conduction band into a
14
two-fold (Δ2) and a four-fold (Δ4) branches. The energy of sub-band in four-fold
valley is lower than that in two-fold valley under uni-axial tensile stress, opposing to
what occurs in the case of bi-axial tensile stress. The energy difference (ΔE) between
Δ2 and Δ4 sub-bands determines the total population of the bands. The enhancement
of uni-axial and bi-axial strained-Si caused by the splitting of conduction band can
suppress inter-valley phonon scattering [36]. At high electric field, even in bulk Si
NMOSFETs, the six-fold degeneracy is broken near the Si/SiO2 interface by the
confinement of carrier at surface (as shown in Fig. 3.2(a)). The two-fold sub-band is
also preferentially occupied at high gate bias. Most inversion electrons are expected to
reside in two-fold sub-band even for devices fabricated on bulk Si. In contrast, bi-axial
tension causes nearly 100% of inversion electrons to occupy the two-fold sub-band at
all gate biases. Note that the enhancement of bi-axial tension at high electrical field,
albeit not as high as that at low field, is still very significant [37].
To quantify the mobility enhancement of holes, changes in the scattering and
effective mass depend on the altered valence band caused by the strain. For both
bi-axial tensile and longitudinal uni-axial compressive stresses, the effective mass is
nearly constant over the surface energy range of a few kT below the valence band in
contrast to un-strained case. The constant effective mass results since strain removes the
15
degeneracy and reduces the band-to-band coupling. From full-band Monte Carlo
simulation [38], uni-axial compressive strained MOSFETs may have lighter in-plane
effective mass thus improve hole mobility. For bi-axial tensile stress, the effective mass
is heavier than un-strained case. The hole mobility enhancement is only possible
through the reduction of inter-valley scattering [39]. This effect becomes significant
only when the strain level is high enough (e.g., Ge > 20 %). Reducing the intra-band
acoustic scattering by altering the light- and heavy-hole band density-of-states is
negligible for uni-axial strain in Si, even at several hundreds of mega-pascal. On the
other hand, the energy difference ΔEs (as shown in Fig. 3.2) between light-hole band
and heavy-hole band was split by uni-axial stress at gamma-point (k=0) and reduces the
optical phonon scattering (as shown in Fig. 3.2(b)). Significant scattering reduction
requires ΔEs > 60meV (optical phonon energy in Si) [13].
Hole mobility at high vertical field with uni-axial compressive and biaxial tensile
stresses would have different behaviors. Splitting of light- to heavy-hold band caused by
uni-axial and biaxial stresses has no significant difference without considering surface
quantization confinement. However, the splitting of light- and heavy-hole bands caused
by bi-axial tensile stress would be nullified at high electric field due to surface
confinement [40]. In contrast, hole mobility enhancement under uni-axial compressive
16
strain is not nullified by surface confinement, which represents a major advantage for
MOSFETs operating at high electric fields. The splitting magnitude of the surface
confinement depends on the relative magnitude of the stress altered light and heavy hole
out-of-plane effective masses. Recent reports [41] showed the interesting result that the
out-of-plane effective mass of light hole is heavier than heavy hole for uni-axial stress
and causes the light to heavy hole band splitting to increase. On the contrary, for
bi-axial stress the previously-reported out-of-plane effective mass of light hole is lighter
than heavy hole and causes the band splitting to be reduced. This is why the bi-axial
stress degrades hole mobility enhancement at high vertical electric fields (as shown in
Fig. 3.2(c)).
The threshold voltage shift caused by bi-axial tensile stress is larger than the case
with uni-axial tensile strain has been reported for NMOSFETs [42]. For PMOSFETs,
larger shift of light-hole band edge under bi-axial tensile strain leads to larger shift in
Vth than the case with uni-axial compressive strain [41].
3.3 Electrical Characteristics of Poly-SiGe Gate Devices
Figure 3.3 shows the cumulative probability distribution of sheet resistance for
poly-Si and poly-SiGe (Ge: 20%) gates with nominally identical implant and annealing
17
conditions. Thickness of the films is around 150nm. As can be seen in the figure, the
sheet resistance becomes lower as Ge incorporated, owing to the higher dopant
activation [19]. This results in improved output characteristics for the device with
poly-SiGe gate, as shown in Fig. 3.4. Figure 3.5 compares the C-V characteristics of the
devices. This further confirms the fact that poly-SiGe gate could effectively suppress
poly-depletion effect. Fig. 3.6 shows the mobility as a function of effective vertical
electric field. PMOSFETs using poly-SiGe as gate material have no significant effect on
holes mobility with the nominally identical channel doping profile. However, lowering
in channel doping to compensate the Vth shift due to work-function difference in
poly-SiGe-gated devices may result in improved low-field mobility.
3.4 Effects of the Strain
The stress from PE-SiN layer was first examined by probing blanket monitor
sample deposited on Si wafers. We confirmed that the stress is compressive and
increases monotonically with increasing thickness. The stress is around –95 MPa for
100 nm SiN. Figures 3.7(a) and 3.7(b) show the output characteristics of PMOSFETs
with the identical geometry at different temperatures. Saturation current increases
monotonically with increasing capping layer thickness. Figures 3.8 (a) and (b) illustrate
18
the Id-Vg characteristics at different temperatures. The transconductance of the devices
exhibits similar trends, as shown in Figs. 3.9 (a) and (b). It should be noted that, in Fig.
3.10, there is no significant difference of the capacitance between unstrained and
strained channel devices. From these results it is inferred that the holes mobility is
improved by SiN capping layer.
Figs. 3.11 (a) and (b) show the percentage increase of the saturation current of the SiN-capping relative to the control devices as a function of channel lengths at 25°C and
125°C, respectively. The enhancement is less pronounced at high temperature owing to
the enhanced phone scattering rate. The mobility enhancement is more significant as
channel length is scaled down. Subthreshold swing of the devices seems not to be
affected by the induced strain, as shown in Figs. 3.12 (a) and (b), even as operated at a raised temperature (125°C).
Figs. 3.13 (a) and (b) show the threshold voltage as a function of channel length.
Fig. 3.14 illustrates the changes in threshold voltage for devices with SiN layer capping relative to that of control devices. For long channel devices (e.g., L > 2 µm), a nearly
constant shift is observed in Fig. 3.14. This phenomenon could be explained by the
reduction in the interface trap density extracted from charge pumping measurements, as
shown in Fig. 3.15. Since the he precursors for SiN deposition are SiH4 and NH3, a large
19
amount of hydrogen species can be introduced during processing and passivate the
interface states. As also can be seen in the figure, the amount of change in threshold
voltage increases with decreasing channel length, especially as channel length is scaled below 1 µm. Such phenomenon is presumably caused by the splitting of valence band
edges by the compressive strain that increases with decreasing channel length.
20
Chapter 4
Effects of SiN Capping on NBTI of PMOSFETs
4.1 Static and Dynamic NBTI
4.1.1 Brief Review of NBTI Mechanisms
For the aggressive scaling of CMOS technologies, an ultra thin gate oxide is
essential to achieve high drive current under lower power operation. The integrity and
reliability of such a thin gate oxide are therefore crucial for ULSI manufacturing.
Recently, negative-bias-temperature instability (NBTI) has been identified as one of the
major reliability concerns for deep sub-micron PMOSFETs [45]. It was observed that a
large number of interface states and positive fixed charges were generated during
negative-bias-temperature stressing (NBTS), resulting in a negative shift in threshold
voltage showing a power-law dependence on stress time:
b
th At
∆V = (4-1)
This phenomenon becomes more significant as gate oxide is scaled down, and may
even become the limiting factor for deep sub-micron p-channel devices. The shift in
threshold voltage and degradation in transconductance have been suggested to be due to
the interfacial electrochemical reactions related to the holes from the channel inversion
21
layer. The exponential value of the power law equation is around 0.25, which could be
explained by the diffusion-controlled electrochemical reactions. Based on the t0.25-like
time evolution, a generalized reaction-diffusion model for interfacial charge formation
based on the trivalent silicon and its hydrogen compounds was proposed [46].
In the Svensson model [47], an interface trap is a trivalent silicon atom with an
unsaturated valence electron (dangling bond) at the Si-SiO2 interface. It is denoted by
Si≡ iSi and acts as an active interface trap. A post-metal-anneal in a forming gas
(typically 10% H2 in N2 ambient) is widely used to passivate the interface dangling
bonds, and introduces a lot of hydrogen-terminated trivalent Si bonds which are
electrically inactive at the actual interface. If the terminated hydrogen is released from
the Si≡ −Si H bond by some dissociation mechanism, the remaining interface
trivalent silicon (dangling bond) is restored as an active interface trap. Various
mechanisms have been proposed for the dissociation process.
High electric fields can dissociate the silicon-hydrogen bond, according to the
model [48]
0
3 3
Si ≡SiH →Si ≡Sii+H , (4-2)
where H0 is a neutral interstitial hydrogen atom or atomic hydrogen. Recent
first-principle calculations show that the positively charged hydrogen or proton H+ is the
22
only stable charge state of hydrogen at the interface, and that H+ reacts directly with the
SiH to form an interface trap, according to the reaction [47]:
3 3 2
Si ≡SiH+H+ →Si ≡Sii+H . (4-3)
The SiH is polarized in this model such that the mobile positive H+ migrates
towards the negatively charged dipole region in the SiH molecule. The H+ atom then
reacts with the H- to form H2, leaving behind a positively charges Si dangling bond.
A different model considers the interaction of SiH with “hot holes” or holes near or
at the Si/SiO2 interface [46]. Dissociation involving holes is given by
3 3
Si ≡SiH+h+ →Si ≡Sii+H+. (4-4)
Fig. 4.1 is a schematic view of reaction-diffusion model for Nit generation.
The fixed charge (Qf) also contributes to threshold voltage shift near the SiO2/Si
interface. Qf is a by-product of trivalent Si defect in the oxide, generated with the
reaction
0
3 3
O ≡SiH+h+ →O ≡Si++H (4-5)
As discussed in Ref. 46, the interface trap density (Nit) and fixed oxide charge
density (Nf) are shown to increase as:
23
here C and C’ are appropriate constant values, Eox is electric field in the oxide, Tox
is oxide thickness and aging time t. Ogawa et al. [46] found that the generation of fixed
oxide charges is independent of oxide thickness, but is inversely proportional to oxide
thickness for interface trap generation. This suggests that NBTI is worse for thinner
oxide, but this phenomenon is not always observed and highly dependent on the process
conditions.
The stable interface traps are only formed if by-product species, X, diffuses away
from the interface into the oxide bulk.
diffusion
interface bulk
X ⎯⎯⎯⎯→X (4-8)
while “X” could be H-related species.
As proved by Jeppson and Svensson [49], the observed t0.25 behavior of the
interface trap generation suggests the generation process is diffusion controlled. Nit
buildup equals the total number of released H species. Hole-assisted reaction breaks
interfacial SiH bonds, resulting in Nit generation:
n
it N X
∆N = (D t)S , (4-9)
where Dx is the diffusion coefficient of X in the oxide, time exponent n depends on
the type of H species trapped and released in the oxide bulk [50].
The model that has often been invoked to explain the t0.25 dependence of the trap
24
generation rates is only partially correct [46]. In fact, there may exist six regimes of the
reaction-diffusion model for Nit generation [51] as shown in Fig. 4.2. During the early
reaction-diffusion model for Nit generation [51] as shown in Fig. 4.2. During the early