Conclusions

Using poly-SiGe as gate material to fabricate PMOSFETs has numerous

advantages, including reduced gate depletion effect and improved gate sheet resistance.

Compressive PECVD SiN layer could significantly enhance the drive current of PMOS devices at either room or raised operating temperatures (125 °C) due to increase of hole

mobility, as shown in our experiment. The degrees of mobility enhancement are

enlarged as devices geometry is scaled down. Despite this merit, our results also

indicate that the SiN capping may aggravate the NBTI characteristics. A high amount of

hydrogen species contained in the PE-SiN layer as well as the strain energy stored in the

channel may be the culprits for the worsened reliability. The interface trap density

change and threshold voltage shift recover significantly during passivation periods.

We’ve also observed that the strained channel device is influenced strongly by AC stress

frequency.

32

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40

Control

sample

SiN 100nm sample

SiN 300nm sample

Passivation Layer

(Capping Layer) TEOS 300nm SiN 100nm + TEOS 300nm

SiN 300nm + TEOS 300nm

Table 2.1 Split table of capping layer structure and thickness

Passivation Voltage B/A

0V 0.29 Control

+1V 0.32 0V 0.27 SiN 100nm

+1V 0.29 0V 0.29 SiN 300nm

+1V 0.33

Table 4.1 B/A ratio of devices with different capping layers, at different passivation voltages during DNBTI stress

41

Fig. 2.1 Schematic cross section of the local strained channel PMOSFET

Fig. 2.2 TEM micrographs of device with channel length 0.55 µm

SiN

Source Drain

TEOS

Gate

42

Fig. 2.3 Configuration for (a) gate-to-substrate, (b) gate-to-channel capacitance measurements

Fig. 2.4 Bias configuration of NBTI stressing

n-substrate

p+ p+

p+

Gate

n-substrate

p+ p+

p+

Gate

G G

B B S/D

S/D

(a) (b)

n-substrate p+

Source

p+

Drain p+

Gate VG<0

43

Fig. 2.5 Measurement setup in our charge pumping experiment Switch

HP 4156

GPIB n-substrate

p+

Source

p+

Drain p+

Gate

h⁺ e

-HP 81110A Pulse Generator

44

CMOS Performance Impact Direction of

Strain Change* NMOS PMOS

X Improve Degrade

Y Improve Improve

Z Degrade Improve

* Strain change = Increased tensile or decreased compressive strain

Fig. 3.1 Schematic illustration for 3D process-induced strain components [43].

Drain

Gate

E_x E_y Ez

Source

Gate Silicide

Process-induced Strain

45 (a)

(b)

(c)

Fig. 3.2 (a) Splitting of 6-fold degenerate conduction band in unstrained and biaxial tensile strained Si inversion layers [44]. (b) Schematic diagram of the valence bands in unstrained and strained Si layers [40]. (c) Splitting of light hole band and heavy hole band with biaxial and uniaxial strains in low electric field (solid line) and high electric field (dash line) [41].

∆6 ∆₄

Low Field High Field Low Field High Field Unstrain Strain

Biaxial Strain Uniaxial Strain

46

Fig. 3.3 Cumulative probability distribution of sheet resistance of poly-Si and poly-SiGe films. Both with thickness of 150nm, implanted with B implant (dose 3e15cm^-2, 8KeV) and anneal at 900°C 30sec.

Sheet Resistance (Ω/sq)

100 200 300 400 500 600

Cumulative Probability (%)

10 30 50 70 90

Poly-Si Gate

Poly-SiGe Gate

47

Fig. 3.4 Output characteristics of devices with poly-Si and poly-SiGe gates at 25°C and V_G -V_th= 0 ~ -2 V, step= -0.4 V, W/L= 10µm/1µm.

Drain Voltage (V)

-2.0 -1.5

-1.0 -0.5

0.0

Drain Current ( µA/ µm)

-160 -140 -120 -100 -80 -60 -40 -20 0

Poly-SiGe Gate

Poly-Si Gate

48

Fig. 3.5 Capacitance of devices with poly-Si and poly-SiGe gates. (W/L= 50µm/50µm)

Gate Voltage (V)

-2 -1 0 1 2

Capacitance ( µF/cm

2

)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Poly-Si Gate Poly-SiGe Gate

49

Fig. 3.6 Comparison of hole mobility among different gate materials measured by split-CV method.

Effective Field (MV/cm)

0.0 0.2 0.4 0.6 0.8 1.0

Mobility (cm

2

/Vs)

0 50 100 150 200 250

Poly-Si gate

Poly-SiGe gate

Universial mobility

50 (a)

(b)

Fig. 3.7 Output characteristics of different capping layers at (a) 25°C (b) 125°C and V_G-V_th= 0 ~ -2 V, step= -0.4 V, W/L=10 µm/0.55µm.

Drain Current ( µA/ µm)

-160

51 (a)

(b)

Fig. 3.8 Subthreshold characteristics of devices with different capping layers at (a)25°C (b)125°C and VD= -0.05 V, -2 V, W/L= 10µm/0.55µm.

52 (a)

(b)

Fig. 3.9 Transconductance for devices with different capping layers at (a)25°C (b)125°C and VD= -0.05 V, W/L= 10µm/0.55µm.

53

Fig. 3.10 Measured CV profile for devices with different capping layers at 25°C, W/L= 50µm/50µm.

Voltage (V)

-2 -1 0 1 2

Capacitance ( µF/cm

2

)

0.0 0.2 0.4 0.6 0.8 1.0

Control

SiN 100nm

SiN 300nm

54 (a)

(b)

Fig. 3.11 Saturation current (VD= -2V, VG -Vth= -2V) enhancement of different SiN thickness as a function of channel length at (a) 25°C (b) 125°C

Channel Length (µm)

55 (a)

(b)

Fig. 3.12 Subthreshold swing of devices with different capping layers as a function of channel length at (a) 25°C, and (b) 125°C.

Channel Length (µm)

56 (a)

(b)

Fig. 3.13 Threshold voltage of devices with different capping layers as a function of channel length at (a) 25°C, and (b) 125°C.

Channel Length (µm)

57

Fig. 3.14 Changes of threshold voltage for devices with different capping layers as a function of channel length at 25°C.

Channel Length (µm)

0 1 2 3 4 5

∆ Vth (V)

0.04 0.06 0.08 0.10 0.12 0.14

SiN 100nm

SiN 300nm

58

Fig. 3.15 Charge pumping current of devices with different capping layers at 25°C, W/L= 10µm/1µm, pulse amplitude= 1.5V, frequency= 1 MHz.

Peak Voltage (V)

0.0 0.5 1.0 1.5 2.0

Charge Pumping Current (nA)

-0.8

-0.6

-0.4

-0.2

0.0

Control

SiN 100nm

SiN 300nm

59

Fig. 4.1 Schematic view of the field-induced hydrogen species current through the gate oxide during negative bias aging.

Fig. 4.2 Various phases of Nit buildup. 1: reaction-limited, 2: quasi-equilibrium, 3:

diffusion-limited, 4: enhancement due to poly absorption, 5: saturation due to poly reflection, 6: final saturation [51].

VG

60 (a)

(b)

Fig. 4.3 (a) Threshold voltage shift, and (b) Transconductance degradation at 25°C during V_GO = –3.9 V stress aging (W/L= 10µm/0.55µm).

61 (c)

(d)

Fig. 4.3 (c) Interface trap density increasing, and (d) Oxide trap density increase at 25°C during V_GO = –3.9V stress aging (W/L= 10µm/0.55µm).

62 (a)

(b)

Fig. 4.4 (a) Threshold voltage shift, and (b) Transconductance degradation at 125°C during VGO = –3.9V stress aging (W/L= 10µm/0.55µm).

63 (c)

(d)

Fig. 4.4 (c) Interface trap density increase, and (d)oxide trap density increase at 125°C during VGO = –3.9V stress aging (W/L= 10µm/0.55µm).

64 (a)

(b)

Fig. 4.5 (a) Threshold voltage shift, and (b) Interface trap density increase of the control sample at 25°C with different VG stresses (W/L= 10µm/0.55µm).

Stress Time (s)

65 (a)

(b)

Fig. 4.6 (a) Threshold voltage shift, and (b) Interface trap density increase of the device with SiN-capping 100nm sample at 25°C with different VG stresses.

(W/L= 10µm/0.55µm)

66 (a)

(b)

Fig. 4.7 (a) Threshold voltage shift, and (b) Interface trap density increase of the device with 300nm SiN-capping at 25°C with different VG stresses.

(W/L= 10µm/0.55µm)

67 (a)

(b)

Fig. 4.8 (a) Threshold voltage shift,and (b) Interface trap density increaseof the control sample at 125°C with different VG stresses. (W/L= 10µm/0.55µm)

Stress Time (s)

68 (a)

(b)

Fig. 4.9 (a) Threshold voltage shift, and (b) Interface trap density increase of the device with 100nm SiN-capping at 125°C with different V_G stresses.

69 (a)

(b)

Fig. 4.10 (a) Threshold voltage shift, and (b) Interface trap density increase of the device with SiN-capping 300nm sample at 125°C with different VG stresses.

(W/L=10µm/0.55µm)

70

Fig. 4.11 Threshold voltage shift dependence on temperature with different capping layers, estimated by VGO = –3.9V, 1000s stress.

1/kT (eV

^-1

)

28 30 32 34 36 38 40

-∆ V

th

(mV)

1 10 100 1000

Control SiN 100nm SiN 300nm slope=-0.19

slope=-0.195

slope=-0.13

71 (a)

(b)

Fig. 4.12 (a) Interface trap density, and (b) Oxide trap density change dependence on temperature with different capping layers, estimated by VGO = –3.9V, 1000s stress.

72 (a)

(b)

Fig. 4.13 (a) Threshold voltage shift, and (b) Interface trap density change of the control sample during VGO = –4V and different passivation stresses at 125°C. (W/L=

10µm/0.75µm)

Stress Time (s)

0 2000 4000 6000 8000 10000 12000

∆ V

th

(mV)

0 2000 4000 6000 8000 10000 12000

∆ N

it

(10

12

/cm

2

)

73 (a)

(b)

Fig. 4.14 (a) Threshold voltage shift, and (b) Interface trap density change of the device with 100nm SiN-capping 1ayer during V_GO = –4V and different passivation stresses at 125°C. (W/L= 10µm/0.75µm)

Stress Time (s)

0 2000 4000 6000 8000 10000 12000

∆V th (mV)

0 2000 4000 6000 8000 10000 12000

∆N it (1012 /cm2 )

74 (a)

(b)

Fig. 4.15 (a) Threshold voltage shift, and (b) Interface trap density change of the device with 300nm SiN-capping layer during VGO = –4V and different passivation stresses at 125°C. (W/L= 10µm/0.75µm)

Stress Time (s)

0 2000 4000 6000 8000 10000 12000

∆V th (mV)

0 2000 4000 6000 8000 10000 12000

∆N it (1012 /cm2 )

75 (a)

(b)

Fig. 4.16 (a) Interface trap density change, and (b) Subthreshold swing shift dependence on threshold voltage shift of the control sample, during VGO= –4V and different passivation stresses at 125°C. (W/L= 10µm/0.75µm)

∆V_th (mV)

76 (a)

(b)

Fig. 4.17 (a) Interface trap density change, and (b) Subthreshold swing shift dependence on threshold voltage shift of the device with 100nm SiN-capping layer, during V_GO= –4V and different passivation stresses at 125°C. (W/L= 10µm/0.75µm)

∆V_th (mV)

77 (a)

(b)

Fig. 4.18 (a) Interface trap density change, and (b) Subthreshold swing shift dependence on threshold voltage shift of the device with 300nm SiN-capping layer, during VGO= –4V and different passivation stresses at 125°C. (W/L= 10µm/0.75µm)

∆V_th (mV)

78 (a)

(b)

Fig. 4.19 (a) Threshold voltage shift, and (b) Interface trap density change of the control sample during different frequency AC stresses (VGO= -3.9V) at 125°C. (W/L=

10µm/0.65µm)

79 (a)

(b)

Fig. 4.20 (a) Threshold voltage shift, and (b) Interface trap density change of the device with 100nm SiN-capping layer, during different frequency AC stresses, V_GO= -3.9V at 125°C. (W/L= 10µm/0.65µm)

Stress Time (s)

80 (a)

(b)

Fig. 4.21 (a) Threshold voltage shift, and (b) Interface trap density change of the device with 300nm SiN-capping layer, during different frequency AC stresses VGO= -3.9V at 125°C. (W/L= 10µm/0.65µm)

Stress Time (s)

81 (a)

(b)

Fig. 4.22 (a) Threshold voltage shift, and (b) Interface trap density change as a function of frequency for devices with different capping layers, after VGO = -3.9V 1000sec stress at 125°C. (W/L= 10µm/0.65µm).

Frequency (Hz)

82

簡 歷

姓名：張伊鋒 性別：男 生日：70.7.18 出生地：台北市 籍貫：台中縣

住址：台北縣土城市延峯街 12 巷 9 號

學歷：台北市立松山高中 1996.9~1999.6 國立中興大學 物理學系 1999.9~2003.6 國立交通大學 電子研究所固態組碩士班 2003.9~2005.6 論文題目：具有複晶矽鍺閘極與局部形變通道之 P 型金氧半場效電晶

體元件製作與分析

Fabrication and Characterization of PMOSFETs with Poly-SiGe gate and

Locally Strained Channel

在文檔中 具有複晶矽鍺閘極與局部形變通道之P型金氧半場效電晶體元件製作與分析 (頁 48-99)