具有複晶矽鍺閘極與局部形變通道之P型金氧半場效電晶體元件製作與分析

國 立 交 通 大 學

電 子 工 程 學 系 電 子 研 究 所 碩 士 班

碩 士 論 文

具有複晶矽鍺閘極與局部形變通道之 P 型金氧

半場效電晶體元件製作與分析

Fabrication and Characterization of PMOSFETs

with Poly-SiGe gate and Locally Strained Channel

研 究 生：張伊鋒

指導教授：黃調元 博士

林鴻志 博士

具有複晶矽鍺閘極與局部形變通道之 P 型金氧

半場效電晶體元件製作與分析

FABRICATION AND CHARACTERIZATION OF

PMOSFETs WITH POLY-SIGE GATE AND

LOCALLY STRAINED CHANNEL

研 究 生：張伊鋒 Student: Yi-Feng Chang

指導教授：黃調元 博士 Advisor: Dr. Tiao-Yuan Huang

林鴻志 博士 Advisor: Dr. Horng-Chin Lin

國 立 交 通 大 學

電子工程學系 電子研究所碩士班

碩 士 論 文

A Thesis

Submitted to Institute of Electronics

College of Electrical Engineering and Computer Science

National Chiao-Tung University

in Partial Fulfillment of the Requirements

for the Degree of Master of Science

in

Electronics Engineering

June 2005

Hsinchu, Taiwan, Republic of China

i

具有複晶矽鍺閘極與局部形變通道之 P 型金氧半場效電晶體

元件製作與分析

研究生：張伊鋒 指導教授：黃調元 博士 林鴻志 博士 國立交通大學 電子工程學系 電子研究所

摘 要

我們探討具有複晶矽鍺閘極、與電漿增強式化學氣相沉積氮化矽

覆蓋層之 P 型金氧半場效電晶體（PMOSFETs）特性。其中，使用複

晶矽鍺閘極，可以有效降低閘極空乏與硼穿透效應；而以電漿增強式

化學氣相沉積之氮化矽層，可以提供通道區域內的壓縮應力。由於通

道內的壓縮應力增強，P 型金氧半場效電晶體之驅動電流隨著氮化矽層

厚度增加而增大。同時，我們也探討，具壓縮應變通道的金氧半場效

電晶體，其負偏壓溫度不穩定特性（NBTI）

。雖然氮化矽覆蓋層可以增

大 P 型金氧半場效電晶體的驅動電流，但負偏壓溫度不穩定效應卻較

未覆蓋氮化矽之電晶體更形嚴重。特別是在高溫條件下，氮化矽層造

成的區域應力導致較多的介面狀態產生，這可能是由於通道內的應變

ii

能量造成大量矽氫鍵結斷裂。而覆蓋氮化矽之 P 型金氧半場效電晶體，

在高溫長時間的應力施加下，由於大部分的矽氫鍵結被打斷，臨界電

壓與介面狀態開始呈現飽和現象。電性回復效應可以有效降低介面狀

態的產生，因此動態負偏壓溫度不穩定性與交流應力也被用來模擬電

路中元件的操作特性。我們觀察到，交流應力頻率強烈影響具有氮化

矽覆蓋層元件之臨界電壓改變、與介面狀態產生。

iii

Fabrication and Characterization of PMOSFETs with Poly-SiGe gate and

Locally Strained Channel

Student: Yi-Feng Chang Advisors: Dr. Tiao-Yuan Huang

Dr. Horng-Chih Lin

Department of Electronics Engineering & Institute of Electronics National Chiao Tung University

Abstract

A PMOSFET structure featuring poly-SiGe gate and plasma-enhanced CVD (PECVD) silicon nitride (SiN) capping layer was explored. Poly-SiGe gate is useful to reduce gate depletion and boron penetration, while PE-SiN is used to induce compressive strain locally inside the channel region. PMOSFET’s drive current is enhanced as the thickness of SiN layer increases due to increasing compressive strain in the channel region. Negative bias temperature instability (NBTI) characteristics of PMOSFETs with compressive strain in the channel were also investigated. Although PMOSFET with SiN capping layer show enhanced drive current, its NBTI is worsened, compared to its counterpart without SiN capping layer. A lot of interface states are generated especially in high temperature stress of PMOSFET with SiN layer. This is

iv

ascribed to a higher amount of hydrogen incorporated during SiN deposition as well as the high strain energy stored in the channel. For PMOSFET with SiN layer, under sufficient long stress time at high temperature, saturation of the threshold voltage and interface states is found, indicating that most Si-H bonds are broken. Dynamic NBTI and AC stress characteristics were used to simulate the switching operation of PMOSFETs in circuits. It is observed that the electrical passivation effect could effectively reduce the generation of interface states. Both threshold voltage shift and interface-state generation are strongly dependent on the frequency of dynamic stress for devices with SiN capping layer.

v

誌 謝

首先要向指導教授 黃調元博士與 林鴻志博士致上最高的敬

意與謝意，在他們兩人兩年來細心的指導與關懷之下，使我在人生態

度與專業知識得以成長，實難將心中謝意表達於萬一。

由衷的感謝呂嘉裕學長，他毫不藏私的開闊胸襟與卓越學識，時

時給我知識與實驗上的實際協助，令我無比感佩。感謝盧文泰學長在

量測儀器上的幫助，使我得以順利完成論文。感謝李耀仁學長、葉冠

麟學長、李明賢學長、林宏年學長、盧景森學長、蘇俊榮學長所給予

的關懷與鼓勵。也感謝同學文廷、聰杰、新原、賢達兩年來在研究上

相互砥礪！此外，感謝 NDL 裡的研究員、工程師與工作人員，協助

我順利完成元件的製作。最後，感謝我的家人與朋友，默默的給予我

支持與鼓勵，使我能順利完成學業。

vi

Contents

Abstract (in Chinese)………..……….i

Abstract (in English)……….………….iii

Acknowledgement (in Chinese)……….………v

Contents……….………vi

Table Captions……….…..ix

vii

Chapter 1 Introduction

1.1 General Background………1

1.2 Organization of This Thesis………5

Chapter 2 Device Fabrication and Measurement Setup 2.1 Process Flow………...………6

2.2 Electrical Characterization and Measurement Setup……….……..……7

Chapter 3 Electrical Characteristics of Locally Strained PMOSFETs with Poly-SiGe gate 3.1 Brief Review of Poly-SiGe Gate Technology………...………10

3.2 Brief Review of Strained Si Technology……….……….………12

3.3 Electrical Characteristics of Poly-SiGe Gate Devices………..……16

3.4 Effects of the Strain………...………17

Chapter 4 Effects of SiN Capping on NBTI of PMOSFETs 4.1 Static and Dynamic NBTI……….………20

4.1.1 Brief Review of NBTI Mechanisms………...………20

4.1.2 Dynamic NBTI………...…………24

4.2 Experimental Results and Discussion………...………26

4.2.1 Static NBTI Characterization……….………26

viii Chapter 5 Conclusions 5.1 Conclusions………...………31 Reference………..………32 Table……….………40 Figure………...………41 Vita………..….………82

ix

Table Captions

Table 2.1 Split table of capping layer structure and thickness.

Table 4.1 B/A ratio of devices with different capping layers, at different passivation voltages during DNBTI stress.

x

Figure Captions

Fig. 2.1 Schematic cross section of the local strained channel PMOSFET. Fig. 2.2 TEM micrographs of device with channel length 0.55µm.

Fig. 2.3 Configuration for (a) gate-to-substrate, (b) gate-to-channel capacitance measurements.

Fig. 2.4 Bias configuration of NBTI stressing.

Fig. 2.5 Measurement setup in our charge pumping experiment.

Fig. 3.1 Schematic illustration for 3D process-induced strain components.

Fig. 3.2 (a) Splitting of 6-fold degenerate conduction band in unstrained and biaxial tensile strained Si inversion layers. (b) Schematic diagram of the valence bands in unstrained and strained Si layers. (c) Splitting of light hole band and heavy hole band with biaxial and uniaxial strains in low electric field (solid line) and high electric field (dash line).

Fig. 3.3 Cumulative probability distribution of sheet resistance of poly-Si and poly-SiGe films. Both with thickness of 150nm, implanted with B implant (dose 3e15cm-2, 8KeV) and anneal at 900°C 30sec.

Fig. 3.4 Output characteristics of devices with poly-Si and poly-SiGe gates at 25°C and VG- Vth= 0 ~ -2 V, step= -0.4 V, W/L= 10µm/1µm.

xi

Fig. 3.5 Capacitance of devices with poly-Si and poly-SiGe gates. (W/L= 50µm/50µm)

Fig. 3.6 Comparison of hole mobility among different gate materials measured by split-CV method.

Fig. 3.7 Output characteristics of different capping layers at (a) 25°C (b) 125°C and VG- Vth= 0 ~ -2 V, step= -0.4 V, W/L= 10µm/0.55µm.

Fig. 3.8 Subthreshold characteristics of devices with different capping layers at (a)25°C (b)125°C and VD= -0.05 V, -2 V, W/L= 10µm/0.55µm.

Fig. 3.9 Transconductance for devices with different capping layers at (a)25°C (b)125°C and VD= -0.05 V, W/L= 10µm/0.55µm.

Fig. 3.10 Measured CV profile for devices with different capping layers at 25°C W/L= 50µm/50µm.

Fig. 3.11 Saturation current (VD= -2 V, VG- Vth= -2 V) enhancement of different SiN

thickness as a function of channel length at (a) 25°C (b) 125°C

Fig. 3.12 Subthreshold swing of devices with different capping layers as a function of channel length at (a) 25°C, and (b) 125°C.

Fig. 3.13 Threshold voltage of devices with different capping layers as a function of channel length at (a) 25°C, and (b) 125°C.

xii

Fig. 3.14 Changes of threshold voltage for devices with different capping layers as a function of channel length at 25°C.

Fig. 3.15 Charge pumping current of devices with different capping layers at 25°C, W/L= 10µm/1µm, pulse amplitude= 1.5V, frequency= 1MHz.

Fig. 4.1 Schematic view of the field-induced hydrogen species current through the gate oxide during negative bias aging.

Fig. 4.2 Various phases of Nit buildup.

Fig. 4.3 (a) Threshold voltage shift, (b) Transconductance degradation, (c) Interface trap density increasing, and (d) Oxide trap density increase at 25°C during VGO = –3.9 V stress aging (W/L= 10µm/0.55µm).

Fig. 4.4 (a) Threshold voltage shift, (b) Transconductance degradation, (c) Interface trap density increase, and (d)oxide trap density increase at 125°C

during VGO = –3.9V stress aging (W/L= 10µm/0.55µm).

Fig. 4.5 (a) Threshold voltage shift, and (b) Interface trap density increase of the control sample at 25°C with different VG stresses (W/L= 10µm/0.55µm).

Fig. 4.6 (a) Threshold voltage shift, and (b) Interface trap density increase of the device with SiN-capping 100nm sample at 25°C with different VG

xiii

Fig. 4.7 (a) Threshold voltage shift, and (b) Interface trap density increase of the device with 300nm SiN-capping at 25°C with different VG stresses.

(W/L= 10µm/0.55µm)

Fig. 4.8 (a) Threshold voltage shift,and (b) Interface trap density increaseof the control sample at 125°C with different VG stresses. (W/L= 10µm /0.55µm)

Fig. 4.9 (a) Threshold voltage shift, and (b) Interface trap density increase of the device with 100nm SiN-capping at 125°C with different VG stresses.

(W/L= 10µm/0.55µm)

Fig. 4.10 (a) Threshold voltage shift, and (b) Interface trap density increase of the device with SiN-capping 300nm sample at 125°C with different VG

stresses. (W/L= 10µm/0.55µm)

Fig. 4.11 Threshold voltage shift dependence on temperature with different capping layers, estimated by VGO = –3.9 V, 1000s stress.

Fig. 4.12 (a) Interface trap density, and (b) Oxide trap density change dependence on temperature with different capping layers, estimated by VGO = –3.9 V,

1000s stress.

Fig. 4.13 (a) Threshold voltage shift, and (b) Interface trap density change of the control sample during VGO = –4 V and different passivation stresses at

xiv

Fig. 4.14 (a) Threshold voltage shift, and (b) Interface trap density change of the device with 100nm SiN-capping 1ayer during VGO = –4 V and different

passivation stresses at 125°C. (W/L= 10µm/0.75µm)

Fig. 4.15 (a) Threshold voltage shift, and (b) Interface trap density change of the device with 300nm SiN-capping layer during VGO = –4 V and different

passivation stresses at 125°C. (W/L=10µm/0.75µm)

Fig. 4.16 (a) Interface trap density change, and (b) Subthreshold swing shift dependence on threshold voltage shift of the control sample, during VGO= –4 V and different passivation stresses at 125°C. (W/L= 10µm

/0.75µm)

Fig. 4.17 (a) Interface trap density change, and (b) Subthreshold swing shift dependence on threshold voltage shift of the device with 100nm SiN-capping layer, during VGO= –4 V and different passivation stresses at

125°C. (W/L= 10µm/0.75µm)

Fig. 4.18 (a) Interface trap density change, and (b) Subthreshold swing shift dependence on threshold voltage shift of the device with 300nm SiN-capping layer, during VGO= –4 V and different passivation stresses at

xv

Fig. 4.19 (a) Threshold voltage shift, and (b) Interface trap density change of the control sample during different frequency AC stresses (VGO= -3.9 V) at

125°C. (W/L= 10µm/0.65µm)

Fig. 4.20 (a) Threshold voltage shift, and (b) Interface trap density change of the device with 100nm SiN-capping layer, during different frequency AC stresses, VGO= -3.9 V at 125°C. (W/L= 10µm/0.65µm)

Fig. 4.21 (a) Threshold voltage shift, and (b) Interface trap density change of the device with 300nm SiN-capping layer, during different frequency AC stresses VGO= -3.9 V at 125°C. (W/L= 10µm/0.65µm)

Fig. 4.22 (a) Threshold voltage shift, and (b) Interface trap density change as a function of frequency for devices with different capping layers, after VGO =

1

Chapter 1

Introduction

1.1 General Background

As the channel length of MOSFETs continues to scale down, it is becoming more and more difficult to maintain high transistor performance because of mobility degradation caused by increased substrate doping. The mobility of carriers in the channel is one of the important parameters for MOSFET operation. Higher mobility helps contain power consumption by allowing the use of lower operation voltage. Moreover, the urgency of incorporating high-k gate dielectric in IC manufacturing can also be relieved. Utilizing strain engineering in the channel region to improve electron and hole mobility has been actively pursued [1,2]. Recently, MOSFETs with high bi-axial tensile channel stress by growing a Si channel layer on a relaxed SiGe substrate has been demonstrated [3,4]. Performance of both NMOSFET and PMOSFET was improved by the bi-axial tensile stress when more than 20 % Ge is incorporated in the relaxed SiGe layer. However, the yield issue associated with high threading dislocation density (typically > 104 cm-2) of the virtual SiGe substrates represents a major obstacle for practical applications. In addition, other concerns, such as high Ge content and up-diffusion, fast diffusion of n-type dopants, and high wafer cost further blight the

2

situation.

In contrast, approaches that introduce uni-axial channel strain can be free from the aforementioned concerns. In this aspect, channel strain can be engineered and optimized by modifying the device processing and/or structure, including those steps involving gate capping layer (e.g., SiN), trench isolation, silicidation, and source/drain [5,6]. Electron mobility gain is similar between uni-axial and biaxial tensile strains, since both originate from the splitting of the six-fold degenerate conduction band valleys. However, uni-axial longitudinal compressive stress offers much larger hole mobility enhancement at a given stress level than the bi-axial tensile strain [7], and may have lower surface roughness scattering probability due to high out-of-plane effective mass.

It has been shown that the mechanical stress from a contact etch-stop SiN layer over the gate electrode can significantly affect the drive current [8, 9]. Depending on the deposition conditions, the SiN capping layer can generate either tensile or compressive stress [9]. It thus can be applied to the NMOS devices that benefit from tensile stress, as well as PMOS devices that benefit from compressive stress.

As CMOS technology is scaled into deep-submicron regime for higher density and speed, thinner gate oxide is required to provide sufficient current drive while the supply voltage is scaled down. Ultra-thin gate oxide (<2nm) has been reported in CMOS devices [10,11]. With such thin oxides, the poly-depletion effect (PDE) and boron

3

penetration have become critical issues. These technical issues impose strict limitations on the process window and may degrade device performance [12,13]. The poly-SiGe has been expected as a promising alternative gate material by taking advantage of its lower PDE and boron penetration. Process compatibility with existing Si technology has been demonstrated and significant improvements of deep-submicron PMOS transistor performance have been observed [14].

Since the melting point of SiGe is lower than that of Si, physical phenomena controlling fabrication processes, such as deposition, crystallization, grain growth, and dopant activation, occur at a lower temperature for SiGe than for Si. Thus, lower process temperature can be used for fabricating devices with poly-SiGe gate. It is thus preferable to poly-Si for various applications in technologies that have limited thermal budget tolerance.

Most important for the work presented here, the p-type work-function decreases with increasing Ge mole fraction [15~20]. Implementation of poy-SiGe gate without adjusting the channel doping profile accordingly results in an increased VT of the

resultant devices, which reduces IOFF. On the other hand, for a specified VT, the channel

doping is reduced to compensate for the change in work-function of the gate electrode, the channel mobility could increase due to suppressed Coulomb scattering.

4

reliability issues emerge. A number of characterization schemes, such as time- or charge-to-breakdown (TBD or QBD), hot carrier stress, and

negative-bias-temperature-instability (NBTI) test, have been developed to evaluate the reliability of dielectrics as well as to predict the lifetime of the MOS device.

As the oxide thickness is thinned down to the regime of 3nm or less, hot carrier effects become less important due to the reduced operation voltage [21,22]. It was recently shown that the threshold voltage shift in a PMOSFET due to negative-bias-temperature (NBT) stress becomes more and more significant as oxide is scaled down.

NBTI of p-channel MOSFETs with ultra-thin gate dielectrics has been reported as one of the most serious reliability issues due to the large threshold voltage shift and drive current degradation. The NBTI degradation may even become the major factor in limiting the device lifetime when the gate oxide thickness is scaled down to 3.5 nm and less. Despite many research efforts, detailed NBTI degradation mechanism is not yet fully understood. This is further complicated by the fact that the NBTI is affected by several other factors, such as hydrogen incorporation and boron penetration.

Conventional NBTI testing based on static experimental data. The measurements disregards the electric passivation effect of the interface traps during the operation of PMOSFETs in digital circuits, and therefore overestimates the degradations of PMOS

5

devices. In this aspect, results of dynamic NBTI (DNBTI) stress measurements are much closer to the situation of practical circuit operation. Therefore, it is important to investigate NBTI under such dynamic stress conditions.

1.2 Organization of This Thesis

In this study we investigate the effect of compressive strain on the performance of pMOS devices with poly-SiGe gate induced by a SiN capping layer and the associated NBTI characteristics. This thesis is divides into five chapters:

In Chapter 2, we briefly describe the process flow for fabricating the pMOS devices with the poly-SiGe gate and SiN capping layer. We also present the characterization method and the stress conditions.

In Chapter 3, we show and discuss the improvement on device performance with SiN capping layer.

In Chapter 4, the results on evaluating the static and dynamic NBTI characteristics of the devices are presented. Effects of strain on the NBTI are also discussed.

Finally important conclusions generated from our experimental results are summarized in Chapter 5. Some recommendations and suggestions for future work are also given.

6

Chapter 2

Device Fabrication and Measurement Setup

2.1 Process Flow

The PMOSFETs were fabricated on 6-inch n-type (100) Si wafers with resistivity of 2~7Ω-cm. Standard local oxidation of silicon (LOCOS) process was used for device isolation. Threshold voltage adjustment and anti-punch through implantation were done by implanting 80 KeV As+ and 120 KeV P+, respectively. After the growth of 3 nm-thick thermal gate oxide, a 150nm undoped poly-SiGe layer was deposited by low-pressure chemical vapor deposition (LPCVD), followed by gate etch process to pattern the film. The Source/Drain (S/D) junctions were then formed by B+ implantation at 10 keV and 5×10-15 cm-2. After a 50nm TEOS spacer formation, S/D regions were etched to a depth of 30 nm. In-situ-doped SiGe (50 nm) epitaxy was subsequently performed on the recessed S/D regions by ultra-high-vacuum chemical vapor deposition (UHVCVD). Rapid thermal anneal(RTA) was then carried out in a nitrogen ambient at 900°C for 30 sec to activate dopants in the gate, S/D, and substrate regions. Afterwards,

a SiN/TEOS stack layer was deposited on the transistor by plasma-enhanced CVD (PECVD). In order to investigate the effect of SiN strain, three types of samples were fabricated with split thickness of 0, 100, and 300nm, respectively. The stress

7

measurement performed on a blanket Si wafer capped with a SiN of 100 nm thickness indicates that 95MPa compressive stress is induced. After contact hole etching, normal metallization scheme was carried out. The final step was a forming gas anneal performed at 400°C for 30 min to mend dangling bonds and reduce interface state

density in gate oxide/Si interface. Cross sectional view of the fabricated device was showed in Fig. 2.1, and transmission electron microscopy (TEM) was shown in Fig. 2.2. PMOSFETs with three different capping layers have been fabricated as shown in Table 2.1.

2.2 Electrical Characterization and Measurement Setup

Electrical characterizations and static NBTI stressing tests were performed using an HP 4156 system. DNBTI stressing tests were performed using a Keithley 4200 system. A precision impedance meter, HP4284, was used for C-V measurements. Temperature-regulated hot chucks were controlled at temperatures ranging from 25°C to 125°C.

Split C-V method was employed to determinate the holes mobility. The electric field produced by the gate voltage is express as:

0 b n eff s Q Q E K η ε + = (2-1) g fb V b gb g V Q =

∫

C dV ′ (2-2)

8 g V n gc g Q C dV −∞ ′ =

∫

(2-3) where Qb and Qn are charge densities in depletion layer and inversion layer, respectively.

The parameter η=1/3 for hole mobility. The gate-to-substrate capacitance (Cgb) and

gate-to-channel capacitance (Cgc) were measured using the configurations illustrated in

Fig. 2.3.

The existence of a gate leakage current may affect the accurate measurement of drain conductance. To solve this problem, we propose some new approaches as followed. The channel current is simply given by the average of the source and the drain currents. For surface carrier concentration evaluation, we have adopted a simple approach that takes drain voltage effect into account [23].

( ) ( ) 1 ( ) ( ( ) ( ) ) 2 2 g g d V V V s g d g g gc g g gc g g d I V I V L V C V dV C V dV W V q µ − −∞ −∞ + ′ ′ ′ ′ = ⋅ ⋅ ⋅

∫

+

∫

(2-4) The fabricated devices were subjected to bias-temperature-stress (BTS) from 25°C to 125°C. During the BTS, a negative gate bias (-3.5 V~ -4.3 V) was applied, while

drain/source and substrate were all grounded, as schematically shown in Fig. 2.4.

The interface state density was evaluated using the charge pumping method. In the characterization, square-wave (f = 1MHz) voltage signals were applied to the gate with a constant pulse amplitude of 1.5 V, and a varying base voltage to tune the surface condition from inversion to accumulation. Fig. 2.5 shows the configuration of

9

measurement setup used in the charge pumping experiment. A MOSFET with a gate area of AG gives the charge pumping current as:

cp G it

I =qA fN (2-5)

Interface trap density could be evaluated by using this equation.

Oxide traps cannot respond to the Icp signal at high frequency and are categorized as slow traps. The mean interface trapped charge contributes only by ψB as surface

potential is roughly equal to 2ψB. A simple and direct way to deduce oxide trap density

(Not) is to calculate the difference between the measured Δ Vth and the term

contributed by ΔNit from charge pumping results, using the following formula:

, ( ( )) ( ) Don Acc ot it s B th ox ox q N q N T V T C C ψ φ ∆ ∆ − ∆ = − − (2-6)

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Chapter 3

Electrical Characteristics of Locally Strained

PMOSFETs with Poly-SiGe gate

3.1 Brief Review of Poly-SiGe Gate Technology

Technical challenges emerge as the critical dimensions of semiconductor devices are scaled down to the deep-submicron regime in a pursuit of higher levels of integration and performance. The dual-gate process has replaced the conventional single-gate process for advanced CMOS fabrication. For dual-gate process, boron penetration through the gate oxide from the p+-doped gate of PMOSFETs becomes a major concern. In addition, gate-depletion effect due to insufficient dopant activation at the gate/dielectric interface becomes more significant as gate oxide thickness is scaled down, and leads to the degradation of the drive current.

To alleviate the above-mentioned problems, poly-SiGe has been proposed as a promising alternate gate material to replace the conventional poly-Si gate. First, the dopant activation in poly-SiGe is better than in poly-Si for p-type gate material. Besides, the p-type poly-SiGe film has lower resistivity, reduced gate-depletion effect, and suppressed boron penetration, thanks to the higher dopant activation ratio as comparing

11

to poly-Si film. Mechanism of the improved boron activation is presumably caused by the local strain compensation due to the difference in atomic radii between Si and B atoms [24].

When p+ poly-Si is substituted by p+ poly-SiGe as the gate material for the PMOS device, the change in the gate to semiconductor work-function difference, ΔΦms, can

be approximately calculated as the difference in the energy bandgaps between the two heavily-doped materials, i.e., ∆Φ =_ms E_Gpoly Si− −E_Gpoly SiGe− . This is due to the fact that the position of the conduction band edge of the materials remains essentially unchanged regardless of the Ge incorporation. For high Ge concentration, a significant amount of stress contained in the poly-SiGe grains results in an extra reduction of the gate work-function [19]. In order to retain the threshold voltage at the reference value, one can change ΔΦms by reducing the channel doping. As a result, hole mobility is

enhanced due to reduction of Coulomb scattering centers in the channel region. The drive current is thus increased. The subthreshold swing could also be reduced due to decrease in the depletion layer capacitance, leading to an improved Ion/Ioff ratio. The

reduction of the body factor results in weaker threshold voltage dependence on variations of the substrate potential.

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point of poly-SiGe film, and this is conducive to reducing the process thermal budget. The poly-SiGe alloy films also have good compatibility with standard CMOS processing.

3.2 Brief Review of Strained Si Technology

Rapid growth in the study of implementing strained silicon to the channel has been witnessed in the past several years. Historically, improvements on MOSFET’s performance have been attained by shrinking device dimensions. However, the practical benefit of scaling is compromised as physical and economic limits are being approached, and novel solutions are being sought. The 2003 ITRS roadmap started to schedule the mobility enhancement factor by stress controls. Strain improves MOSFET drive current by altering the band structure of the channel and can therefore enhance performance even at aggressively scaled channel lengths. Bi-axial and uni-axial strained silicon technologies are promising for enhancement of CMOS performance [25~30]. For the case of a silicon layer under bi-axial tensile strain, it is mainly implemented by the lattice mismatch with an underling relaxed SiGe layer. Note that, to avoid the generation of high amount of dislocations, thickness of the top strained Si layer must be thinner than the critical thickness that depends on the Ge content of the underlying relaxed SiGe

13

layer. In contrast, uni-axial strain can be engineered by modifying capping layer deposition [9][31], shallow trench isolation [32][33], source/drain material [6], silicidation [34], packing process [35], and so on. Furthermore, the behaviors of carrier mobility under uni-axial strain depend on the strength of the strain and the orientation. Electron and hole mobilities respond to the complex three-dimensional mechanical stress in different, even opposite ways, as shown in Fig. 3.1.

Several different behaviors caused by bi-axial and uni-axial stress were reported, such as the drop of mobility enhancement at high electric field and threshold voltage shift. Bi-axial strain improves electron transport more than hole transport, and vice versa for the perpendicular uni-axial strain. Uni-axial strain can be applied arbitrarily in any direction relative to the carrier transport direction. Enhancements of carrier mobility under bi-axial and uni-axial strain were induced by different factors and mechanisms.

For NMOSFETs, recent reports and theoretical calculations indicate that strained-Si under bi-axial or uni-axial tension should exhibit a higher mobility than bulk Si. The differences in electronic conduction due to bi-axial and uni-axial strain can be explained by examining the splitting of the degeneracy at the conduction band edges. The biaxial tensile strain induces splitting of degeneracy in the triangular potential well of the MOS inversion layer. This splits the six-fold degenerate Si conduction band into a

14

two-fold (Δ2) and a four-fold (Δ4) branches. The energy of sub-band in four-fold valley is lower than that in two-fold valley under uni-axial tensile stress, opposing to what occurs in the case of bi-axial tensile stress. The energy difference (ΔE) between Δ2 and Δ4 sub-bands determines the total population of the bands. The enhancement

of uni-axial and bi-axial strained-Si caused by the splitting of conduction band can suppress inter-valley phonon scattering [36]. At high electric field, even in bulk Si NMOSFETs, the six-fold degeneracy is broken near the Si/SiO2 interface by the

confinement of carrier at surface (as shown in Fig. 3.2(a)). The two-fold sub-band is also preferentially occupied at high gate bias. Most inversion electrons are expected to reside in two-fold sub-band even for devices fabricated on bulk Si. In contrast, bi-axial tension causes nearly 100% of inversion electrons to occupy the two-fold sub-band at all gate biases. Note that the enhancement of bi-axial tension at high electrical field, albeit not as high as that at low field, is still very significant [37].

To quantify the mobility enhancement of holes, changes in the scattering and effective mass depend on the altered valence band caused by the strain. For both bi-axial tensile and longitudinal uni-axial compressive stresses, the effective mass is nearly constant over the surface energy range of a few kT below the valence band in contrast to un-strained case.The constant effective mass results since strain removes the

15

degeneracy and reduces the band-to-band coupling. From full-band Monte Carlo simulation [38], uni-axial compressive strained MOSFETs may have lighter in-plane effective mass thus improve hole mobility. For bi-axial tensile stress, the effective mass is heavier than un-strained case. The hole mobility enhancement is only possible through the reduction of inter-valley scattering [39]. This effect becomes significant only when the strain level is high enough (e.g., Ge > 20 %). Reducing the intra-band acoustic scattering by altering the light- and heavy-hole band density-of-states is negligible for uni-axial strain in Si, even at several hundreds of mega-pascal. On the other hand, the energy difference ΔEs (as shown in Fig. 3.2) between light-hole band and heavy-hole band was split by uni-axial stress at gamma-point (k=0) and reduces the optical phonon scattering (as shown in Fig. 3.2(b)). Significant scattering reduction requires ΔEs > 60meV (optical phonon energy in Si) [13].

Hole mobility at high vertical field with uni-axial compressive and biaxial tensile stresses would have different behaviors. Splitting of light- to heavy-hold band caused by uni-axial and biaxial stresses has no significant difference without considering surface quantization confinement. However, the splitting of light- and heavy-hole bands caused by bi-axial tensile stress would be nullified at high electric field due to surface confinement [40]. In contrast, hole mobility enhancement under uni-axial compressive

16

strain is not nullified by surface confinement, which represents a major advantage for MOSFETs operating at high electric fields. The splitting magnitude of the surface confinement depends on the relative magnitude of the stress altered light and heavy hole out-of-plane effective masses. Recent reports [41] showed the interesting result that the out-of-plane effective mass of light hole is heavier than heavy hole for uni-axial stress and causes the light to heavy hole band splitting to increase. On the contrary, for bi-axial stress the previously-reported out-of-plane effective mass of light hole is lighter than heavy hole and causes the band splitting to be reduced. This is why the bi-axial stress degrades hole mobility enhancement at high vertical electric fields (as shown in Fig. 3.2(c)).

The threshold voltage shift caused by bi-axial tensile stress is larger than the case with uni-axial tensile strain has been reported for NMOSFETs [42]. For PMOSFETs, larger shift of light-hole band edge under bi-axial tensile strain leads to larger shift in Vth than the case with uni-axial compressive strain [41].

3.3 Electrical Characteristics of Poly-SiGe Gate Devices

Figure 3.3 shows the cumulative probability distribution of sheet resistance for poly-Si and poly-SiGe (Ge: 20%) gates with nominally identical implant and annealing

17

conditions. Thickness of the films is around 150nm. As can be seen in the figure, the sheet resistance becomes lower as Ge incorporated, owing to the higher dopant activation [19]. This results in improved output characteristics for the device with poly-SiGe gate, as shown in Fig. 3.4. Figure 3.5 compares the C-V characteristics of the devices. This further confirms the fact that poly-SiGe gate could effectively suppress poly-depletion effect. Fig. 3.6 shows the mobility as a function of effective vertical electric field. PMOSFETs using poly-SiGe as gate material have no significant effect on holes mobility with the nominally identical channel doping profile. However, lowering in channel doping to compensate the Vth shift due to work-function difference in poly-SiGe-gated devices may result in improved low-field mobility.

3.4 Effects of the Strain

The stress from PE-SiN layer was first examined by probing blanket monitor sample deposited on Si wafers. We confirmed that the stress is compressive and increases monotonically with increasing thickness. The stress is around –95 MPa for 100 nm SiN. Figures 3.7(a) and 3.7(b) show the output characteristics of PMOSFETs with the identical geometry at different temperatures. Saturation current increases monotonically with increasing capping layer thickness. Figures 3.8 (a) and (b) illustrate

18

the Id-Vg characteristics at different temperatures. The transconductance of the devices exhibits similar trends, as shown in Figs. 3.9 (a) and (b). It should be noted that, in Fig. 3.10, there is no significant difference of the capacitance between unstrained and strained channel devices. From these results it is inferred that the holes mobility is improved by SiN capping layer.

Figs. 3.11 (a) and (b) show the percentage increase of the saturation current of the SiN-capping relative to the control devices as a function of channel lengths at 25°C and 125°C, respectively. The enhancement is less pronounced at high temperature owing to

the enhanced phone scattering rate. The mobility enhancement is more significant as channel length is scaled down. Subthreshold swing of the devices seems not to be affected by the induced strain, as shown in Figs. 3.12 (a) and (b), even as operated at a raised temperature (125°C).

Figs. 3.13 (a) and (b) show the threshold voltage as a function of channel length. Fig. 3.14 illustrates the changes in threshold voltage for devices with SiN layer capping relative to that of control devices. For long channel devices (e.g., L > 2 µm), a nearly

constant shift is observed in Fig. 3.14. This phenomenon could be explained by the reduction in the interface trap density extracted from charge pumping measurements, as shown in Fig. 3.15. Since the he precursors for SiN deposition are SiH4 and NH3, a large

19

amount of hydrogen species can be introduced during processing and passivate the interface states. As also can be seen in the figure, the amount of change in threshold voltage increases with decreasing channel length, especially as channel length is scaled below 1 µm. Such phenomenon is presumably caused by the splitting of valence band

20

Chapter 4

Effects of SiN Capping on NBTI of PMOSFETs

4.1 Static and Dynamic NBTI

4.1.1 Brief Review of NBTI Mechanisms

For the aggressive scaling of CMOS technologies, an ultra thin gate oxide is essential to achieve high drive current under lower power operation. The integrity and reliability of such a thin gate oxide are therefore crucial for ULSI manufacturing. Recently, negative-bias-temperature instability (NBTI) has been identified as one of the major reliability concerns for deep sub-micron PMOSFETs [45]. It was observed that a large number of interface states and positive fixed charges were generated during negative-bias-temperature stressing (NBTS), resulting in a negative shift in threshold voltage showing a power-law dependence on stress time:

b

th At

V

∆ = (4-1)

This phenomenon becomes more significant as gate oxide is scaled down, and may even become the limiting factor for deep sub-micron p-channel devices. The shift in threshold voltage and degradation in transconductance have been suggested to be due to the interfacial electrochemical reactions related to the holes from the channel inversion

21

layer. The exponential value of the power law equation is around 0.25, which could be explained by the diffusion-controlled electrochemical reactions. Based on the t0.25-like time evolution, a generalized reaction-diffusion model for interfacial charge formation based on the trivalent silicon and its hydrogen compounds was proposed [46].

In the Svensson model [47], an interface trap is a trivalent silicon atom with an unsaturated valence electron (dangling bond) at the Si-SiO2 interface. It is denoted by

Si≡ iSi and acts as an active interface trap. A post-metal-anneal in a forming gas

(typically 10% H2 in N2 ambient) is widely used to passivate the interface dangling

bonds, and introduces a lot of hydrogen-terminated trivalent Si bonds which are electrically inactive at the actual interface. If the terminated hydrogen is released from the Si≡ −Si H bond by some dissociation mechanism, the remaining interface

trivalent silicon (dangling bond) is restored as an active interface trap. Various mechanisms have been proposed for the dissociation process.

High electric fields can dissociate the silicon-hydrogen bond, according to the model [48]

0

3 3

Si ≡SiH →Si ≡Sii+H , (4-2)

where H0 is a neutral interstitial hydrogen atom or atomic hydrogen. Recent first-principle calculations show that the positively charged hydrogen or proton H+ is the

22

only stable charge state of hydrogen at the interface, and that H+ reacts directly with the SiH to form an interface trap, according to the reaction [47]:

3 3 2

Si ≡SiH+H+ →Si ≡Sii+H . (4-3)

The SiH is polarized in this model such that the mobile positive H+ migrates towards the negatively charged dipole region in the SiH molecule. The H+ atom then reacts with the H- to form H2, leaving behind a positively charges Si dangling bond.

A different model considers the interaction of SiH with “hot holes” or holes near or at the Si/SiO2 interface [46]. Dissociation involving holes is given by

3 3

Si ≡SiH+h+ →Si ≡Sii+H+. (4-4)

Fig. 4.1 is a schematic view of reaction-diffusion model for Nit generation.

The fixed charge (Qf) also contributes to threshold voltage shift near the SiO2/Si

interface. Qf is a by-product of trivalent Si defect in the oxide, generated with the

reaction

0

3 3

O ≡SiH+h+ →O ≡Si++H (4-5)

As discussed in Ref. 46, the interface trap density (Nit) and fixed oxide charge

density (Nf) are shown to increase as:

1.5 0.25 it ox exp( a/ ) / Tox N CE t E kT ∆ = − ; (4-6) ' 1.5 0.14 ' ox exp( / ) f a N C E t E kT ∆ = − , (4-7)

23

here C and C’ are appropriate constant values, Eox is electric field in the oxide, Tox

is oxide thickness and aging time t. Ogawa et al. [46] found that the generation of fixed oxide charges is independent of oxide thickness, but is inversely proportional to oxide thickness for interface trap generation. This suggests that NBTI is worse for thinner oxide, but this phenomenon is not always observed and highly dependent on the process conditions.

The stable interface traps are only formed if by-product species, X, diffuses away from the interface into the oxide bulk.

diffusion

interface bulk

X ⎯⎯⎯⎯→X (4-8) while “X” could be H-related species.

As proved by Jeppson and Svensson [49], the observed t0.25 behavior of the interface trap generation suggests the generation process is diffusion controlled. Nit

buildup equals the total number of released H species. Hole-assisted reaction breaks interfacial SiH bonds, resulting in Nit generation:

n

it N X

∆N = (D t)S , (4-9)

where Dx is the diffusion coefficient of X in the oxide, time exponent n depends on

the type of H species trapped and released in the oxide bulk [50].

24

generation rates is only partially correct [46]. In fact, there may exist six regimes of the reaction-diffusion model for Nit generation [51] as shown in Fig. 4.2.During the early stress stage, the generation of interface states and hydrogen species is limited by the dissociation rate (regime1, Nit ~ t1). Then, the process enters the quasi-equilibrium

regime (regime2, Nit ~ t0) immediately. After some stress time, the transport of

hydrogen species limits the dissociation process (regime3, Nit ~ t0.25). However, the

reaction-controlled regime could directly merge into the diffusion-controlled regime. The rate of ΔNit changes after H diffusion front reaches the SiO2/poly interface. Either

H absorption into poly ensures faster H removal and higher rate of ΔNit (regime4) or H

reflection from poly would result in ΔNit saturation (regime5). Finally, ΔNit should

eventually saturate when all SiH bonds are broken (regime6).

4.1.2 Dynamic NBTI

The conventional NBTI based on static experimental data. During normal operations of digital circuits, the applied bias to the gate of PMOSFETs in a CMOS inverter is switched between “high” and “low” voltages. During “low” phase of PMOSFETs applied bias, the “electric passivation” effect may effectively reduce the interface traps generated during the “high” phase. The dynamic NBTI (DNBTI) effect greatly prolongs the lifetime of PMOSFETs operating in a digital circuit, while the

25

conventional static NBTI measurement underestimates the PMOSFET lifetime. Furthermore, the DNBTI effect is dependent on temperature and gate oxide thickness [52]. A physical model is proposed for DNBTI that involves the interaction between hydrogen and silicon dangling bonds [53]. According to this reaction-diffusion theory, the Δ Vth is attributed to the creation of interface traps as a consequence of dissociation of Si-H bonds, and subsequent diffusion of the released hydrogen species towards the gate electrode. In the recovery process, released hydrogen re-passivates Si dangling bonds [53]. The ΔVth recovery progresses in accordance with the power law dependency as follows:

n th

V =A-B t

∆ ⋅ , (4-10) where B/A ratio indicates the ratio of a recovery reaction coefficient to ΔVth just after NBT stress. This finding has significant impact on the determination of maximum operation voltage as well as lifetime for future scaling of CMOS devices. Therefore, it is critically important to investigate NBTI under such dynamic stress conditions.

26

4.2 Experimental Results and Discussion

4.2.1 Static NBTI Characterization

Figure 4.3 shows the results of NBTI stress performed at 25°C with gate overdrive bias of –3.9 V (VGO = VG - Vth). As can be seen in Fig. 4.3(a), larger change in threshold

voltage shift, ΔVth, is observed in the device with SiN capping layer. The shift curves

show a fractional power-law dependence on time, and the exponential values with SiN-capping sample are larger than the control sample. According to the classical reaction-diffusion model, such dependence implies that NBTI is controlled by the diffusion. From Fig. 4.3(b), the maximum value of transconductance, Gmmax, degrades

gravely in the device with SiN layer. The increase of interface trap density, ΔNit, for

devices with SiN capping layer are larger than that of control case, as shown in Fig. 4.3(c). The exponential value ofΔNit in power-law relationship is higher for devices

with SiN capping. Similar phenomenon is also observed for the generation of oxide trapped charges, ΔNot, as shown in Fig. 4.3(d).

The above results clearly indicate that the use of PECVD SiN capping may result in degraded NBTI. Two plausible origins are postulated to explain the worsen NBTI: (1) Higher density of Si-H bonds at the oxide/Si interface, since the SiN layer contains a

27

large amount of hydrogen species because of the use of SiH4 and NH3 precursor gases;

(2) Higher strain energy stored in the channel. The energy may help trigger the electrochemical reactions at the interface. This is evidenced by the higher exponent value of the power-time dependence for devices with SiN capping.

Figure 4.4 shows the results after NBTI stress at 125°C. The trends are similar to those occurring at 25°C. The devices with SiN-capping have aggravated NBTI issue. It should be noted that in Fig. 4.4(a), Fig. 4.4(c) and Fig. 4.4(d), nearly saturation inΔVth,

ΔNit andΔNot are observed for the device with SiN capping when the stress time is

longer than 1000 sec. The NBTI is related to the amount of hydrogen species bonded at the oxide/Si interface, and ∆Nit should eventually saturate when nearly all Si-H bonds

are broken. The disparity between the two splits is postulated to be caused by the local strain induced in the SiN capping split. The existence of strain weakens the bond strength of hydrogen species that in turn accelerates the bond-breaking process. Such phenomenon is not observed in the control devices due to the lack of high strain in the channel.

Figures 4.5 ~ 4.7 show ΔVth and ΔNit characteristics as a function of time under

different VGO at 25°C for the three splits of samples. ΔVth andΔNit for all cases

28

power-law relationship are similar under different stress conditions in each split. Because of ΔNit ∝ Eox1.5, higher VGO can induce larger amount of Nit and degradation.

Figures 4.8 ~ 4.10 illustrate ΔVth and ΔNit evolution under different VGO aging at

125°C for the three splits of samples. The trend for ΔVth at 125°C is similar to the

results at 25°C. However, the exponential value of ΔNit in power-law relationship

decreases with increasing stress bias for the devices with SiN capping. It can be concluded that larger amounts of SiH bonds are broken by higher stress bias during early stress aging. Figures 4.11 and 4.12 illustrate the temperature dependence (Arrehenius plots) of ΔVth, ΔNit andΔNot under 1000 sec stressing. The slope

(activation energy) is larger for the devices with SiN capping.

4.2.2 DNBTI and AC stress

To simulate the switching operation of the device in the CMOS circuits, the gate voltage during NBTI stress is switched between negative and positive bias for all splits as shown in Figures 4.13 ~ 4.15. The condition during stress periods was for 125°C, VGO = –4 V, while that for passivation periods VG was set at several biases. Other

terminals were grounded during the measurement. As can be seen in Figs. 4.13(a), 4.14(a) and 4.15(a), theΔVth, reductions of VG = +1 V during passivation are more

29

when higher strain is contained in the channel. The trends in interface trap density shift are similar among the three splits, as shown in Fig. 4.13(b), Fig. 4.14(b) and Fig. 4.15(b), which have weaker dependence on the recover voltage. BecauseΔNit is

proportionate to ΔVth even at different positive biases during DNBT stressing, as

shown in Fig. 4.16(a), Fig. 4.17(a) and Fig. 4.18(a), it can be concluded that ΔVth is

directly affected by ΔNit during entire dynamic stress period. However, it should be

noted that in Fig. 4.16(b), Fig. 4.17(b) and Fig. 4.18(b), the decreases in ΔVth do not

follow the consistent decrease in ΔS, especially for the case with passivation bias VG =

+1 V. It may be due to the electron trapping related to the positive hydrogen charges in the gate dielectric according to reactions (4-8). The B/A ratio of DNBTI is shown in Table. 4.1. The recovery reaction coefficients are similar between strained and unstrained cases.

Furthermore, the frequency dependences of NBT degradation were measured and shown in Figs. 4.19 to 4.21 with 50% duty cycle. ΔVth and ΔNit are plotted as a

function of frequency, as shown in Fig.4.17. Both ΔVth and ΔNit are strongly

dependent on frequency for devices with SiN capping layer. The results indicate that the stress under higher AC frequency shows lessΔVth andΔNit degradation. It is due to the

30

being recovered before entering the next stress state. Interface trap generation would be contained by increase AC stress frequency and Δ Vth is suppressed indirectly.

Reduction in NBT degradation for strained-channel devices under AC stress is more significant than the control case, mainly because the amount of broken SiH bonds with SiN capping layer is larger than the control sample.

31

Chapter 5

Conclusions

5.1 Conclusions

Using poly-SiGe as gate material to fabricate PMOSFETs has numerous advantages, including reduced gate depletion effect and improved gate sheet resistance. Compressive PECVD SiN layer could significantly enhance the drive current of PMOS devices at either room or raised operating temperatures (125 °C) due to increase of hole

mobility, as shown in our experiment. The degrees of mobility enhancement are enlarged as devices geometry is scaled down. Despite this merit, our results also indicate that the SiN capping may aggravate the NBTI characteristics. A high amount of hydrogen species contained in the PE-SiN layer as well as the strain energy stored in the channel may be the culprits for the worsened reliability. The interface trap density change and threshold voltage shift recover significantly during passivation periods. We’ve also observed that the strained channel device is influenced strongly by AC stress frequency.

32

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40

Control

sample

SiN 100nm

sample

SiN 300nm

sample

Passivation Layer

(Capping Layer)

TEOS 300nm

SiN 100nm +

TEOS 300nm

SiN 300nm +

TEOS 300nm

Table 2.1 Split table of capping layer structure and thickness

Passivation

Voltage

B/A

0V 0.29

Control

+1V 0.32

0V 0.27

SiN 100nm

+1V 0.29

0V 0.29

SiN 300nm

+1V 0.33

Table 4.1 B/A ratio of devices with different capping layers, at different passivation voltages during DNBTI stress

41

Fig. 2.1 Schematic cross section of the local strained channel PMOSFET

Fig. 2.2 TEM micrographs of device with channel length 0.55 µm

SiN

Source

Drain

TEOS

42

Fig. 2.3 Configuration for (a) gate-to-substrate, (b) gate-to-channel capacitance measurements

Fig. 2.4 Bias configuration of NBTI stressing

n-substrate p+ p+ p+ Gate n-substrate p+ p+ p+ Gate

G G

B B

S/D

S/D

(a) (b) n-substrate p+ Source p+ Drain p+ Gate

V

G

<0