Chapter 2 Review of Principle
2.4 RESURF LDMOSFET
High voltage devices usually require thick and low doped epitaxial layer, which makes them difficult to integrate with low voltage circuitry. Because of the high resistivity epitaxial layer, the on-state resistances of such devices is large. In 1979 Appels and Vaes suggested the reduced surface field (RESURF) concept [5]. The RESURF concept [6] gives the best trade-off between the breakdown voltage and the on-resistance of lateral devices. It has been shown that a lateral diode with a thin n type epitaxial layer on a lowly doped p substrate can give a higher breakdown voltage than a conventional lateral diode.
As shown in Figure 2.6 for a certain range of the n epitaxial (drift region) thickness and doping, the depletion region covers almost all the area of the thin epitaxial layer. It allows the depletion region to extend further than for the corresponding one-dimensional lateral diode without p substrate. As a result the surface field is decreased, and higher voltages can be applied to the devices. This is the well known RESURF effect. For an optimum doping and thickness of the n layer, a uniformly distributed voltage across the silicon surface in the drift region can be seen and a bulk breakdown voltage can be achieved. The breakdown voltage of lateral RESURF devices is limited by the substrate doping. The charge of the n layer determines the resistance of the drift region which is the most critical parameter of high-voltage devices. Together with the length of the drift region it will determine the on-resistance and current handling capability of the device.
Figure 2.6 Lateral RESURF structure full depletion
The RESURF technology has been one of the most frequently applied methods for the design of high-voltage lateral devices with low on-resistance [7,8,9]. It has been successfully used for lateral high-voltage devices such as diodes and LDMOS transistors for 20-1200V. This technology provides an efficient way to integrate high voltage devices with low voltage circuitry. The traditional RESURF structure is constructed by a lateral P+N diode (P+/N epitaxial) that defines the on-resistance characteristic of the device and a vertical P/N diode which supports a space charge depletion region enabling high BV (breakdown voltage).
The lateral BV of this structure depends on the N-epi net charge of the drift region, which is given when the N-epi net doping is integrated from the surface to the vertical PN junction (P substrate/N-epi) along the cut line A in Figure 2.6. Assuming that the N-epi layer is fully depleted with optimum drift dose, the maximum BV is determined
by the BV of the vertical PN diode (P substrate/N epitaxial). The drift region resistance is inversely proportional to the net charge in this region. Due to the vertical junction of the RESURF structure, a second electric field peak forms at the n+ cathode of the device. As shown in Figure 2.7 the electric field at the surface of the RESURF device (after full depletion) assumes a parabolic rather than a linear distribution which can be seen in conventional high voltage devices. It helps to reduce the electric field at the surface of the device during off-state.
Figure 2.7 Electric field comparison at the surface
The basic properties of RESURF structures are determined by the P substrate doping concentration (Csub), the N-epi layer doping concentration (N-epi), and the N-epi layer thickness (Tnepi). In the structure shown in Figure 2.6, an approximate net charge Qn of the N-epi layer (assuming uniform doping) is given by
n epi nepi
Q =N ×T ( 2.11 )
The BV performance depends significantly on the net charge Qn of the N-epi layer. The optimum Qn is found by assuming that the vertical depletion must reach the surface before the lateral junction breaks down. The vertical space charge width in the N-epi region extends and interacts with the lateral junction space charge region allowing the lateral depletion width to effectively span a larger distance compared to the case without the presence of the P substrate. As a result, the lateral electric field at the lateral P+N-epi junction is significantly reduced relative to the one-dimensional diode case, therefore enabling higher voltages to be applied. Consequently, to achieve a high BV in RESURF structures, it is required that the N-epi region is fully depleted before the lateral electric field reaches a critical value.
CHAPTER 3
Analysis and Dessssign of Trench LDMOSFET
In order to gain higher breakdown voltage of power MOSFET, conventional LDMOSFET is designed by needing to increase length of drift region. When length of drift region is getting longer, breakdown voltage and on-resistance are becoming larger.
This is unfavorable factor. Thus, we use Trench LDMOSFET to improve the performance of LDMOSFET. The main object of this thesis is Trench LDMOSFET.
The characteristic of the structure is to fill a SiO2 Trench in the drift region under the gate, which decrease on-resistance and increase breakdown voltage is better than conventional LDMOSFET. Gaining higher breakdown voltage and reducing area of device are anticipated by design of Trench LDMOSFET.
3.1 Structure Analysis of LDMOSFET
RESURF technology to gain high breakdown voltage, to change physical property, and decide to adopt one factor at a time, to observe electric property of cell pitch, substrate concentration, concentration and thickness of drift region, and concentration and thickness of P-base. Thus, the specification of LDMOSFET parameter include cell pitch (50um), P-substrate (1E14cm-3), concentration of drift region (4E14cm-3), depth of drift region (9um), concentration of P-base (1E15cm-3), depth of P-base (3um), and concentration of the source and drain (1E17cm-3) as shown in Figure 3.1.
Figure 3.1 Structure of LDMOSFET
3.1.1 Cell pitch
Cell pitch is getting large, and breakdown voltage is also higher, but cost must add, this method can not avoid. According to Figure 3.2 and Figure 3.3, length of LDMOSFET is becoming long, breakdown voltage and on-resistance are getting large at the same time.
P substrate Drift region (N-epi layer) P-Base
Figure 3.2 Breakdown voltage of cell pitch
3.1.2 Substrate Concentration
RESURF theorem can get up to effect of reducing surface electric field, and makes use of vertical full depletion region (P type substrate and N type drift region), the
junction takes place high electric field. When substrate concentration is smaller than critical concentration, drift region is not covered by upward depletion region, and can’t develop RESURF function. LDMOSFET under gate takes place breakdown because electric field of lateral depletion region of P-base and gate edge as shown in Figure 3.4.
When substrate concentration is greater than critical concentration, drift region is covered by upward depletion region, and device has RESURF function. LDMOSFET under gate and drain takes place breakdown because electric field of lateral depletion region of P-base and gate edge as shown in Figure 3.5. When substrate increases concentration, the depletion region of PN junction is getting large, breakdown voltage is also raising as shown in Figure 3.6. and Figure 3.7. By the two figure, and use one factor at a time, to observe breakdown voltage is 179V, in other words, the substrate concentration is 5E14cm-3, and gain breakdown voltage. But change of substrate concentration will increase production cost. Therefore, substrate concentration of Trench design is still 1E14cm-3, and this device has effect of junction isolation, to turn on-state, drain current don’t pass through substrate, substrate resistance is ignored that affects on-resistance.
Figure 3.4 Non-RESURF structure of LDMOSFET
Figure 3.5 RESURF structure of LDMOSFET Breakdown Voltage
BVdss= 33V
Substrate Concentration
=1E13cm-3
Breakdown Voltage BVdss= 153V
Substrate Concentration
=1E14cm-3
`
3.1.3 Concentration and Thickness of Drift Region
Width of depletion region has relations with concentration of drift region and substrate, substrate decides whether drift region is covered by upward depletion region.
If drift region is high concentration, it makes depletion region is getting small, electric field is getting large, substrate upward depletion region can not generate effective depletion, and causes under gate to take place breakdown as shown in Figure 3.8. If drift region is low concentration, width of substrate upward depletion region become large, RESURF performance is also getting better, and reverse voltage can gain high breakdown voltage. But concentration of drift region controls drift resistance, and it is getting high concentration, resistance of drift region is becoming small as shown in Figure 3.9.
Thickness of drift region affects RESURF technology, if it is too thick, substrate upward depletion region can’t cover whole drift region, and maximum electric field is under gate, to take place breakdown. When it is getting thin, substrate upward depletion region and lateral depletion region of P-base generate function, and reduce surface electric field of P-base, which avoids breakdown under gate, but electric field under drain is becoming large, in any case, this drift region (N-epi layer) is too thin, it causes breakdown under drain as shown in Figure 3.10 and Figure 3.11.
Figure 3.8 Breakdown voltage of concentration of drift region
0.E+00 2.E+14 4.E+14 6.E+14 8.E+14 1.E+15 1.E+15
Concentration of drift region (cm-3)
B re ak d o w n v o lt ag e (V )
0.E+00 2.E+14 4.E+14 6.E+14 8.E+14 1.E+15 1.E+15
Concentration of drift region (cm-3)
O n -r es is ta n ce ( m Ω -c m
2
)
Cell pitch= 30um
Figure 3.10 Breakdown voltage of epi depth
3.1.4 Concentration and Thickness of P-base
In this power MOSFET, the P-base region and the N+ source regions are diffused through a common window defined by the edge of the polysilicon gate. The name for this device is derived from this double-diffusion process. The P-base region is driven-in deeper than the N+ source. The difference in the lateral diffusion between the P-base and N+ source regions defines the surface channel region.
When a positive drain voltage is now applied, it reverse biases the P-base/N-drift region junction. This junction supports the drain voltage by the extension of a depletion layer on both sides. Due to the higher doping level of the P-base region, the depletion layer extends primarily into the N-drift region. Its doping concentration, depth and width must be chosen in accordance with the criteria established for avalanche breakdown of PN junction. A higher drain blocking voltage capability requires a lower drift region doping and a larger depth and width.
When concentration of the P-base region is getting high, breakdown voltage is also becoming large, but change of on-resistance is unapparent. If depth of the P-base region is getting deep, breakdown voltage is also becoming large as shown in Figure 3.12 to Figure 3.15.
Figure 3.12 Breakdown voltage of P-base concentration
Figure 3.13 On-resistance of P-base concentration
6.9 12
5.E+14 6.E+14 7.E+14 8.E+14 9.E+14 1.E+15 1.E+15
Concentration of P-base (cm-3)
B re ak d o w n v o lt ag e (V )
5.E+14 6.E+14 7.E+14 8.E+14 9.E+14 1.E+15 1.E+15
Concentration of P-base (cm-3)
O n -r es is ta n ce ( m Ω -c m
2
)
Cell pitch= 30um
Figure 3.14 Breakdown voltage of P-base depth
Figure 3.15 On-resistance of P-base depth
4.3 8
3.2 Disadvantage of RESURF LDMOSFET
Peak electric field of gate edge is form, and observe equipotential line of gate edge which is crowded as shown in Figure 3.16 [10]. When power device is off-state, the drain to gate have potential (Vdg). To estimate electric field (E) of gate edge (see Figure 3.17):
dg ˆ
E V a
= − L r
( 3.1 )
Where L is distant of gate to drain, which is proportional to length of drift region.
When length of drift region is too short, to cause electric field of gate and drain that is too large. Avalanche breakdown is easy to take place in under gate edge, this is because RESURF LDMOSFET can’t design short drift region.
The optimal case is obtained when the depletion region extends equally in the N-drift and P substrate regions. If the lateral distance is sufficient, breakdown occurs vertically in the semiconductor bulk under the N+ region. As shown in Figure 3.5 the electric field distribution of the optimized lateral diode, where the peak electric field can be seen under three position (source, gate, and drain edge). As shown in Figure 3.4 is not RESURF of LDMOSFET, and cause breakdown voltage become smaller.
Figure 3.16 Potential distribution of LDMOSFET (20um)
Figure 3.17 Electric field distribution of LDMOSFET (20um) Breakdown Voltage
BVdss= 39V
3.3 Advantage of Trench LDMOSFET
The main structure in this thesis, drift region of conventional LDMOSFET add oxide trench, is called Trench LDMOSFET as shown Figure 3.18. We choose silicon dioxide to do material of trench, which is high critical electric field (107V/cm), and it is 33.3 times electric field of silicon. Therefore, it bears higher electric field of gate edge.
Silicon dioxide and silicon match pretty well and process easily.
Figure 3.18 Structure of Trench LDMOSFET
In order to verify oxide trench to avoid breakdown of gate edge, and observe off state in Trench LDMOSFET which is 159V electric field of breakdown voltage. Trench LDMOSFET has a part of surface that is filled with silicon dioxide. Figure 3.19 is electric field of Trench LDMOSFET, and shows to keep away from gate edge, electric field is becoming smaller. Interface of silicon and silicon dioxide have great energy gap.
When Trench LDMOSFET is on state, electron can not punch through silicon dioxide,
P
+N
+N
+and electron that need detour silicon dioxide of trench move to drain. Design of oxide-trench etch part of drift region, and cause cross-section area of electron current which is getting smaller. Oxide trench cause resistance of drift region that is becoming larger. If drift region increases concentration, drain reduces the peak value of electric field (see Figure 3.20). The result of simulation prove this conjecture.
Figure 3.19 Electric field of Trench LDMOSFET Breakdown Voltage
BVdss= 209V
Ron,sp= 47.6mΩ-cm2
Epi concentration ( 6E14 cm-3 )
Figure 3.20 Electric field of Trench LDMOSFET
3.4 Design of Trench LDMOSFET
For power device, a good device owns characteristic of large breakdown voltage and small on-resistance, and at the same time a size of cell pitch designs emphasis on the whole efficiency, in other words, the power device is smaller, it will save us a lot of cost. A structure parameter of device is quite a few, it is very difficult to use Full factorial analysis. In order to understand change of physical property, and decide to adopt one factor at a time. Finally, we change parameter to observe relationship between Trench LDMOSFET and LDMOSFET.
Breakdown Voltage BVdss= 159V
Ron,sp=11.3mΩ-cm2
Epi concentration ( 3E15 cm-3 )
Trench LDMOSFET improves avalanche breakdown of LDMOSFET in gate edge.
Therefore, designing trench to increase breakdown voltage and reduce on-resistance effect.
3.4.1 Parameter definition
Designing power device has two parameter of electric property that is important, and defines breakdown voltage and on-resistance.
3.4.1.1 Breakdown voltage
In general, device operation is off state (Vg=0V), and increases drain voltage by degrees. When drain current is getting to 1x10-6 A, this device stands for breakdown state. We use simulation soft of device electric property (ISE TCAD_Dessis) [11,12,13]
which is two-dimension simulation program, width of device is defined 1um, the result of drain current (Id) is unit width of drain current (Id/1um). Because width of normal power device is about 10mm, we increase drain voltage make unit width of drain current (over1x10-10A/um) which enter breakdown state. At this time, drain voltage is also breakdown voltage. Breakdown voltage of device (as shown Figure 3.21) is 159V.
Figure 3.21 Breakdown voltage of Trench LDMOSFET
3.4.1.2 On-resistance
The on-resistance [14] of a Power MOSFET is a very important parameter because it determines how much current the device can carry for low to medium frequency applications. After being turned on, the on-state is defined simply as its on-state voltage divided by on-state current. When conducting current as a switch, the power dissipation in the power MOSFET during current conduction is given by:
2
D D D D on
P =I V =I R ( 3.2 ) 159V
VGS=0V
Expressed in terms of the chip area (A): operated in its linear region at a relatively small drain bias during current conduction.
The region of operation in Figure 3.22 have been labeled linear and saturated. To understand the difference, recall that the actual current path in a MOSFET is horizontal through the channel created under the gate oxide and then vertical through the drain. In the linear region of operation, the voltage across the MOSFET channel is not sufficient for the carriers to reach their maximum current density. The static on-resistance (Ron), defined simply as VDS/IDS, is a constant. To adopt VGS=5V and VDS=1V, and get drain current to calculate on-resistance. Thus specific on-resistance (Ron,sp) is 11.3mΩ-cm2.
Figure 3.22 Output Characteristics of Trench LDMOSFET VGS=5V
VDS=1V
Ron,sp=11.3mΩΩΩ-cmΩ 2
3.4.2 Fabrication of Trench LDMOSFET
Oxide trench can improve characteristic of LDMOSFET, and change structure of LOCOS (LOcal Oxidation Of Silicon) gain better efficiency. The process flow of Trench LDMOSFET is as shown in Table3.1 [15].
Table 3.1 Process procedure of Trench LDMOSFET 1 Lightly doped P-type substrate wafer<100> Figure 3.23 2 Growth of a heavily doped N-type epitaxial
layer
Figure 3.24
3 P-base creation with boron implantation and diffusion
1 Figure 3.25
4 Reactive ion etching(RIE) is performed to form trenches
5 Trench is filled with silicon dioxide 6 To polish surface by CMP
2 Figure 3.26
7 Depositing silicon dioxide(350Å) Figure 3.27
8 Depositing Poly-silicon layer(2000Å) to form gate patterning
3 Figure 3.28
9 Arsenic implantation is carried out to form S/D region
4 Figure 3.29
10 BF2 implantation is performed to create P-base contact
5 Figure 3.30
11 Depositing silicon dioxide
12 Contact window is opened for source/gate/drain
Figure 3.31
13 Aluminum is sputtered 14 Metal patterning
6
Figure 3.32
Figure 3.23 Process Flow Chart
Figure 3.24 Process Flow Chart
Figure 3.25 Process Flow Chart PSubstrate
1. <100> P type wafer
PSubstrate N-Drift Region
2. To Grow N type epi layer
3. Mask 1
-boron implantation and diffusion to form P-base PSubstrate
N-Drift Region Boron
Photo-resistance (PR)
Figure 3.26 Process Flow Chart
5. To deposite oxide in surface
P-Base 6. To deposite polysilicon
in surface
`
Figure 3.31 Process Flow Chart
P-Base 10. To deposite metal (Al)
Reuse Mask 6
3.4.3 Trench design
For LDMOSFET, breakdown voltage is positive relation with the drift region, and gains high breakdown voltage to make the longer drift region, which reduces cell pitch.
This is disadvantage of LDMOSFET, which can’t save cost and reduce device area.
Trench LDMOSFET [16,17,18,19] can reduce electric field of gate edge as shown in Figure 3.19, and can decrease length of the drift region. According to equation 3.1, electric field of gate edge is positive proportional to length of the drift region. When length of the drift region decreases, it causes electric field to become large as shown in Figure 3.17. Therefore, better trench design reduces electric field of gate edge.
3.4.3.1 Depth of Oxide Trench
In order to understand effect of oxide trench on Trench LDMOSFET, we adopt to analyze parameter of LDMOSFET, concentration of the drift region is 7E14cm-3, depth of the drift region is 10um, concentration of P-base is 1E15 cm-3, and depth of P-base is 5um. To use these conditions to change depth of oxide trench, and observe breakdown state. According to Figure 3.33 and Figure 3.34, depth of oxide trench is getting deep, breakdown voltage is also becoming large. In other words, oxide trench increases depth, the drift region is getting thin, electron pass through cross sectional area, which is becoming small, resistance of the drift region becomes large, and on-resistance is getting large.
Figure 3.33 Breakdown voltage of Trench depth
Figure 3.34 On-resistance of Trench depth 0
3.4.3.2 Position of Oxide Trench
The above-mentioned result point to breakdown voltage and on-resistance are controlled by depth of Trench LDMOSFET. After oxide trench analyzes depth, to discuss position of oxide trench, and understand breakdown voltage and on-resistance.
We use parameter of trench depth, and set trench depth (T) is equal to 5um as shown in Figure 3.35, trench width is 10um (L1+L2), to change L1 length (gate edge to left size of oxide trench), which is 0.5um, 1um, 1.5um, 2um, 2.5um, and 3um. L2 (gate edge to right size of oxide trench) length is changed by L1, the result is in Figure 3.36 and Figure 3.37. When L1 is getting large, breakdown voltage change just a little, on-resistance change just a little like breakdown voltage.
Figure 3.35 Structure parameter of Trench LDMOSFET
Figure 3.36 Breakdown voltage of L1 length
Figure 3.37 On-resistance of L1 length
Figure 3.37 On-resistance of L1 length