This dissertation is divided into five chapters. The contents in each chapter are described as follows.
In chapter 1, the history of power MOSFET about conventional MOSFET、
VMOSFET、DMOSFET、UMOSFET devices are introduced in this chapter.
In chapter 2, this section focus on review of principle of LDMOSFET.
In chapter 3, this section focus on analysis and design of Trench LDMOSFET.
In chapter 4, and use Taguchi Methods to improve best efficiency of higher voltage and lower on-resistance of Trench LDMOSFET.
In chapter 5, this section includes the conclusions and the future work of this study.
CHAPTER 2
Review of Principle
Power MOSFETs in power integrated circuits, in the main, to do function of the switch. When the switch is off-state, power device come into being open circuit, which bear higher reverse voltage to avoid breakdown. Besides, the switch is on-state, power device come into being short circuit, which can help current pass through, moreover on-resistance is becoming more and more low. It is important to improve the power device performance by optimizing on-resistance for a given area and a breakdown voltage. A cost effective and elegant method to utilize such a trade-off between on-resistance and breakdown voltage is to optimize the device layout.
2.1 Structure and operation of LDMOSFET
Power MOSFETs have been widely applied to power electronics owing to great semiconductor industry, and have vertical channel and lateral channel structures. The power MOSFET in this thesis is LDMOSFET (Laterally Diffused MOSFET).What is LDMOSFET [3], in other words, this is lateral DMOS. In general, DMOS is a vertical structure, as shown in Figure 2.1. It is different to have Drain on the substrate of DMOSFET between DMOSFET and LDMOSFET. But Drain is on the surface of LDMOSFET, as shown in Figure 2.2.
LDMOSFET is an asymmetric power MOSFET designed for high on-resistance
and high blocking voltage. These features are obtained by creating a diffused p type channel region in a low-doped n type drain region. The low doping on the drain side results in a large depletion layer with high blocking voltage. The channel region diffusion can be defined with the same mask as the source region, resulting in a short channel with high current handling capability. The relatively deep p type diffusion causes a large radius of curvature at the edges, which eliminates the edge effects. While the device name implies that the fabrication require a diffusion, the dopants can just as well be implanted and annealed. Diffusion can be used in addition to further increase the junction depth and radius of curvature. The device can be fabricated by diffusion as well as ion implantation. The p type region is formed first, followed by shallow p+ and n+ regions. The n+ regions provide both source and drain contact regions. The p+ region contacts the p type body, which is typically shorted to the source, and eliminating the body effect.
It is the same to have operation principle of LDMOSFET and conventional MOSFET. For n channel LDMOSFET, positive voltage on the gate is increasing, and then electron in the P-base are attracted, and form a channel. Finally, the electron take shape a route, which include source, channel, drift layer and drain.
Figure 2.1 Conventional structure of DMOSFET
Figure 2.2 Structure of LDMOSFET N+ Substrate
N-Drift Region N+
P-base
Source Gate
Drain
PSubstrate N-Drift Region N+
P-base
Source Gate
Substrate
N+ Drain
2.2 Breakdown of LDMOSFET
In power devices, large electric fields can occur both within the interior regions of the device where current transport takes place and at the edges of the devices. The voltage is supported across a depletion layer formed across either a PN junction, a metal semiconductor interface, or a metal oxide semiconductor interface. The electric field that exists across the depletion layer is responsible for sweeping out any holes or electrons that enter this region by the process of either space charge generation or by diffusion from the neighboring quasi-neutral regions. When voltage is increased, the electric field in the depletion region increases and the mobile carriers are accelerated to higher velocities. In the case of silicon, the mobile carriers attain a saturated drift velocity of about 1x107cm/sec. when the electric field becomes larger than 1x105V/cm.
In general, power devices cause breakdown which have 2 main kinds, Avalanche breakdown and Zener breakdown.
2.2.1 Avalanche Breakdown
Avalanche breakdown is caused by impact ionization of electron-hole pairs by carriers that have gained energy by accelerating in the high electric field in the depletion region of a reversed biased PN diode. The ionization rate is quantified by the ionization constants of electrons and holes, αn and αp [4]. These ionization constants are defined as the change of carrier density with position divided by the carrier density or:
M n
d =α Mdx ( 2.1 )
The ionization causes a generation of additional electrons and holes. In order to compute the BV, it is necessary to determine the condition under which the impact ionization achieves an infinite rate. Generation of electron-hole pairs due to impact ionization requires a certain threshold energy (approximately 3.6eV for electrons and 5.0eV for holes in silicon) and the possibility of acceleration of the energy of electrons and holes, i.e. wide space charge regions. If the width of the space charge region is larger than the mean free path of carriers, charge multiplication occurs, which can cause electrical breakdown.
Consider a reverse-biased parallel-plane N+P junction with a positive bias applied to the N+ region (see Figure 2.3). Under the influence of the electric field E in the depletion region, the electron will be swept towards the N+ region and the hole will be swept towards the P region. Using the definitions for the ionization coefficients, the hole will create (αpdx) electron-hole pairs after traveling a distance (dx) and the
electron will create (αndx) electron-hole pairs. The total number of electron-hole pairs
M(x) created in the depletion region by a single electron-hole pair generated at a
where W is the depletion layer width
Figure 2.3 Reverse biased pn junction
The integrations are performed along field lines through the depletion region. A solution of this integral equation is
following integral equals one
The left-hand side of equation ( 2.4 ) is known as the ionization integral. With the approximation given in the avalanche breakdown condition corresponds to
0 voltage and the breakdown voltage using the following empirical relation:
1
2.2.2 Zener Breakdown
Zener breakdown occurs in heavily doped PN junctions. The heavy doping makes the depletion layer extremely thin. So thin, in fact, carriers can’t accelerate enough to cause impact ionization. With the depletion layer so thin, however, quantum mechanical tunneling through the layer occurs causing current to flow. The temperature coefficient of the Zener mechanism is negative breakdown voltage for a particular diode decreases with increasing temperature. However, the temperature coefficient is essentially independent of the rated breakdown voltage, and on the order of -3 mV/K [4].
In a Zener diode either or both breakdown mechanisms may be present. At low doping levels and higher voltages the avalanche mechanism dominates while at heavy doping levels and lower voltages the Zener mechanism dominates. At a certain doping level and around 6 V for Si, both mechanism are present with temperature coefficients that just cancel. It is possible to make Zener diodes with quite small temperature coefficients.
Neither Zener nor Avalanche breakdown are inherently destructive in that the crystal lattice is damaged. However, the heat generated by the large current flowing can cause damage, so either the current must be limited and/or adequate heat sinking must be supplied.
2.3 On-Resistance of LDMOSFET
Power devices in power integrated circuits, in the main, to do function of the switch. When the switch is on-state, and get lower on-resistance. Therefore, designing power devices need to know combination of on-resistance, and can get effective design and analysis. In structure of LDMOSFET, on-resistance is combined by three main resistance [1], which channel resistance (Rch), accumulation resistance (Ra) and drift region resistance (Rd). Thus on-resistance is as follows.
on ch a d calculate the contribution from the channel, consider the resistance of LDMOSFET cell structure shown in Figure 2.4, The channel resistance (Rch) per cm2 for the linear cell structure is given by:
Where W is channel width Lch is channel length
µns is electron mobility of channel surface Cox is gate oxide of capacitance
Figure 2.4 Resistance of LDMOSFET
2.3.2 Accumulation Layer Resistance
The resistance of the accumulation layer (Ra) accounts for the current spreading from the channel into JFET region. The accumulation layer resistance is dependent upon the charge in the accumulation layer and the mobility for free carriers at the accumulated surface. Thus, the inference of accumulation layer resistance is similar to channel resistance. The accumulation layer resistance per cm2 is:
(
A)
Where LA is length of accumulation layer (from the edge of the P-base region to the right of the polysilicon gate (point A).
µnA is electron mobility of carrier accumulation of epitaxial layer surface.
2.3.3 Drift Region Resistance
Drift region is in cell structure of LDMOSFET, and have a low concentration of epitaxial layer. We regard LDMOSFET as MOSFET plus a resistance, which is drift region resistance (RD). Therefore, the drift region resistance is estimated by formula of resistance.
D
R L ρ A
= ( 2.10 )
Where ρD is resistivity of drift layer region.
L is length of electron path.
A is cross sectional area of electron pass through.
Figure 2.5 is potential distribution of LDMOSFET operate mode. In order to estimate drift layer resistance, and use formula of integration to compute length and cross sectional area of power line in the drift region.
Figure 2.5 Potential distribution of LDMOSFET
2.4 RESURF LDMOSFET
High voltage devices usually require thick and low doped epitaxial layer, which makes them difficult to integrate with low voltage circuitry. Because of the high resistivity epitaxial layer, the on-state resistances of such devices is large. In 1979 Appels and Vaes suggested the reduced surface field (RESURF) concept [5]. The RESURF concept [6] gives the best trade-off between the breakdown voltage and the on-resistance of lateral devices. It has been shown that a lateral diode with a thin n type epitaxial layer on a lowly doped p substrate can give a higher breakdown voltage than a conventional lateral diode.
As shown in Figure 2.6 for a certain range of the n epitaxial (drift region) thickness and doping, the depletion region covers almost all the area of the thin epitaxial layer. It allows the depletion region to extend further than for the corresponding one-dimensional lateral diode without p substrate. As a result the surface field is decreased, and higher voltages can be applied to the devices. This is the well known RESURF effect. For an optimum doping and thickness of the n layer, a uniformly distributed voltage across the silicon surface in the drift region can be seen and a bulk breakdown voltage can be achieved. The breakdown voltage of lateral RESURF devices is limited by the substrate doping. The charge of the n layer determines the resistance of the drift region which is the most critical parameter of high-voltage devices. Together with the length of the drift region it will determine the on-resistance and current handling capability of the device.
Figure 2.6 Lateral RESURF structure full depletion
The RESURF technology has been one of the most frequently applied methods for the design of high-voltage lateral devices with low on-resistance [7,8,9]. It has been successfully used for lateral high-voltage devices such as diodes and LDMOS transistors for 20-1200V. This technology provides an efficient way to integrate high voltage devices with low voltage circuitry. The traditional RESURF structure is constructed by a lateral P+N diode (P+/N epitaxial) that defines the on-resistance characteristic of the device and a vertical P/N diode which supports a space charge depletion region enabling high BV (breakdown voltage).
The lateral BV of this structure depends on the N-epi net charge of the drift region, which is given when the N-epi net doping is integrated from the surface to the vertical PN junction (P substrate/N-epi) along the cut line A in Figure 2.6. Assuming that the N-epi layer is fully depleted with optimum drift dose, the maximum BV is determined
by the BV of the vertical PN diode (P substrate/N epitaxial). The drift region resistance is inversely proportional to the net charge in this region. Due to the vertical junction of the RESURF structure, a second electric field peak forms at the n+ cathode of the device. As shown in Figure 2.7 the electric field at the surface of the RESURF device (after full depletion) assumes a parabolic rather than a linear distribution which can be seen in conventional high voltage devices. It helps to reduce the electric field at the surface of the device during off-state.
Figure 2.7 Electric field comparison at the surface
The basic properties of RESURF structures are determined by the P substrate doping concentration (Csub), the N-epi layer doping concentration (N-epi), and the N-epi layer thickness (Tnepi). In the structure shown in Figure 2.6, an approximate net charge Qn of the N-epi layer (assuming uniform doping) is given by
n epi nepi
Q =N ×T ( 2.11 )
The BV performance depends significantly on the net charge Qn of the N-epi layer. The optimum Qn is found by assuming that the vertical depletion must reach the surface before the lateral junction breaks down. The vertical space charge width in the N-epi region extends and interacts with the lateral junction space charge region allowing the lateral depletion width to effectively span a larger distance compared to the case without the presence of the P substrate. As a result, the lateral electric field at the lateral P+N-epi junction is significantly reduced relative to the one-dimensional diode case, therefore enabling higher voltages to be applied. Consequently, to achieve a high BV in RESURF structures, it is required that the N-epi region is fully depleted before the lateral electric field reaches a critical value.
CHAPTER 3
Analysis and Dessssign of Trench LDMOSFET
In order to gain higher breakdown voltage of power MOSFET, conventional LDMOSFET is designed by needing to increase length of drift region. When length of drift region is getting longer, breakdown voltage and on-resistance are becoming larger.
This is unfavorable factor. Thus, we use Trench LDMOSFET to improve the performance of LDMOSFET. The main object of this thesis is Trench LDMOSFET.
The characteristic of the structure is to fill a SiO2 Trench in the drift region under the gate, which decrease on-resistance and increase breakdown voltage is better than conventional LDMOSFET. Gaining higher breakdown voltage and reducing area of device are anticipated by design of Trench LDMOSFET.
3.1 Structure Analysis of LDMOSFET
RESURF technology to gain high breakdown voltage, to change physical property, and decide to adopt one factor at a time, to observe electric property of cell pitch, substrate concentration, concentration and thickness of drift region, and concentration and thickness of P-base. Thus, the specification of LDMOSFET parameter include cell pitch (50um), P-substrate (1E14cm-3), concentration of drift region (4E14cm-3), depth of drift region (9um), concentration of P-base (1E15cm-3), depth of P-base (3um), and concentration of the source and drain (1E17cm-3) as shown in Figure 3.1.
Figure 3.1 Structure of LDMOSFET
3.1.1 Cell pitch
Cell pitch is getting large, and breakdown voltage is also higher, but cost must add, this method can not avoid. According to Figure 3.2 and Figure 3.3, length of LDMOSFET is becoming long, breakdown voltage and on-resistance are getting large at the same time.
P substrate Drift region (N-epi layer) P-Base
Figure 3.2 Breakdown voltage of cell pitch
3.1.2 Substrate Concentration
RESURF theorem can get up to effect of reducing surface electric field, and makes use of vertical full depletion region (P type substrate and N type drift region), the
junction takes place high electric field. When substrate concentration is smaller than critical concentration, drift region is not covered by upward depletion region, and can’t develop RESURF function. LDMOSFET under gate takes place breakdown because electric field of lateral depletion region of P-base and gate edge as shown in Figure 3.4.
When substrate concentration is greater than critical concentration, drift region is covered by upward depletion region, and device has RESURF function. LDMOSFET under gate and drain takes place breakdown because electric field of lateral depletion region of P-base and gate edge as shown in Figure 3.5. When substrate increases concentration, the depletion region of PN junction is getting large, breakdown voltage is also raising as shown in Figure 3.6. and Figure 3.7. By the two figure, and use one factor at a time, to observe breakdown voltage is 179V, in other words, the substrate concentration is 5E14cm-3, and gain breakdown voltage. But change of substrate concentration will increase production cost. Therefore, substrate concentration of Trench design is still 1E14cm-3, and this device has effect of junction isolation, to turn on-state, drain current don’t pass through substrate, substrate resistance is ignored that affects on-resistance.
Figure 3.4 Non-RESURF structure of LDMOSFET
Figure 3.5 RESURF structure of LDMOSFET Breakdown Voltage
BVdss= 33V
Substrate Concentration
=1E13cm-3
Breakdown Voltage BVdss= 153V
Substrate Concentration
=1E14cm-3
`
3.1.3 Concentration and Thickness of Drift Region
Width of depletion region has relations with concentration of drift region and substrate, substrate decides whether drift region is covered by upward depletion region.
If drift region is high concentration, it makes depletion region is getting small, electric field is getting large, substrate upward depletion region can not generate effective depletion, and causes under gate to take place breakdown as shown in Figure 3.8. If drift region is low concentration, width of substrate upward depletion region become large, RESURF performance is also getting better, and reverse voltage can gain high breakdown voltage. But concentration of drift region controls drift resistance, and it is getting high concentration, resistance of drift region is becoming small as shown in Figure 3.9.
Thickness of drift region affects RESURF technology, if it is too thick, substrate upward depletion region can’t cover whole drift region, and maximum electric field is under gate, to take place breakdown. When it is getting thin, substrate upward depletion region and lateral depletion region of P-base generate function, and reduce surface electric field of P-base, which avoids breakdown under gate, but electric field under drain is becoming large, in any case, this drift region (N-epi layer) is too thin, it causes breakdown under drain as shown in Figure 3.10 and Figure 3.11.
Figure 3.8 Breakdown voltage of concentration of drift region
0.E+00 2.E+14 4.E+14 6.E+14 8.E+14 1.E+15 1.E+15
Concentration of drift region (cm-3)
B re ak d o w n v o lt ag e (V )
0.E+00 2.E+14 4.E+14 6.E+14 8.E+14 1.E+15 1.E+15
Concentration of drift region (cm-3)
O n -r es is ta n ce ( m Ω -c m
2
)
Cell pitch= 30um
Figure 3.10 Breakdown voltage of epi depth
3.1.4 Concentration and Thickness of P-base
In this power MOSFET, the P-base region and the N+ source regions are diffused through a common window defined by the edge of the polysilicon gate. The name for this device is derived from this double-diffusion process. The P-base region is driven-in deeper than the N+ source. The difference in the lateral diffusion between the P-base and N+ source regions defines the surface channel region.
When a positive drain voltage is now applied, it reverse biases the P-base/N-drift region junction. This junction supports the drain voltage by the extension of a depletion layer on both sides. Due to the higher doping level of the P-base region, the depletion layer extends primarily into the N-drift region. Its doping concentration, depth and width must be chosen in accordance with the criteria established for avalanche breakdown of PN junction. A higher drain blocking voltage capability requires a lower
When a positive drain voltage is now applied, it reverse biases the P-base/N-drift region junction. This junction supports the drain voltage by the extension of a depletion layer on both sides. Due to the higher doping level of the P-base region, the depletion layer extends primarily into the N-drift region. Its doping concentration, depth and width must be chosen in accordance with the criteria established for avalanche breakdown of PN junction. A higher drain blocking voltage capability requires a lower