Design of Trench LDMOSFET

For power device, a good device owns characteristic of large breakdown voltage and small on-resistance, and at the same time a size of cell pitch designs emphasis on the whole efficiency, in other words, the power device is smaller, it will save us a lot of cost. A structure parameter of device is quite a few, it is very difficult to use Full factorial analysis. In order to understand change of physical property, and decide to adopt one factor at a time. Finally, we change parameter to observe relationship between Trench LDMOSFET and LDMOSFET.

Breakdown Voltage BVdss= 159V

Ron,sp=11.3mΩ-cm²

Epi concentration ( 3E15 cm^-3 )

Trench LDMOSFET improves avalanche breakdown of LDMOSFET in gate edge.

Therefore, designing trench to increase breakdown voltage and reduce on-resistance effect.

3.4.1 Parameter definition

Designing power device has two parameter of electric property that is important, and defines breakdown voltage and on-resistance.

3.4.1.1 Breakdown voltage

In general, device operation is off state (Vg=0V), and increases drain voltage by degrees. When drain current is getting to 1x10^-6 A, this device stands for breakdown state. We use simulation soft of device electric property (ISE TCAD_Dessis) [11,12,13]

which is two-dimension simulation program, width of device is defined 1um, the result of drain current (Id) is unit width of drain current (Id/1um). Because width of normal power device is about 10mm, we increase drain voltage make unit width of drain current (over1x10^-10A/um) which enter breakdown state. At this time, drain voltage is also breakdown voltage. Breakdown voltage of device (as shown Figure 3.21) is 159V.

Figure 3.21 Breakdown voltage of Trench LDMOSFET

3.4.1.2 On-resistance

The on-resistance [14] of a Power MOSFET is a very important parameter because it determines how much current the device can carry for low to medium frequency applications. After being turned on, the on-state is defined simply as its on-state voltage divided by on-state current. When conducting current as a switch, the power dissipation in the power MOSFET during current conduction is given by:

2

D D D D on

P =I V =I R ( 3.2 ) 159V

VGS=0V

Expressed in terms of the chip area (A): operated in its linear region at a relatively small drain bias during current conduction.

The region of operation in Figure 3.22 have been labeled linear and saturated. To understand the difference, recall that the actual current path in a MOSFET is horizontal through the channel created under the gate oxide and then vertical through the drain. In the linear region of operation, the voltage across the MOSFET channel is not sufficient for the carriers to reach their maximum current density. The static on-resistance (Ron), defined simply as VDS/IDS, is a constant. To adopt V_GS=5V and VDS=1V, and get drain current to calculate on-resistance. Thus specific on-resistance (Ron,sp) is 11.3mΩ-cm².

Figure 3.22 Output Characteristics of Trench LDMOSFET V_GS=5V

V_DS=1V

Ron,sp=11.3mΩΩΩ-cmΩ ²

3.4.2 Fabrication of Trench LDMOSFET

Oxide trench can improve characteristic of LDMOSFET, and change structure of LOCOS (LOcal Oxidation Of Silicon) gain better efficiency. The process flow of Trench LDMOSFET is as shown in Table3.1 [15].

Table 3.1 Process procedure of Trench LDMOSFET 1 Lightly doped P-type substrate wafer<100> Figure 3.23 2 Growth of a heavily doped N-type epitaxial

layer

Figure 3.24

3 P-base creation with boron implantation and diffusion

1 Figure 3.25

4 Reactive ion etching(RIE) is performed to form trenches

5 Trench is filled with silicon dioxide 6 To polish surface by CMP

2 Figure 3.26

7 Depositing silicon dioxide(350Å) Figure 3.27

8 Depositing Poly-silicon layer(2000Å) to form gate patterning

3 Figure 3.28

9 Arsenic implantation is carried out to form S/D region

4 Figure 3.29

10 BF² implantation is performed to create P-base contact

5 Figure 3.30

11 Depositing silicon dioxide

12 Contact window is opened for source/gate/drain

Figure 3.31

13 Aluminum is sputtered 14 Metal patterning

6

Figure 3.32

Figure 3.23 Process Flow Chart

Figure 3.24 Process Flow Chart

Figure 3.25 Process Flow Chart PSubstrate

1. <100> P type wafer

PSubstrate N-Drift Region

2. To Grow N type epi layer

3. Mask 1

-boron implantation and diffusion to form P-base PSubstrate

N-Drift Region Boron

Photo-resistance (PR)

Figure 3.26 Process Flow Chart

5. To deposite oxide in surface

P-Base 6. To deposite polysilicon

in surface

`

Figure 3.31 Process Flow Chart

P-Base 10. To deposite metal (Al)

Reuse Mask 6

3.4.3 Trench design

For LDMOSFET, breakdown voltage is positive relation with the drift region, and gains high breakdown voltage to make the longer drift region, which reduces cell pitch.

This is disadvantage of LDMOSFET, which can’t save cost and reduce device area.

Trench LDMOSFET [16,17,18,19] can reduce electric field of gate edge as shown in Figure 3.19, and can decrease length of the drift region. According to equation 3.1, electric field of gate edge is positive proportional to length of the drift region. When length of the drift region decreases, it causes electric field to become large as shown in Figure 3.17. Therefore, better trench design reduces electric field of gate edge.

3.4.3.1 Depth of Oxide Trench

In order to understand effect of oxide trench on Trench LDMOSFET, we adopt to analyze parameter of LDMOSFET, concentration of the drift region is 7E14cm^-3, depth of the drift region is 10um, concentration of P-base is 1E15 cm^-3, and depth of P-base is 5um. To use these conditions to change depth of oxide trench, and observe breakdown state. According to Figure 3.33 and Figure 3.34, depth of oxide trench is getting deep, breakdown voltage is also becoming large. In other words, oxide trench increases depth, the drift region is getting thin, electron pass through cross sectional area, which is becoming small, resistance of the drift region becomes large, and on-resistance is getting large.

Figure 3.33 Breakdown voltage of Trench depth

Figure 3.34 On-resistance of Trench depth 0

3.4.3.2 Position of Oxide Trench

The above-mentioned result point to breakdown voltage and on-resistance are controlled by depth of Trench LDMOSFET. After oxide trench analyzes depth, to discuss position of oxide trench, and understand breakdown voltage and on-resistance.

We use parameter of trench depth, and set trench depth (T) is equal to 5um as shown in Figure 3.35, trench width is 10um (L1+L2), to change L1 length (gate edge to left size of oxide trench), which is 0.5um, 1um, 1.5um, 2um, 2.5um, and 3um. L2 (gate edge to right size of oxide trench) length is changed by L1, the result is in Figure 3.36 and Figure 3.37. When L1 is getting large, breakdown voltage change just a little, on-resistance change just a little like breakdown voltage.

Figure 3.35 Structure parameter of Trench LDMOSFET

Figure 3.36 Breakdown voltage of L1 length

Figure 3.37 On-resistance of L1 length 94

3.4.3.3 Length of Polysilicon Gate

According to simulation result of trench parameter, we adjust L1 (1um), trench width (L1+L2=10um), and trench depth (5um) to change length of polysilicon gate (Lgate), and observe breakdown voltage and on-resistance as shown in Figure 3.38 and Figure 3.39. When length of polysilicon gate is getting longer, this device increases breakdown voltage and reduces on-resistance. Because polysilicon gate edge is far away from the source, potential is on Silicon and Silicon dioxide, the drain (N⁺) and electric field of N drift region is too small to take place breakdown, and get higher breakdown voltage. The positive bias of polysilicon gate attracts electron to form channel of lower resistance on surface, while length of polysilicon gate is getting longer, this channel is also becoming long, and causes on-resistance to decrease.

Figure 3.38 Breakdown voltage of Polysilicon Gate length

Figure 3.39 On-resistance of Polysilicon Gate length 106