STI and Well implant formationSTI and Well implant formation
EOT 12A Gate oxide formationEOT 12A Gate oxide formation
Poly gate patterningPoly gate patterning
Post SiGe implant Post SiGe implant (As 25Kev 3e13cm (As 25Kev 3e13cm--2)2)
RTA (1000C) anneal RTA (1000C) anneal
MSA anneal (1200C, 500us)MSA anneal (1200C, 500us)
Nitride spacer formationNitride spacer formation
S/D SiGe recess and formationS/D SiGe recess and formation (high/low ratio of SiGe area to (high/low ratio of SiGe area to
whole wafer area)
STI and Well implant formationSTI and Well implant formation
EOT 12A Gate oxide formationEOT 12A Gate oxide formation
Poly gate patterningPoly gate patterning
Post SiGe implant Post SiGe implant (As 25Kev 3e13cm (As 25Kev 3e13cm--2)2)
RTA (1000C) anneal RTA (1000C) anneal
MSA anneal (1200C, 500us)MSA anneal (1200C, 500us)
Nitride spacer formationNitride spacer formation
S/D SiGe recess and formationS/D SiGe recess and formation (high/low ratio of SiGe area to (high/low ratio of SiGe area to
whole wafer area)
Figure 4.3.1. The S/D strained SiGe with different ratio of total SiGe area to whole wafer are designed and followed with As implant, RTA and MSA
Figure 4.3.2. The schematic plot of (a) low ratio of total SiGe area and (b) high ratio of total SiGe area to whole die area.
SiGe
Low ratio of SiGe area to whole wafer
SiGe
Low ratio of SiGe area to whole wafer
(a)
SiGe
High ratio of SiGe area to whole wafer
SiGe
High ratio of SiGe area to whole wafer
(b)
93
4. 4 Results and Discussion
4.4.1 Global effect: ratio of total SiGe area to whole wafer and its effect on wafer warpage with MSA
Fig. 4.4.1 shows that the pattern SiGe wafer bow height change was affecting by the ratio of total SiGe area to total wafer area with the following implant, RTA and MSA process.
For blanket wafer fully covered with SiGe, 100% ratio of total SiGe area, the wafer bow height of relaxed strained-SiGe with MSA revealed large value in tensile state and was gradually reduced while total SiGe area ratio was decreased. As we proposed the two factors caused defect formation in the underlying Si substrate while MSA was applied on the relaxed strained-SiGe.
Fig. 4.4.1 shows the pattern SiGe wafer warpage was affecting by the ratio of total SiGe area to total wafer area with the following implant, RTA and MSA
94
One is the larger CET of SiGe than that of Si, and the other is the lowered yield stress of relaxed strained-SiGe during high temperature. Therefore, the more SiGe area in the portion of wafer, the larger surface expansion and the higher wafer bow height.
As the ratio of total SiGe area was less than 10%, the wafer bow height was acceptable for the following lithographic limitation. Therefore, a well-designed ratio of total SiGe area to whole wafer area is important to avoid large wafer warpage in the integration of SiGe and MSA and get rid of lithographic limitation due to high wafer warpage.
4.4.2 Local effect: relation of SiGe area and defect formation in the underlying Si substrate with MSA
Fig 4.4.2 (a) exhibits the schematic plot of pattern wafer bow height change following process flow of SiGe, implantation, RTA and MSA. The ratio of total SiGe area to whole wafer area was controlled at around 2% to verify local SiGe area size effect on defect formation in the underlying Si substrate during MSA. The pattern SiGe wafer warpage was close flat after MSA and supposes that there was no defect formation in the underlying Si substrate due to the small value of wafer bow height. However, large SiGe area of 25um2 showed high defect density up to 2um depth in the underlying Si substrate after MSA as shown in the Fig 4.4.2 (b). In contrast, at the same pattern SiGe wafer the nearby small SiGe
95
Local SiGe area (um2) D e fect co u n ts ( ea )
Total SiGe area ratio = 2%0.2um2
Local SiGe area (um2) D e fect co u n ts ( ea )
Total SiGe area ratio = 2%0.2um2
Fig 4.4.2 (a) exhibits the schematic plot of pattern wafer bow height change following process flow of SiGe, implantation, RTA and MSA (b) defect formation in Si for large SiGe area (c) defect free in Si for small SiGe area.
Fig. 4.4.3 illustrates that the defect density counting per unit length at TEM image could dramatically decrease while local SiGe area was less than 0.2um2
SiGe
96
pad with area size around 0.02 um2 did not exhibit defect formation at all in the underlying Si substrate after MSA. It is obvious that the phenomenon of MSA on implanted strained-SiGe causing defect formation in the underlying Si substrate has SiGe area size dependency.
Fig. 4.4.3 illustrates that the defect density counting per unit length at TEM image could dramatically decrease while local SiGe area was less than 0.2um2. A well-designed rule of local SiGe area to avoid defect formation in the underlying Si substrate with the combination of SiGe and MSA process is very important for 28nm CMOSFET and beyond.
4.4.3 Simulated SiGe area effect on defect formation during MSA
Active SiGe area dependency: Simulated SiGe area size effect on SiGe strain was showed in Fig. 4.4.4. When source/drain SiGe was surrounding by SiO2 – like the stress absorber, SiGe/Si interface stress was reduced. Stress absorption effect of the SiO2 was feeble in large SiGe area size to have higher SiGe/Si interface stress, which was unstable and was prone to form misfit dislocation by post-SiGe implant and RTA, resulting in defect injection when MSA was applied. The active SiGe area size dependency on defect formation during MSA was further discussed to verify the correction of mechanism that we have proposed in chapter 2.4
From the mechanism we proposed in chapter 2.4, there are two factors affecting defect formation in the underlying Si substrate while MSA was applied on the relaxed strained-SiGe.
97
SiGe area : W=0.1 m ~5 m Length=0.5 m Ge% is fixed
1.0 1.4 1.8 2.2
0.01 0.1 1 10