The degree of strained-SiGe relaxation remarkably affected the channel stress and the formation of the defects in the underlying Si substrate as well as the wafer bending while the MSA was applied to the S/D strained-SiGe in 28nm PMOSFET devices. Low-energy As implantation to cause shallower Rp in the strained-SiGe surface induced low-level 11% of relaxation and did not generate defects in the underlying Si, because the remaining strained-SiGe was sufficiently thick to resist wafer bending by the tensile stress associated with MSA thermal treatment. However, moderate relaxation 51% of the strained-SiGe by medium-energy As implantation revealed the partly relaxed SiGe with lower shear stress of yielding deformation was unable to withstand the significantly compressive stress of the surface expansion to form defects in the underlying Si substrate during MSA heating and more surface contraction of high CTE of SiGe to cause over-bending in the tensile state during MSA cooling. In addition, the 75% relaxation of the SiGe layer by high-energy implantation would for lots of interfacial misfit dislocations and low-density of coherent bonding with Si substrate. The highly relaxed strained-SiGe film is then deformed freely along with the externally thermal stress direction and would not cause any residual strain to
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the underlying Si substrate during the MSA thermal cycle. Therefore, proper implantation conditions were chosen to provide a relaxation-less strained-SiGe and boost the channel stress, achieving a 10% current gain. The defect-free underlying Si in millisecond-annealed 28 nm PMOSFETs devices exhibits a decrease in the junction leakage current by four orders of magnitude.
We have concluded that the degree of strained-SiGe relaxation significantly caused the wafer bending as well as the defect formation in the underlying Si substrate when MSA was applied to the relaxed strained-SiGe wafers. In either cases of post-SiGe implant or post-SiGe soak annealing or in-situ Ge at.% resulting in the relaxation of strained SiGe, low relaxation less than 10% did not cause large SiGe wafer bending during the MSA. Upon the MSA, the medium relaxation level indeed caused significant SiGe wafer bow height from the compressive to tensile state as well as the defect formation in the underlying Si substrate.
A design rule of S/D SiGe with different active area sizes to form the defects in the underlying Si substrate during MSA has been also proposed for the 28nm PMOSFETs. As the ratio of total SiGe area to whole wafer was less than 10%, the wafer bow height was less than 100 um after the MSA and it was acceptable for the following lithographic limitation.
Therefore, a well-designed ratio of global SiGe area to whole wafer area is critical to prevent the large wafer warpage in the integration of SiGe and MSA and get rid of the lithographic limitation. We also came out the critical SiGe area to avoid defect formation in the underlying
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Si substrate during the MSA. With the local SiGe area size smaller than 0.2um2, upon the MSA, the defect formation in the underlying Si and the junction leakage of SiGe to the substrate could be controlled as low as those for non-MSA process. Therefore, a well-designed rule of global SiGe area ratio to whole wafer and local SiGe area size were proposed to avoid defect formation in the underlying Si substrate and junction leakage for 28nm CMOSFETs volume production.
A novel technique of creating an embedded SiGe channel (ESC) structure without Si surface passivation shows a pFETs Gm gain of 26% as well as Ion_Ioff performance gain of 8% higher than those of conventional strained Si pFETs with the source/drain (S/D) SiGe for the 28 nm pMOSFETs. Better S/D resistance (Rsd) in the resistance versus gate length plot and improved swing slop of Id_Vgs plot indicate the higher mobility in the ESC devices.
According to the XPS analysis, the gate oxide leakage and the reliability of the constant voltage stress were also examined to recognize the superior SiGe/SiO2 interface with only the Si-O bonding and no Ge-O bonding. The novel etch process to create the ESC structure is thus considered as a very promising technique for the 28 nm pMOSFETs and future N/P SiGe channel in FinFETs.
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Chapter 7
Future Prospects
There are some interesting and important topics that are valuable for the future further research about the strained-SiGe relaxation induced defect formation in the underlying silicon substrate and a significant wafer bending during the millisecond annealing (MSA) process for 28 nm node PMOSFETs and beyond.
(1) To figure out if or not there is process window for the MSA temperature independency to show defect-free in the underlying Si substrate whiles the S/D SiGe and MSA were combined in the integrated process of CMOS and beyond. Lowering MSA temperature would provide a small thermal stress to avoid defect formation in the underlying silicon substrate and wafer bending.
(2) Further thinking about the studying if there is orientation dependency with MSA (Flash anneal or Laser scanning anneal (LSA)), varying LSA scanning direction on relaxed strained-SiGe to come out defect-free in the underlying Si and result in better junction leakage.
As we knew that different SiGe lattice orientation to LSA scan direction would show different immunity to MSA induced wafer warpage, which can widen LSA temperature window. In general, (100) lattice plane displays high immunity to strain deformation than that of (110)