具有源極汲極應變矽鍺與嵌入式矽鍺通道之28奈米和下世代P型金氧半場效電晶體特性之研究

國

立

交

通

大

學

電子工程學系 電子研究所

博 士 論 文

具有源極汲極應變矽鍺與嵌入式矽鍺通道之 28 奈米

和下世代 P 型金氧半場效電晶體特性之研究

Study on the Electrical Characteristics of the PMOSFETs with the Strained

SiGe S/D and Embedded SiGe Channel for the 28 nm Node and Beyond

研 究 生：游明華

指導教授：鄭晃忠 教授

具有源極汲極應變矽鍺與嵌入式矽鍺通道之 28 奈米

和下世代 P 型金氧半場效電晶體特性之研究

Study on the Electrical Characteristics of the PMOSFETs with the Strained

SiGe S/D and Embedded SiGe Channel for the 28 nm Node and Beyond

研 究 生：游明華 Student：Ming-Hua Yu

指導教授：鄭晃忠 博士 Advisor：Dr. Huang-Chung Cheng

國 立 交 通 大 學

電子工程學系 電子研究所

博 士 論 文

A Dissertation

Submitted to Department of Electronics Engineering and Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Doctor of Philosophy in

Electronics Engineering

June 2013

Hsinchu, Taiwan, Republic of China

i

具有源極汲極應變矽鍺與嵌入式矽鍺通道之 28 奈米

和下世代 P 型金氧半場效電晶體特性之研究

研究生：游明華 指導教授：鄭晃忠 博士

國立交通大學電子工程學系暨電子研究所

摘要

在此論文中，分別針對應變源極汲極矽鍺與嵌入式矽鍺通道等二項工程提出不同結 構與技術改善以提昇 28 奈米 P 型電晶體元件特性。針對應變源極汲極矽鍺，我們探討 製程參數所造成的鬆弛性矽鍺對 P 型電晶體元件特性之通道應力衰減與矽基材缺陷形成 的影響。針對嵌入式矽鍺通道，我們提出一種新穎製程方式可製作具高載子移動率，不 須矽表面覆蓋卻有著較佳的閘極氧化層完整性(Gate Oxide Integrity, GOI)，來應用於 28 奈米電晶體元件特性之改善。 首先，針對源極汲極的矽鍺電晶體，對於製程流程上的離子佈值與毫秒式退火造成 應變矽鍺的部份鬆弛性，所造成的通道應力衰減與缺陷形成於底下矽基材內而造成大量 漏電，同時也造成晶片的大量彎曲變形有礙於黃光曝光的製程之 28 奈米 P 型電晶體元 件特性。低能量砷離子佈值僅造成 11% 應變矽鍺的部份鬆弛性，在後續的毫秒式退火 下 並不會造成缺陷形成於矽基材上而造成大量漏電，同時也不會造成晶片的大量彎曲 變形。然而中能量砷離子佈值僅造成 51% 應變矽鍺的部份鬆弛性，在後續的毫秒式退 火下，會造成缺陷形成於矽基材上而造成 100 倍大量漏電，同時也造成晶片的大量彎曲 變形從壓應變到拉伸應變。藉由離子佈值種類的改變由砷變成磷離子和砷離子佈值的順 序變化可以得到機乎完全應變無鬆弛的矽鍺而有 10% 趨動電流的改善。進一步高能量砷 離子佈值造成 75% 應變矽鍺的大部份鬆弛性，在後續的毫秒式退火下，又不會造成缺

ii 陷形成於矽基材上，同時也不會造成晶片的大量彎曲變。此一現象了解與探討，有助於 28 奈米 P 型電晶體元件特性的改善。 針對應變矽鍺的鍺含量與後續退火條件來探討其所成應變矽鍺的部份鬆弛性，在後 續的毫秒式退火下，是否也會造成缺陷形成於矽基材上以及晶片的大量彎曲變形。經由 實驗得知 27%的鍺含量和 600 秒 800 度都會造成應變矽鍺的中等部份弛性，在後續的毫 秒式退火下，也會造成缺陷形成於矽基材上與晶片的大量彎曲變形。因此不管是用離子 佈值或長時間退火亦或應變矽鍺的鍺含量高低所造成應變矽鍺的中等部份鬆弛性，都會 造成缺陷形成於矽基材上與晶片的大量彎曲變形從壓應變到拉伸應變，因此好的矽鍺後 製程設計，對 28 奈米電晶體元量產顯得重要。另外，了解矽鍺與毫秒式退火造成缺陷 現象是否與矽鍺面積圖案有關而顯得格外重要。由實驗得知矽鍺佔種面積 10%以上時會 有嚴重的晶片彎曲變形，當矽鍺區域面積大於 0.2 毫米平方時，即時矽鍺佔種面積 10% 以下時，也會有缺陷形成於矽基材內且有大量漏電。所以一個良好的矽鍺面積設計對 28 奈米電晶體元量產顯得格外重要。 其次，針對通道工程的改善，我們提出一種新穎製程方式可製作具高載子移動率的 嵌入式矽鍺通道，不須矽表面覆蓋卻有著較佳的閘極氧化層完整性(Gate Oxide Integrity, GOI)，來應用於 28 奈米電晶體元件特性之改善。藉由源極汲極凹槽蝕刻時，緊接著額 外的氣體蝕刻將(110)晶格面移除而停在(111)晶格面，並將源極與汲極打通而形成懸空的 閘極與氧化層。由於此蝕刻氣體並不會與氧化層反應，所以可以再利用矽鍺沉積得到矽 鍺通道。如此的結構可以得到較佳的載子移動率約 26%電導通率增益(Gm)與 8% Ion_Ioff 增益特性改善。同時閘極氧化層並不會被破壞且矽鍺不會與閘極氧化層反應而形成鍺氧 化層，所以可以得到與矽氧化層相同的完整性與低漏電，如此一個新穎的結構可用於 28 奈米電晶體以及更進階的三維電晶體元件特性之改善 最後，本論文所提之應變源極汲極矽鍺與嵌入式矽鍺通道等二項工程改善不僅在 28 奈米電晶體展現優越的特性及其在下世代也極具潛力。

iii

Study on the Electrical Characteristics of the PMOSFETs with

the Strained SiGe S/D and Embedded SiGe Channel

for the 28 nm Node and Beyond

Student : Ming-Hua Yu Advisor : Dr. Huang-Chung Cheng

Department of Electronics Engineering &

Institute of Electronics

National Chiao Tung University

ABSTRACT

In this thesis, the strained SiGe source/drain (S/D) and the epitaxial SiGe channel of the

PMOSFETs with the technique improvement and novel structures have been systematically

investigating to boost device performance for the 28 nm node and beyond. For the former one,

the impacts of the process parameters on the relaxation of the strained-SiGe induced channel

stress degradation and defect formation in the under-layered Si substrate are discussed. For

the later one, a novel technique to create the suspending stacked gate and subsequently to fill

in an embedded SiGe channel (ESC) between the gate oxide and under-layered Si substrate

has been proposed for the first time to enhance the drive current gain of the 28 nm

PMOSFETs.

iv

strained-SiGe relaxation caused by implantation significantly affected the channel stress and

the formation of defects in the underlying Si substrate as well as wafer bending when the

millisecond anneal (MSA) was applied to the S/D strained-SiGe in 28nm PMOSFET devices

for resistance reduction. Proper implantation species selection from Arsenic (As) to

Phosphorus (P) was chosen to provide a relaxation-less strained-SiGe and enhanced the

channel stress. It could achieve a 10% higher current gain. The defect-free underlying Si in

the millisecond-annealed 28 nm PMOSFETs devices exhibits a decrease in the junction

leakage current by four orders of magnitude. A new approach to modify the implantation

conditions was also developed to achieve a relaxation-less strained-SiGe layer and defect-free

underlying Si substrate for the 28nm PMOSFETs.

For the process parameter effects on the strained-SiGe relaxation, the formation of the

induced defects in the underlying Si substrate associated with the interaction of the partly

relaxed strained-SiGe layer and subsequent millisecond annealing (MSA) has been explored.

Three kinds of methods including the post-SiGe implant, post-SiGe soak anneal and in-situ

Ge at.% effect that were used to boost the device performance were investigated how to avoid

the strained-SiGe relaxation and defect formation in the underlying Si during the MSA. All of

them revealed the same phenomena that the medium relaxation of the strained SiGe either by

the post-implant, post-soak anneal, or Ge content would cause significant wafer bending

v

considered to avoid wafer bending and defect formation for the advanced PMOSFETs.

A design rule of the strained SiGe S/D with different active area sizes to form the defects

in the underlying Si substrate during the MSA has been also proposed for the 28nm

PMOSFETs. As the ratio of total SiGe area to whole wafer was less than 10%, the wafer

bending was acceptable small for the following lithographic limitation. Therefore, a

well-designed ratio of global SiGe area to whole wafer area is important to avoid large wafer

warpage in the integration of the SiGe and MSA. We also came out the critical SiGe area to

avoid the defect formation in the underlying Si substrate during the MSA. With the local SiGe

area size smaller than 0.2um2, upon MSA there is no defect formation in the underlying Si

and the junction leakage could be controlled as low as those of the non-MSA process.

Therefore, a well-designed ratio of the global SiGe area to the whole wafer and local SiGe

area size were proposed for the 28nm CMOSFETs volume production.

Secondly, for the channel engineering of epitaxial strained SiGe, a novel technique to

create the suspending stacked gate oxide and subsequently to fill in an embedded SiGe

channel (ESC) between the gate oxide and under-layered silicon substrate has been proposed

for the first time to fabricate the 28nm PMOSFETs. Without the Si surface passivation on the

embedded SiGe channel, such an ESC structure could achieve p-FETs transconductance (Gm)

gain of 26% higher as well as Ion_Ioff performance gain of 8% higher than those of

vi

resistance versus gate length plot and improved swing slop of Id_Vgs plot indicates the higher

mobility in the ESC devices. Moreover, the off-state gate current and reliability stressing of

the ESC structure are also comparable to the conventional ones. From the X-ray photoelectron

spectrum (XPS) analysis, only the Si-O bonding and no Ge-O bonding at the SiGe/SiO2

interface could be accounted for this superior gate oxide integrity for the ESC and strained Si

structure. Therefore, such a novel technique with an ESC structure is very promising for the

28 nm pMOSFETs devices and beyond.

Finally, the strained SiGe source/drain (S/D) and the novel embedded SiGe channel of

the PMOSFETs with the structure and technique improvement are promising to boost device

vii

誌 謝

僅以此論文獻給我的父母親游允發先生與黃秀英女士，感謝你們多年來的養育之 恩，我才得能無後顧之憂地完成學業；感謝我的太太鄧佳芝無怨無悔的支持，我才得以 全心全力於學業上；同時也謝謝我的姊姊游玉玲、游玉霜、游玉芬女士，感謝你們在我 求學期間對整個家的付出。 特別感謝我的論文指導教授鄭晃忠老師，恩師在為人處事及論文研究上的熱心指 導，都讓我獲益良多，我才得能順利取得博士學位，在此表達由衷感謝。 感謝實驗室的學長、學弟妹們，有了你們在生活上及實驗上相互的扶持與砥礪，漫 長的研究生涯才能顯得更多采多姿。特別感謝與我一起打拼的學弟們，廖大傳學弟、吳 俊諭學弟、王昭龍學弟，有了你們的相互扶持與合作此論文才能順利完成。另外，更感 謝實驗室其他夥伴在生活與實驗上的幫忙、討論與打氣，才得以讓實驗更順利完成，其 中包含了李逸哲學弟、蔡萬霖學弟、胡采綸助理、張加聰學弟、李宏顯學弟、黃昱智學 弟、胡明哲學弟…等，在此一併致謝。 因實驗大部分都是在台灣積體電路股份有限公司完成，非常感謝研發部門李資良副 處長與葉凌彥經理於實驗計畫上的支持與大力協助，並感謝研發部門同事李志鴻副理、 黃泰鈞副理、蔡邦彥副理、王立廷同事、林育樟同事、李彥儒同事與李承瀚同事之討論 與相互勉勵，以及台灣大學廖銘漢助理教授於實驗上的鼎力協助。 最後感謝所有曾經幫助過我、支持過我及關心過我的朋友及長輩們。

viii

Contents

Abstract (in Chinese)

Abstract (in English)

Acknowledgements

Contents

Table Lists

Figure Captions

i

i

iii

vii

viii

xiv

xv

i

Chapter 1 Introduction

………..………..… ………...…..1

1.1 Overview of SiGe alloy for semiconductor………1

1.2 Why SiGe ...2

1.3 Global strain by SiGe on Si substrate.…………..…..………..………..3

1.4 Local strain by SiGe at source/drain region.……….………..5

1.5 Measurement techniques for strain by XRD and Raman scattering………...8

1.6 Roadmap of epitaxial SiGe for PMOSFETs ………...………..10

1.7 Motivation………...12

1.8 Thesis organization………..……….………….…...15

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Chapter 2 The investigation for the underlying Si defects induced by the

relaxation of the strained-SiGe source/drain following the

millisecond annealing (MSA) for the 28nm PMOSFETs…….…21

2.1 Introduction……….………..………21

2.2 Motivation ………...24

2.2.1 Why we need S/D SiGe for 28 nm device performance...24

2.2.2 Why we need MSA for 28 nm device performance...26

2.3 Experiments………...30

2.3.1 Fabrication process – S/D SiGe first prior to implant...………….……...30

2.3.2 Fabrication process – S/D SiGe last …………..………...31

2.4 Results and Discussion………..…32

2.4.1 Defect formation in the underlying Si for the SiGe S/D and MSA…..…..32

2.4.2 Effect of Dopant species on strain relaxation of SiGe and device performance………38

2.4.3 Effect of Implant sequence on strain relaxation of S/D SiGe and device performance………....43

2.5 Mechanism of defect formation in the under-layered Si substrate for the relaxation of strained SiGe and MSA……… ………...45

2.6 Summary………...…………60

xi

Chapter 3 Post-Implant, Thermal and Ge at.% dependency on the Strained

SiGe Relaxation Induced Defects in the Underlying Si and Wafer

Bending with the MSA………...69

3.1 Introduction……….….……….69

3.2 Motivation...…...71

3.3 Fabrication of post-SiGe implant, soak anneal and varying Ge content for the

strained SiGe S/D with following MSA………..………...73

3.4 Results and Discussion………...………..75

3.4.1 Effect of Implant on relaxation of strained SiGe………...…….77

3.4.2 Effect of In-situ doped Ge content on relaxation of strained SiGe………80

3.4.3 Effect of Post-SiGe soak anneal on relaxation of strained SiGe…..……82

3.5 Summary……….……….84 References………..………..……….………….…...85

Chapter 4 Pattern Dependency of Strained SiGe Relaxation Induced Defects

in the underlying Si and Wafer Bending with the MSA

……...……87

4.1 Introduction……….….……….….…87

4.2 Motivation………...………90

xii

4.4 Results and Discussion……….…..……93

4.4.1 Global effect: ratio of total SiGe area to whole wafer and its effect on wafer warpage with MSA……….93

4.4.2 Local effect: relation of SiGe area and defect formation in the underlying Si substrate with MSA………94

4.4.3 Simulated SiGe area effect on defect formation during MSA………96

4.4.4 SiGe area effect on junction leakage with MSA……….98

4.5 Summary……….……….100

References………..………..……….………….…...101

Chapter 5 Novel Technique to Fabricate 28 nm p-MOSFETs Possessing

Gate Oxide Integrity on the Embedded SiGe Channel without

Silicon Surface Passivation………...105

5.1 Introduction……….….………105

5.2 Motivation ………106

5.3 Fabrication of Embedded SiGe Channel for 28nm PMOSFETs …...109

5.4 Results and Discussion………117

5.4.1 Method of Electrical Parameter Extraction……….117

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PMOSFETs………..…… 120

- Boron diffusion in ESC device...120

- Transconductance and Total Resistance performance of ESC devices...122

- Id_Vgs and Id_Vds characterization of ESC devices…………...125

5.4.3

Simulation of the 28 nm Embedded SiGe Channel (ESC) PMOSFETs..127

5.4.4 Gate oxide integrity of the 28 nm ESC PMOSFETs..………..………… 129

5.4.5 Leakage current performance of the 28 nm ESC PMOSFETs….……… 131

5.4 Summary………..………133

References………..………..……….………...134

Chapter 6 Summary and Conclusions……….……….139

Chapter 7 Future Prospects………..…….143

Publication Lists……….………147

Patent Lists……….…...…………149

xiv

Table Lists

Table 5.3.1 The activation energy of etching away [110] is the lowest among [100] and [111] lattice planes………99

xv

Figure Captions

Chapter 1

Figure 1.3.1 The global strain formation by SiGe at blanket substrate with tensile Silicon on relaxed SiGe, which shows high defect density (Welser, J. et.al, IEDM, 1992)...………...4 Figure 1.4.1 The local strain by SiGe at source/drain region with uniaxial strain, which

shows almost fully strained SiGe and very low defect density (Thompson, S. et.al. IEDM 2002).………...5 Figure 1.4.2 (a) Si_0.8Ge_0.2 shows large lattice constant than silicon. (b) fully strained SiGe on

the silicon substrate (not equilibrium state)………..6 Figure 1.4.3 (a) equilibrium state of blanket strained SiGe on Si and wafer bending (b)

schematic plot of strained SiGe in the S/D region (Thompson, S. et.al. IEDM 2002).………7 Figure 1.4.4 The local compressive stress by SiGe at source/drain region with uniaxial strain

along <110>, and tensile stress for the other two directions (Lim, Ji-Song et. al, TED, 2004) ...………..………..…7 Figure 1.4.5 NMOS and PMOS preference strain direction and performance impact………..7

Figure 1.5.1 The XRD shows silicon peak and SiGe epitaxial layer with good fringe profile.

(Kelin J. et. al, ECS Trans. 2010)………..8 Figure 1.6.1 The Raman spectra of SiGe epitaxial layer on the silicon substrate (Kelin J. et.

xvi

al, ECS Trans. 2010)………...…10 Figure 1.7.1 The epitaxial SiGe and source/drain recess profile evolution for PMOSFETs and

beyond (James, D. et al. CICC, 2012)…………...……….….11

Chapter 2

Figure 2.1.1 The strained-SiGe Ge fraction and temperature effect on strained thickness (D.C. Houghton, et. al. J. Appl. Phys. 1991)...22 Figure 2.1.2 The S/D strained SiGe structure and its uniaxial stress to channel (Thompson, S.

et.al. IEDM 2002).……...23 Figure 2.1.3 The strained-SiGe Ge content effect on hole mobility enhancement (D.C. Houghton, et. al, ICPS 2004)…....………....23 Figure 2.2.1 The strained-SiGe Ge fraction and channel strain for technology node (Kelin J. et. al, ECS Trans. 2010)….………...25 Figure 2.2.2 The mobility loss between theory and experiment for various Ge content..…25 Figure 2.2.3 The Rs performance under scaling junction depth for technology node (S. D. Kim, et. al. IEDM, 2005)...…26 Figure 2.2.4 The spacer resistance dominates 58% of total resistance of PFET (S. D. Kim, et. al., IEDM, 2005)...……….………....…27 Figure 2.2.5 Solid solubility of Boron reaches saturation at high temperature (T. Ito, et. al.

SSDM, 2001)...…..……27 Figure 2.2.6 Anneal temperature and time effect on Boron diffusion length………..……..28 Figure 2.2.7 The surface heating of laser anneal enables to show millisecond anneal with

xvii

less diffusion (B. J. Cho, et. al. Int. Workshop Junction Technology, 2004)…28 Figure 2.3.1 The Process flow of the source/drain SiGe followed by implantation, then

subsequent MSA was conducted.………..30 Figure 2.3.2 The Process flow of implantation followed by the S/D SiGe, then subsequent

MSA was conducted………..……31 Figure 2.4.1 The implanted SiGe PMOSFETs device with RTA and MSA processes

exhibits higher junction leakage than that of those without implanted SiGe or millisecond anneal device……….……32 Figure 2.4.2 The TEM of the implanted SiGe wafer with the RTA and MSA process shows high defect density in the relaxed SiGe layer as well as in the underlying Si substrate..………..……34 Figure 2.4.3 Simulated MSA wafer temperature profile and exhibited large temperature

gradient close wafer surface.……….34 Figure 2.4.4 Small temperature ramp-up and ramp-down on implanted SiGe..…………...35 Figure 2.4.5 TEM showed defect-free in the underlying Si under small thermal gradient on implanted strained SiGe.……….……….…..35 Figure 2.4.6 Change in bow height of strained-SiGe wafer associated with following implantation, RTA and subsequent MSA. A fully strained-SiGe sample directly underwent MSA, exhibited no change in bow height. ….…..………...37 Figure 2.4.7 The combination of implanted strained SiGe and MSA form defects in the

underlying Si substrate. ….………...37 Figure 2.4.8 Simulated that implant species arsenic (As) and phosphorus (P) at the

xviii

comparable implant energy and concentration caused different degrees of damage in the strained SiGe layer………...39 Figure 2.4.9 The As implant dosage effect on PAI layer formation in SiGe….………….39 Figure 2.4.10 The relaxation of strained-SiGe is a function of dopant impurities, determined from the XRD rocking curve…..…..………..35 Figure 2.4.11 Raman measurements (wave number shifts) indicated the relaxation of strained-SiGe is associated with post implanted species, As and P, and their effects on the Si channel stress in Si………...41 Figure 2.4.12 Drive current, Ion-Lmin was affected by the implanted As and P induced

damage effect in the strained-SiGe layer, which causes various degrees of strain relaxation upon the RTA and MSA…..………...………..41 Figure 2.4.13 Improvement in the P+/n well junction leakage by the post-SiGe implantation of species, P, reduces the relaxation of strained-SiGe and yields a defect-free underlying Si substrate upon RTA+MSA……..…..………...42

Figure 2.3.14 The Process flow of implantation followed by the S/D SiGe, then subsequent MSA was conducted………44

Figure 2.4.15 Improvement of Ion-Ioff by the change in sequence of SiGe and implantation. Implantation prior to SiGe deposition exhibited less strain relaxation and a higher channel stress………..………...44 Figure 2.4.16 Upon MSA, implantation following the SiGe process sequence results in low strain relaxation and few defects in the underlying Si, and consequently improved junction leakage………46

xix

Figure 2.4.17 High-resolution X-ray diffraction reciprocal space maps (HR XRD RSMs) and TEM of strained-SiGe and underlying Si following implantation under various energy and RTA and MSA, associated with various strained-SiGe relaxation (a) No defect formation for 11% relaxation of strain SiGe. (b) Defects in the underlying Si for 51% strained-SiGe relaxation. (c) 75% relaxation shows the almost completely relaxed strained-SiGe with weak diffraction peak, and defect-free in the underlying Si………...47 Figure 2.4.18 Upon MSA, TEM image showed that relaxed strained-SiGe caused injection of defects into underlying Si………..………...…48 Figure 2.4.19 Correlation between relaxation of strain SiGe and injection of defects,

determined from wafer bow height and full width at half maximum (FWHM) of Si XRD peak……….49 Figure 2.4.20 the shear stress of yielding point of silicon is linearly dependent on the

annealing temperature (S.P. Nikanorov, et. al., Materials Science and Engineering, 2006)………....53 Figure 2.4.21 the second moment of inertia shows large over-bending while external loading over critical point (L. Zhang et. al. NSTI-Nanotech, 2006)………..54 Figure 2.4.22 (a) Real-time micro-second camera image of wafer warpage change associated with as-grown SiGe and the MSA temperature ramp-up and cool down. (b) the metrology concept of how to in-situ measure wafer warpage……….55 Figure 2.4.23 (a)(b) microscope of lattice deformation during post-implant, RTA and MSA temperature heat-up………...55 Figure 2.4.23 (c)(d) microscope of lattice deformation and wafer bending during MSA

xx

Figure 2.4.24 Schematic plot of various implantations Rp to thickness of SiGe layer change in wafer bow height and resultant injection of defects in underlying Si substrate………..………..59

Chapter 3

Figure 3.1.1 Single dislocation energy while dislocation formed in SiGe layer (J.Y. Tsao, et.al. PRL, 1986)………...70 Figure 3.1.2 Dislocation formed in SiGe for energy required in equilibrium (J.Y. Tsao, et.al.

PRL, 1986) ...………...70 Figure 3.1.3 Critical thickness of SiGe Ge content for different lattice plane (111), (110) and (100) (J.Y. Tsao, et.al. PRL, 1986)...………....…..71 Figure 3.2.1 The strained-SiGe Ge fraction and temperature effect on strained SiGe

thickness and its strained SiGe TEM image (D.C. Houghton, et. al, JAP, 1994).………72 Figure 3.2.2 Dislocation propagation at high post-SiGe anneal temperature and its TEM

image (D.C. Houghton, et. al, JAP, 1994)………...…………72 Figure 3.3.1 Process flow of the relaxation of strained SiGe associated to (a) various implant conditions, (b) various Ge contents SiGe, and (c) various soak anneal time…...……….74 Figure 3.4.1 Bow height change of strained-SiGe wafer associated with following implant, RTA and subsequent MSA, causing large SiGe wafer bending. A fully strained-SiGe sample directly underwent MSA, exhibited no wafer

xxi

bending ....………...…77 Figure 3.4.2 Correlation between the relaxation of strained SiGe and injection of defects,

determined from wafer bow height...………...….…..77 Figure 3.4.3 Bow height change of four Si wafers with following Si1-xGex deposition (x=0.2,

0.27, 0.33 and 0.44), implant of Arsenic, spike rapid anneal (RTA), and laser MSA annealing………..………79 Figure 3.4.4 Correlation between the relaxation of strained SiGe and wafer bow height after

laser MSA annealing...…….………..79 Figure 3.4.5 Upon MSA, correlation of bow height change and post-SiGe various soak

thermal annealing causing relaxation of strained-SiGe. Medium relaxation of strained-SiGe by post-SiGe soak annealing also caused defect formation in the underlying Si substrate……….81 Figure 3.4.6 Upon MSA, different degree of strained-SiGe relaxation caused by post soak anneal (a) 12% relaxation of strained SiGe did not show defects in Si (b) 36% relaxation of strained SiGe showed defects in the underlying Si……….…..81 Figure 3.4.7 The schematic plot of in-situ Ge content, soak anneal and implant effect on

defect formation in the underlying Si during MSA...……..82

Chapter 4

Figure 4.1.1 Critical mesa size vs Ge concentration with a SiGe thickness of 100 nm. Solid symbols indicate the buckled films, and open symbols indicate the unbuckled

xxii

films (C.Y. Yu, et. al. J. Appl. Phys. 2006)………88 Figure 4.1.2 Optical micrograph images of varying dimension of Si0.8Ge0.2 layers on the

viscous oxide after thermal oxidation at 960 °C for 6 minutes. (C.Y. Yu, et. al. J. Appl. Phys. 2006)………...………..89 Figure 4.2.1 (a) The structure of implated SiGe to form P/N junction. (b) high dislocation of SiGe sample caused high junction leakage current (Geert Eneman, et.al. APL. 2005)………...………...91 Figure 4.3.1 The S/D strained SiGe with different ratio of total SiGe area to whole wafer are designed and followed with As implant, RTA and MSA………..92 Figure 4.3.2 The schematic plot of (a) low ratio of total SiGe area and (b) high ratio of total

SiGe area to whole die area……….…92 Figure 4.4.1 It shows the pattern SiGe wafer warpage was affecting by the ratio of total SiGe area to total wafer area with the following implant, RTA and MSA…………...93 Figure 4.4.2 (a) exhibits the schematic plot of pattern wafer bow height change following process flow of SiGe, implantation, RTA and MSA (b) defect formation in Si for large SiGe area (c) defect free in Si for small SiGe area………95 Figure 4.4.3 illustrates that the defect density counting per unit length at TEM image could dramatically decrease while local SiGe area was less than 0.2um2…………..95 Figure 4.4.4Simulated size effect of SiGe strain under the same Ge% (a) W=5um (b) W=0.2um and both SiGe length=0.5um ………97 Figure 4.4.5 Simulated stress at SiGe/Si interface as a function of the size of SiGe area…..97 Figure 4.4.6MSA induced junction leakage current at different size of the active SiGe area……….………...99

xxiii

Chapter 5

Figure 5.1.1 (a) Channel stress was dramatically decreased as the S/D recess depth and the S/D SiGe dimension are scaled down. (b) Inevitably mobility degradation and device performance degradation with gate length scaling (Geert Eneman, et. al. TED, 2006)………106 Figure 5.2.1 (a) the schematic structure of the SiGe channel with a thin Si cap layer (b) SiGe channel shows high effective mobility than that of Si channel at the same effective field. (F. Andrieu, et. al. EDL, 2006)………108 Figure 5.2.2 (a) effective mobility of SiGe channel is dependent on the thickness of thin Si cap (b) Dit is also dependent on the thickness of thin Si cap layer. (F. Andrieu, et. al. EDL, 2006)……….………..110 Figure 5.3.1 The channel direction was changed from [100] to [110] for pMOSFET device performance boosting………110 Figure 5.3.2 A conventional reactive ion etching process (RIE), named as dry etch-1 and

(110) lattice plane of sidewall appeared………110 Figure 5.3.3 illustrates the design of the embedded SiGe channel by defining the various depth of dry etch-1, Y, then obtaining the corresponding SiGe channel……112 Figure 5.3.4 The suspending SiGe channel depth, Z versus S/D Si recess depth, Y………113 Figure 5.3.5 shows the 3-D profile of embedded SiGe channel and S/D SiGe region……...114 Figure 5.3.6 shows the 2-D profile of embedded SiGe channel and S/D SiGe region…….114 Figure 5.3.7 TEM picture shows the embedded SiGe channel (ESC) structure……….115

xxiv

Figure 5.3.8 The good crystallinity of ESC layer on blanket wafer was characterized by X-ray diffraction spectrum (XRD)………115 Figure 5.3.9 The following nitride removal and LDD implant on the ESC structure……….116 Figure 5.3.10 The following main nitride spacer was conducted on the ESC structure as well

as S/D implant………116 Figure 5.4.1 blanket-SiGe layer exhibits a smaller Boron out-diffused length around 3.5nm than that in Si substrate……….120 Figure 5.4.2 Under compressive strain, interstitial sites in lattice were reduced, and vacancy sites were increased (P.R. Chidambaram, et. al, TED, 2006)………...121 Figure 5.4.3 Boron was an interstitial diffuser then Boron diffusion was retarded under

compressive strain of epitaxial SiGe layer (P.R. Chidambaram, et. al, TED, 2006)………121 Figure 5.4.4. The ESC device demonstrates slightly better or comparable Vth to that of the conventional strained Si pFETs with the Source/Drain (S/D) SiGe devices…122 Figure 5.4.5 The ESC device shows 26% pFET Gm gain higher than that of the conventional strained Si pFETs with the Source/Drain (S/D) SiGe devices….………….…123 Figure 5.4.6 Rlin as a function of gate length showing mobility enhancement for ESC pFETs

device………..……….124 Figure 5.4.7 Ion-Ioff characteristic of PFET devices showing a performance improvement

gain of 8% for ESC wafers. No other strain element such as compressive stressed nitride liner was used in either the control or the ESC devices……..124 Figure 5.4.8 Ids-Vgs characteristic of 28nm Lg PFET with the control wafer and the ESC

xxv

Figure 5.4.9 Ids-Vds characteristic of 28nm Lg PFET with the control wafer and the ESC device. ……….………126 Figure 5.4.10 Simulates the hole mobility of the ESC structure and S/D SiGe structure. The

epitaxial SiGe layer sharing more Si channel shows higher channel Si stress induced mobility enhancement………..128 Figure 5.4.11 The channel stress is dependent of Si region, X, intra-spacing of source to drain recess, created by Si lateral etch-2……….128 Figure 5.4.12. It shows the XPS analysis data and indicates no Ge-O bonding observed for the

grown SiGe layer on the SiO2, which means only the Si-O bonding is observed

in our ESC device. ……….………130 Figure 5.4.13. ESC device shows comparable Gate oxide leakage performance with the

strained Si pFETs because there is no GeOx composition during SiGe

deposition according to the XPS analysis……….…..132 Figure 5.4.14. The constant voltage stress of the ESC device shows the same delta Vth shift

with the strained Si pFETs with the S/D SiGe. No GeOx induced further Dit increment for ESC pFETs. ……….………132

1

Chapter 1

Introduction

1.1 Overview of SiGe alloy for semiconductor

For the past few decades, continuous focus on Moore’s Law transistor scaling has

provided increasing CMOS transistor performance and density. First stated in 1965, Moore’s

law describes the technology advancement over the past 40 years which has allowed the

number of transistors on a chip to double about every two years [1]. This phenomenal progress has been made possible by continual downscaling of the metal-oxide-semiconductor

field-effect transistor (MOSFET) to smaller physical dimensions. MOSFETs have the

remarkable feature that as they become smaller they also become cheaper, consume less

power, become faster, and enable more functions per unit area of silicon. As a result, denser

silicon integrated circuits (ICs) can be realized, offering superior performance at reduced cost

per function for the advanced next technology generation.

For much of this time, Moore’s Law transistor scaling meant classic scaling, where oxide

thickness (Tox), transistor length (Lg) and transistor width (W) were scaled by a constant

factor (1/k) in order to provide a delay improvement of 1/k at constant power density.

2

by the use of performance enhancers (such as strain and high-k metal gate). The literature has

reported the significant role that SiGe has played in the past on enhancing CMOS transistor

performance, provide some information on present and developing uses of SiGe for CMOS

scaling, and speculate on the role that SiGe will play in future CMOS technology generations

[2-3]

1.2 Why SiGe

As we knew that Ge material shows higher electron and hole carrier mobility than those

of Si material. Ge and Si present their drift electron mobility 3900, 1500 cm2/V-s,

respectively, and 1900 and 490 cm2/V-s for drift hall mobility. Mobility is simply related

to carrier inter-scattering time and effective mass in semiconductor material. Let’s

discuss how Ge atoms and Si atoms demonstrate different effective mass in the

semiconductor. Consider 1-dimension periodic atom with potential, U, to affect carrier

transport in the series of atoms. Assume carrier wave function follow Schrödinger time

independent equation, then the wave function is reduced to the relationship of energy and

space. In order to follow continuous boundary conditions of carrier transport at the

atomic potential well, a relation of energy (E) and momentum (K) is established, so

3

gap between two energy states. However, for semiconductor material, such as Ge and Si

atoms, they show 2U of band gap among two energy states at the boundary, lower one is

valance band, the upper one is conduction band. One can obtain 1-D E-K diagram to

determine the curvature of conduction band, which indicates effective mass of carrier.

For Ge, the curvature of conduction band valley is smaller than that of Si. Therefore, Ge

shows small effective mass than that of Si resulting in higher mobility than Si.

1.3 Global strain by SiGe at substrate

Biaxial tensile strain is of particular interest for NMOS silicon channels. Strain can be

introduced by epitaxial growth of lattice mismatched Si on SiGe [4-5]. Because the Si lattice

is smaller than the SiGe (or Ge) lattice, the Si layer will be stretched in two directions

(biaxially). This biaxial stretching places the channel in biaxial tension and breaks the

symmetry of the six-fold conduction band valleys. The out-of-plane valleys (lower transport

mass) drop in energy, thus electrons move to populate these lower mass valleys. Furthermore,

the energy separation between valleys is increased, reducing scattering between bands and

valleys. The work in this area was done by Welser in 1992, when he first quantified the strain

enhancement for NMOS in strained Si on relaxed SiGe. This was followed with a series of

comparative studies with both strained and unstrained Si surface channels. That repopulation

4

stress at high fields. Strained Si on relaxed SiGe is just one of several process options for

obtaining biaxial strain using Si/SiGe systems as shown in Fig.1.3.1.

However, in the past decade, in the most recent technology nodes, much effort has been

directed towards increasing the carrier mobility and thus improving Ion by biaxial strain

engineering. The wafer-level strain methods such as tensile-stressed Si on relaxed Si1-xGex did

not make their way to high volume production due to high defect density in the underlying

SiGe layer, which was not favorable for junction leakage. It is difficult to obtain a relaxed

Si1-xGex buffered layer without dislocation formation and propagation into to upper tensile

silicon layer where electrons transport.

SiGe

Si

SiGe

Si

Relaxed SiGe

Grading SiGe

Si sub.

Tensile Si

SiGe

Si

SiGe

Si

Relaxed SiGe

Grading SiGe

Si sub.

Tensile Si

Relaxed SiGe

Grading SiGe

Si sub.

Tensile Si

Figure 1.3.1 The global strain formation by SiGe at blanket substrate with tensile Silicon on relaxed SiGe, which shows high defect density (Welser, J. et.al, IEDM, 1992)

5

1.4 Local strain by SiGe at source/drain region

Another method of implementing SiGe/Si system in the semiconductor to achieve

strained silicon is uniaxial compressive stress, which is along <110> channel direction and

that is of particular interest for PMOS silicon channels as shown in Fig.1.4.1. Uniaxial strain

can be produced by growing lattice mismatched SiGe inside Si source-drain regions. Because

the SiGe lattice is larger than the Si lattice, and because the source-drain regions run parallel

to the channel, the SiGe layer will push on the source-drain regions (and thus the channel) in

only one direction as shown in Fig.1.4.2 and Fig.1.4.3 [6-8]. This single direction pushing

places the channel in uniaxial compression and both warps and splits the valence band

structure of silicon. The band warping produces improved effective transport mass for the

heavy hole band. The uniaxial stress further increases the light-hole to heavy-hole band

separation reducing the inter-band scattering. Uniaxial strain along <110> channel direction

has a significant advantage over biaxial strain due to the presence of shear strain components

which are responsible for strong anisotropic warping of the bands leading to repopulation of

carriers to the band structure regions with the lighter transport mass. Hence, a strained SiGe at

the source/drain region provide a uniaxial compressive stress to Si channel and push other two

directions to become tensile stress due to poison ratio effect which is preferred for PMOS

6

Figure 1.4.1 The local strain by SiGe at source/drain region with uniaxial strain, which shows almost fully strained SiGe and very low defect density (Thompson, S. et.al. IEDM 2002).

Figure 1.4.2 (a) Si0.8Ge0.2 shows large lattice constant than silicon. (b) fully

7

Figure 1.4.3 (a) equilibrium state of blanket strained SiGe on Si and wafer bending (b) schematic plot of strained SiGe in the S/D region (Thompson, S. et.al. IEDM 2002).

Figure 1.4.4 The local compressive stress by SiGe at source/drain region with uniaxial strain along <110>, and tensile stress for other two direction.(Lim, Ji-Song et. al, TED, 2004)

Figure 1.4.5 NMOS and PMOS preference strain direction and performance impact (Lim, Ji-Song et. al, TED, 2004)

8

Therefore, a fully strained SiGe at the source/drain region with low interfacial defect density demonstrates a uniaxial compressive stress to Si channel and provide huge PMOS device performance boosting and its low defect density make it easy to implement at advanced CMOSFETs process and volume production.

1.5 Measurement techniques for strain by XRD and Raman

scattering

X-ray diffraction (XRD) and Raman scattering are the most common techniques for assessing strain on large area and nano-beam and convergent beam diffraction (NBD and

CBED) are the most common techniques used for assessing strain within the channel region,

but not mature yet for strained-SiGe measurement.

In an X-ray diffraction measurement, the sample is mounted on a goniometer and rotated Figure 1.5.1 The XRD shows silicon peak and SiGe epitaxial layer with good

9

XRD uses Bragg scattering at x-ray wavelengths to determine the configuration of

atoms in a crystalto produce a diffraction pattern. XRD can determine epitaxial layer in-plane

and out of plane strain components through analysis of symmetric and asymmetric diffraction

patterns as shown in Fig.1.5.1. For SiGe samples of interest, XRD can determine the Ge

content in buffer and graded layers, the strain of SiGe buffer and epitaxial layer and determine

dislocation type and density. However, XRD cannot measure small structures, has limited

depth resolution and poor sensitivity to ultrathin films/surface layers.

Raman scattering is the inelastic scattering of photons from vibration–induced phonon

modes in a material. Raman scattering is a two–photon process (hωlaser -hωscattered = hωphonon)

whose probability is dependent on the polarizability change in the bond during phonon

motion [9]. A laser source is typically used for Raman spectroscopy and the recorded

spectrum shows the scattering intensity relative to the shift in frequency of the laser. In

crystalline materials such as silicon and SiGe, the presence of stress causes a shift of phonon

peak positions as shown in Fig.1.6.1. The magnitude and direction of the shift can be

correlated to the amount and sign (compressive/tensile) of the strain. By accessing the Ge-Ge,

Si-Ge and Si-Si phonon modes one can derive Ge content and strain independently for SiGe

systems including Si epitaxial layers. Inherently Raman is an indirect measure of the lattice

constant(s) of the system and suffers from phonon broadening effects such as laser heating.

10

significantly better spot size (~1 micron), and delivers improved surface sensitivity

(dependent on laser wavelength).

1.6 Roadmap of epitaxial SiGe for PMOSFETs

In order to maintain the historical 17% per year performance improvement rate, various

novel processes and materials have been introduced to the bulk Si-MOSFET structure. Figure

1.7.1 shows the insertion of the new materials for Intel’s logic PMOSFET technologies. While

the use of strain as a performance enhancer is expected to continue as a key contributor to the

CMOS scaling roadmap. Epitaxial SiGe was used at Source/drain region of PMOSFET device

performance enhancement for the first time for 90nm technology. Then source/drain recess

shape was modified to boost pFETs device performance from 65nm to 32nm. A 3-D device

structure was implemented from 22nm. After that, the most intriguing future use of Ge or Figure 1.6.1 The Raman spectra of SiGe epitaxial layer on the silicon substrate.

11

SiGe in CMOS scaling is as a high mobility replacement for the Si channel. Recall that Ge

was the primary transistor material from the invention of the transistor in 1947 until the 1960s,

when MOS became technologically important. The two most critical reasons for switching

from Ge to Si for early MOS technology remain the two most critical issues today; namely the

poor quality of GeO2 compared to SiO2 and the smaller band gap of Ge compared to Si. The

critical changes between 1960 and 2010 leading to reconsideration of Ge channels are: 1.

advent of manufacturable high-k technologies, 2. decreasing voltages of modern products, and

3. development of highly quantum confined devices, which increase the effective band gap.

Competitive dielectric thicknesses without degrading mobility, the key challenge with

Ge (and SiGe) is that both industry and academic data show rapid degradation in mobility

N90 N65 N45/40 N32/28 N22/20 N10 (CICC), 2012 IEEE

High density & high performance PFETs NFETs N14 (IMEC) 2012 (Intel) N65 (IBM) N45 (Intel) 90nm N90 N65 N45/40 N32/28 N22/20 N10 (CICC), 2012 IEEE

High density & high performance PFETs NFETs N14 (IMEC) 2012 (Intel) N65 (IBM) N45 (Intel) 90nm

Figure 1.7.1 The epitaxial SiGe and source/drain recess profile evolution for PMOSFETs and beyond. (James, D. et al. CICC, 2012)

12

with decreasing electrical oxide thickness. The primary model for this degradation is poor

quality germanium oxide at the Ge/dielectric interface. Thus, the goal is to create a high

quality interface between the dielectric and the SiGe [10-14].

Scaling CMOS to and beyond the 22 nm node will probably require structural changes to

the planar silicon transistor and/or use of high-mobility channel material. The advanced

transistor structures such as multi-gate FET (MuGFET) is seen as potential replacements for

the bulk MOSFET because of their inherent superior electrostatic integrity. Another promising

alternative is the adoption of germanium (Ge) as the channel material. p-channel

Ge-MOSFETs have been proposed for highly-scaled high-performance technology due to

higher bulk mobility of holes in Ge.

1.7 Motivation

Epitaxial SiGe at source/drain (S/D) region for pFETs drive current enhancement has

been pursued aggressively in scaled CMOS technologies and significant carrier mobility

enhancement at strained Si channel have been reported. Increasing Ge concentration in the

S/D SiGe region is a straightforward method without extra process flow / profile change and

device parameter tuning to boost device performance as PFETs scaling down. However, Ge

content is inevitable to continuous increment in the S/D SiGe due to the critical thickness

13

the interface of SiGe and Si substrate. Hence, for high Ge content at S/D region, strain loss

due to misfit dislocation formation at the SiGe/Si substrate made real carrier mobility lower

than that of theoretical fully strain. In order to meet target of device performance for the

technology generation, suppressing the dislocation formation of epitaxial SiGe at S/D region

caused by post-SiGe implantation and thermal budget is very important for 28nm CMOS

volume production.

Since we would investigate the implant species effect on S/D strained SiGe relaxation as

well as implantation sequence effect and resultant defect formation once strained SiGe was

relaxed by post process. Meanwhile, how strain loss of S/D SiGe affected device performance.

On the other hand, to investigate in more detail the impact of MSA on the leakage current of

embedded SiGe S/D junctions with SiGe area size dependency is very important. Particular

emphasis is to come out a well-designed rule of the S/D strained SiGe area with MSA process

to avoid wafer large warpage and defect formation. The resultant design rule of active SiGe

area can obtain a as low junction leakage as that of non-MSA process or non-SiGe process to

volume production of 28nm CMOSFET and beyond.

In order to further boost device performance in 28nm PMOSFETs and beyond, another

approach to channel strain engineering is SiGe channel, which was considered as a promising

candidate in the nano pMOSFETs for the performance boost-up. As we knew that higher

14

in the SiGe channel is good candidate to boost device performance. We would demonstrate a

novel embedded SiGe channel (ESC) structure composed of strained SiGe channels without

extra Si surface passivation to show potentially superior hole mobility and superior gate oxide

15

1.8 Thesis Organization

In this thesis, various structures and techniques are studied for the fabrication of

high-performance 28nm PMOSFETs through the source/drain (S/D) and channel engineering

of epitaxial strained SiGe. In addition, the process parameters to impact of strained-SiGe

relaxation induced channel stress degradation and defect formation on device performance are

investigated as well.

In chapter 2, for source/drain engineering of epitaxial strained SiGe, the degree of

strained-SiGe relaxation caused by implantation importantly affected the channel stress and

the formation of defects in the underlying Si substrate as well as wafer bending when

millisecond anneal (MSA) was applied to the S/D strained-SiGe in 28nm PMOSFET devices.

In chapter 3, For process parameter effects on strained-SiGe relaxation, the formation of

the induced defects in the underlying Si substrate associated with the interaction of the partly

relaxed strained-SiGe layer and subsequent millisecond annealing (MSA) has been explored.

Three kinds of methods including post-SiGe implant, post-SiGe soak anneal and in-situ Ge

at.% effect that were used to boosting device performance were investigated how to avoid

strained-SiGe relaxation and defect formation in the underlying Si during MSA.

In chapter 4, a design rule of S/D SiGe with different active area size to form defects in

16

In chapter 5, for channel engineering of epitaxial strained SiGe, a novel technique to

create the suspending stacked gate oxide and subsequently to fill in an embedded SiGe

channel (ESC) between the gate oxide and under-layered silicon substrate has been proposed

for the first time to fabricate the 28nm PMOSFETs.

Finally, summary and conclusions as well as recommendation for further research are

17

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gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain

engineering”, Electron Devices Meeting, pp. 251-254, 2003.

[14] James, D. ; Ottawa, K., “Intel Ivy Bridge unveiled - The first commercial tri-gate, high-k,

21

Chapter 2

The investigation for the underlying Si defects

induced by the relaxation in strained-SiGe

layer following the millisecond annealing

for the 28nm PMOSFETs

2.1 Introduction

Strain engineering and material innovation have been critical to improve the performance

of CMOS devices over the past few years. For instance, selective epitaxially SiGe is used in

source/drain regions to introduce uniaxially compressive stress into PMOSFETs, substantially

enhancing the carrier mobility and the drive current, which is very difficult to be achieved by

the conventional Si technology [1-4]. Therefore, introducing a high quality of epitaxial SiGe

layer at source/drain for device performance boosting is very crucial for the advanced

PMOSFETs. By growing a epitaxial strained-SiGe layer in the S/D region with suitable

process condition of Ge content and SiGe thickness a compressive fully strained SiGe stressor

to PFET channel was achievable as shown in Fig.2.1.1. In fact, the strained SiGe layer was

psudomophic state and with Ge content increasing the strained SiGe thickness was reduced

22

critical thickness (fully strained SiGe thickness) was also reduced. Hence, growing a fully

strained SiGe at source/drain region with proper deposition temperature and Ge content as

well as thickness was very important for channel stress enhancement. Fig.2.1.2. showed a

strained SiGe at source/drain region and it provided an uniaxial stress to channel. If one

considered 1.2% of strain formed by S/D SiGe, the corresponding carrier mobility

enhancement was significantly exhibited 60% improvement over un-strained one as shown in

Fig. 2.1.3. Hence, S/D strained SiGe is an important knob for device boosting for 28nm

CMOS and beyond.

Figure 2.1.1 The strained-SiGe Ge fraction and temperature effect on strained thickness (D.C. Houghton, et. al. J. Appl. Phys. 1991)

23

S/D

S

_xx

S

_yy

S

_zz

[110]

S/D

S

_xx

S

_yy

S

_zz

[110]

Ge content(%)

Strain (%)

H

o

le

m

o

b

ility

e

n

h

a

n

c

e

m

e

n

t

60% mobility

Ge content(%)

Strain (%)

H

o

le

m

o

b

ility

e

n

h

a

n

c

e

m

e

n

t

60% mobility

Figure 2.1.2 The S/D strained SiGe structure and its uniaxial stress to Si channel (Thompson, S. et.al. IEDM 2002).

Figure 2.1.3 The strained-SiGe Ge content effect on hole mobility enhancement. (D.C. Houghton, et. al, ICPS 2004)

24

2.2 Motivation

2.21 Why we need S/D SiGe for 28nm device performance

Epitaxial SiGe at source/drain (S/D) region for pFETs drive current enhancement has

been pursued aggressively in scaled CMOS technologies and significant carrier mobility

enhancement at strained Si channel have been reported. Increasing Ge concentration in the

S/D SiGe region is a straightforward method without extra process flow / profile change and

device parameter tuning to boost device performance as PFETs scaling down as shown in

Fig.2.2.1. However, Ge content is inevitable to continuous increment in the S/D SiGe due to

the critical thickness effect that increasing Ge content in the S/D SiGe would cause misfit

dislocation formation in the interface of SiGe and Si substrate. Hence, for high Ge content at

S/D region, strain loss due to misfit dislocation formation at the SiGe/Si substrate made real

carrier mobility lower than that of theoretical fully strain as shown in Fig.2.2.2. In order to

meet target of device performance for the technology generation, suppressing the dislocation

formation of epitaxial SiGe at S/D region caused by post-SiGe implantation and thermal

process is very important for 28nm CMOS volume production.

In this work, we would investigate the implant species effect on S/D strained SiGe

relaxation as well as implantation sequence effect and resultant defect formation once strained

SiGe was relaxed by post process. Meanwhile, how strain loss of S/D SiGe affected device

25

N90

N65

N45 N32/28

N90

N65

N45 N32/28

Ge content(%)

Strain (%)

Hole mobi

lity

enhance

m

ent

Mobility loss btw theory and exp.

Ge content(%)

Strain (%)

Hole mobi

lity

enhance

m

ent

Mobility loss btw theory and exp.

Figure 2.2.2 The mobility loss between theory and experiment for various Ge content.

Figure 2.2.1 The strained-SiGe Ge fraction and channel strain for technology node.

26

2.2.2 Why we need millisecond anneal (MSA) for 28nm pMOSFETs

Source/drain strained-SiGe with low resistivity, formed using a well controlled doping

concentration and by minimizing the short channel effect associated with a shallow doping

profile, is important in CMOS device scaling as shown in Fig.2.2.3. Fig.2.2.4 showed that

spacer resistance, Rspr (Rext + RS/D) dominated the 60% total resistance of PFET. In order to

provide a low resistance of Rspr R, a high Boron activation is necessary to be achieved by very

high temperature anneal to recover implanted Boron as shown in Fig.2.2.5. Recently,

millisecond annealing (MSA, flash annealing or laser annealing) [5-7], which promotes

dopant activation but causes less dopant diffusion at high annealing temperature,

Figure 2.2.3 The Rs performance under scaling junction depth for technology node. (S. D. Kim, et. al. IEDM, 2005)

27 P As B P As B P As B

Figure 2.2.4 The spacer resistance dominates 58% of total resistance of PFET. (S. D. Kim, et. al. IEDM, 2005)

Figure 2.2.5 Solid solubility of Boron reaches saturation at high temperature. (T. Ito, et. al. SSDM, 2001)

28

Figure 2.2.7 The surface heating of laser anneal enables to show millisecond anneal with less diffusion. (B. J. Cho, et. al. Int. Workshop Junction Technology, 2004)

Figure 2.2.6 Anneal temperature and time effect on Boron diffusion length (B. J. Cho, et. al. Int. Workshop Junction Technology, 2004)

29

has emerged as an alternative approach for high-performance CMOS devices as shown in

Fig.2.2.6 and Fig.2.2.7. Therefore, the combination of strained-SiGe in the source/drain

regions as channel stressors and MSA process is a candidate method for improving the

performance of devices based on the 28 nm technology. However, the relaxation of the

strained-SiGe layer due to the large thermal stress that is induced by MSA may make such a

combination challenging. [8-11]

The aim of this work is to elucidate defect formation that results from the combination of

strained-SiGe and subsequent MSA processes and its impact on strain loss of S/D SiGe as

well as device performance. Under certain implantation conditions, the MSA process induced

defects in the underlying Si and degraded device performance. The phenomenon of defect

formation by the MSA treatment is therefore modeled and discussed, and the effective

30

2.3. Experiments

2.3.1. Fabrication process – S/D SiGe first prior to implant

A series of PMOSFETs with SiON gate oxide (Equivalent Oxide Thickness, EOT=12A and Gate length, Lg=28nm) were fabricated using source/drain strained-Si1-xGex (x

nearly~0.35) and in-situ Boron doping with a 100nm-thick layer on 300mm (001) Si wafers. The pocket implant was conducted in SiGe pattern wafers by implantation using Arsenic (As), at energy of approximately 35keV with titled 35 ﾟ and a dose of 3E13cm-2 to suppress the short channel effect (SCE). Spike rapid thermal annealing (RTA) around 1000°C was carried out to recover the damage induced by implantation and to activate the dopants. Laser MSA annealing at around 1200°C for 500s then performing to enhance dopant activation, was as plotted in Fig. 2.3.1.

Implant

(Arsenic)

SiGe

Deposition

RTA

Milli-second

Anneal (MSA)

Implant

(Arsenic)

SiGe

Deposition

RTA

Milli-second

Anneal (MSA)

(Flow-2)

(Flow-1)

Si SiGe Si SiGe Si SiGe Wafer warpage Si SiGe

Implant

(Arsenic)

SiGe

Deposition

RTA

Milli-second

Anneal (MSA)

Implant

(Arsenic)

SiGe

Deposition

Milli-second

Anneal (MSA)

(Flow-2)

(Flow-1)

Si SiGe Si SiGe Si SiGe Si SiGe Wafer warpage Si SiGe Si SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe

Implant

(Arsenic)

SiGe

Deposition

RTA

Milli-second

Anneal (MSA)

Implant

(Arsenic)

SiGe

Deposition

RTA

Milli-second

Anneal (MSA)

(Flow-2)

(Flow-1)

Si SiGe Si SiGe Si SiGe Si SiGe Si SiGe Si SiGe Wafer warpage Si SiGe Si SiGe

Implant

(Arsenic)

SiGe

Deposition

RTA

Milli-second

Anneal (MSA)

Implant

(Arsenic)

SiGe

Deposition

Milli-second

Anneal (MSA)

(Flow-2)

(Flow-1)

Si SiGe Si SiGe Si SiGe Si SiGe Wafer warpage Si SiGe Si SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe SiGe

Figure 2.3.1 The Process flow of the source/drain SiGe followed by implantation, then subsequent MSA was conducted.