5.1 Introduction
The last few years have seen the Si/SiGe material system widely integrated into CMOS technology. The 4.2% lattice mismatch between Si and Ge can be used to obtain the strained layer, where electron (in Si under tension) and hole (in SiGe under compression) transport is improved. Epitaxial SiGe at source/drain (S/D) region for pFETs drive current enhancement has been pursued aggressively in scaled CMOS technologies [1-2]. However, the S/D strained SiGe of the pFETs performance improvement is getting diminished because the volume left for this S/D SiGe stressor is getting smaller and smaller for the advanced technology node [3]. Channel stress was dramatically decreased as the source/drain recess depth and the source/drain SiGe dimension are scaled down as shown in Fig.5.1.1(a).
Inevitably mobility degradation and device performance degradation with gate length scaling has been reported as shown in Fig.5.1.1(b). There have several methods of S/D epitaxial SiGe process to boost device performance as CMOS scaling. Increasing Ge content or enlarge S/D
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SiGe volume or using SiGe channel are the candidates for device performance boosting that have been worldwide discussed. Therefore, finding a good way of epitaxial SiGe process for device performance boosting is necessary for 28nm CMOS and beyond.
5.2 Motivation.
Increasing Ge concentration in the S/D SiGe region is a straightforward method without extra process flow / profile change and device parameter tuning to boost device performance as PFETs scaling down. However, Ge content is inevitable to continuous increment in the S/D SiGe due to the critical thickness effect that increasing Ge content in the S/D SiGe would cause misfit dislocation formation in the interface of SiGe and Si substrate. Unfortunately,
C h annel S tr ess ( % ) C h ann el St ress ( % )
Node (nm) Node (nm)
1414 2222 2828
C h annel S tr ess ( % ) C h ann el St ress ( % )
Node (nm) Node (nm)
1414 2222 2828
S/D SiGe spacing (nm) S/D SiGe spacing (nm)
Figure 5.1.1 (a) Channel stress was dramatically decreased as the S/D recess depth and the S/D SiGe dimension are scaled down. (b) Inevitably mobility degradation and device performance degradation with gate length scaling. (Geert Eneman, et. al. TED, 2006)
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high Ge content loss more strain and results in lower channel stress that would cause opposite result to degrade device performance. In general, Ge content over 50% is very difficult to integrate in the advanced CMOS process flow unless a robust S/D SiGe profile or a well-designed implant and thermal process flow.
On the other hand, widening S/D SiGe volume to shorten the proximity of the S/D SiGe to gate stack is getting attraction to increase channel stress for device performance enhancement [4-5]. Tetsuji has reported that deposition of epitaxial SiGe layer at the lightly doping drain (LDD) region by extra pre-etch process enabled to boost device performance [6].
However, Extension of S/D SiGe to gate stack also faced limitation in scaled CMOS technologies because we can not push S/D SiGe layer into the channel region unless process flow was changed.
Another approach to channel strain engineering is SiGe channel, which was considered as a promising candidate in the nano pMOSFETs for the performance boost-up [7-10]. As we knew that higher carrier mobility about three times in the SiGe material than that of Si. Hence, carrier transport in the SiGe channel is good candidate to boost device performance because channel length did not scale very much and drive current did not loss as that of S/D SiGe while CMOS scaling. However, in order to integrate SiGe channel, one needs to provide a thin Si cap on SiGe channel to prevent Germanium oxide (GeOx) formation during gate oxide growth as shown in Fig.5.2.1. Thicker Si surface passivation capping layer near 5nm could
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Figure 5.2.1 (a) the schematic structure of the SiGe channel with a thin Si cap layer (b) SiGe channel shows high effective mobility than that of Si channel at the same effective field. (F. Andrieu, et. al. EDL, 2006)
Figure 5.2.2 (a) effective mobility of SiGe channel is dependent on the thickness of thin Si cap (b) Dit is also dependent on the thickness of thin Si cap layer. (F.
Andrieu, et. al. EDL, 2006)
(a) (b)
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demonstrate as low interfacial defect (Dit) as Si channel as shown in Fig.5.2.2. But it would attribute to dual channel profile that carriers transport in the Si and SiGe layers degrading carrier mobility. The optimized Si capping layer is about 1~2nm to provide better carrier mobility and low interfacial defects. Such a thin Si cap layer near 1~2nm is very difficult to control for mass production and one also need to consider the post SiGe-channel thermal induced dislocation resulting in gate leakage and device performance degradation. In all, an inevitable epitaxial Si cap layer to provide gate oxide integrity and subsequent thermal budget control to avoid onset of threading dislocations from SiGe channel become the major barriers of technology implementation [11-16].
In this work, we demonstrate a novel embedded SiGe channel (ESC) structure composed of strained SiGe channels without extra Si surface passivation to show potentially superior hole mobility and superior gate oxide integrity. It is believed that ESC structure is a very promising candidate in nano device era with the beautiful essence of low cost and standard pMOSFETs process compatibility.
5.3 Experiments
A series of pFETs with STI and well implantation to control Vt in the embedded SiGe channel (ESC) devices, in which SiGe has smaller energy gap (Eg) than Si substrate
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were fabricated on 300 mm [110]/(001) Si wafers. Following 1.5nm-thick SiON with 10%~15% of nitrogen concentration was formed by rapid thermal process (RTP) and decoupling plasma nitridation (DPN). 30nm gate length of poly-crystal was defined and the poly-crystal line was normal to channel direction [110] shown as in the Fig.5.3.1. Channel direction was switched to boost PMOSFET device performance from 65nm technology. Then 15nm nitride spacer critical dimension (CD) was conducted. A conventional reactive ion etching process (RIE), named as dry etch-1 (Fig.5,3.2), created a recessed region of 60 nm in depth with sidewall Si lattice plane (110) and bottom Si lattice plane (100).
(111)
Figure 5.3.1 The channel direction was changed from [100] to [110] for pMOSFET device performance boosting
Figure 5.3.2 A conventional reactive ion etching process (RIE), named as dry etch-1 and (110) lattice plane of sidewall appeared.
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Subsequently the samples were put into the reduced pressure chemical vapor deposition (RPCVD) chamber at 700°C for the novel technique of the dry etch, named as dry etch-2, which is an in-situ etch process of Cl2 or HCl gas to etch away silicon along (111) plane with 54.5° to create suspending gate stack (Fig.5.3.3)). The activation energy of etching away [110]
is the lowest among [100] and [111] lattice planes as shown in table 5.3.1. One could use the difference of etching activation energy to make [110] plane disappeared and kept [100] and [111] plane. At the same time, the in-situ etching gas in the epitaxial chamber did not damage with silicon nitride (Si3N4) and gate oxide (SiO2) at 700°C and the chemical equations for describing the formation of the embedded SiGe channel (ESC) structure are expressed as below:
2Cl2(g) + Si(s) SiCl4(g) T=700°C, (1) 4HCl(g) + Si(s) SiCl4(g) + 4H(g) T=700°C, (2) 4HCl(g) + SiO2(s) SiCl4(g) + 2H2(g) + O2(g) T>1800°C, (3) 12HCl(g) + Si3N4(s) 3SiCl4(g) +4 NH3(g) T>1800°C. (4)
Plane Ea (eV) Lattice plane
<100> 2.37 Existed
<110> 1.81 Disappeared
<111> 2.32 Existed Plane Ea (eV) Lattice plane
<100> 2.37 Existed
<110> 1.81 Disappeared
<111> 2.32 Existed
Table 5.3.1 The activation energy of etching away [110] is the lowest among [100] and [111] lattice planes
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By well-designed depth of dry etch-1 over 40nm and the lattice crystalline characteristic of dry etch-2 along (111) plane under gate length of 30nm and silicon nitride of 15nm, we can perform calculations involving trigonometric functions to obtain a suspending gate stack of poly-silicon as shown in Eq. (5.3.1.) and Fig.5.3.4. The process was very healthy and channel depth is well-controlled because [111] is the highest packing plane and etching would stop while [111] appears. Because the high modulus of silicon material at gate region, it is not so easy to break down while the substrate is empty. Therefore, we could obtain the depth of SiGe channel we want in the device design.
Z = Y - [(0.5 Lg + X ] tan (54.5°) (5.3.1)
Figure 5.3.3 It illustrates the design of the embedded SiGe channel by defining the various depth of dry etch-1, Y, then obtaining the corresponding SiGe channel depth, Z.
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An undoped SiGe epitaxial layer (Ge~40 at. %) to fill up channel and a doped SiGe
SiGe layer to fill up source/drain was deposited at 700°C without the necessity of a thin Si surface passivation layer in the same RPCVD chamber. The epitaxial SiGe layer was conjointly formed in compressive mode at channel as well as the LDD and S/D region (Fig.5.3.5) and Fig.5.3.6). The transmission electron microscopy (TEM) image of the almost dislocation-free ESC showed the good crystalline embedded SiGe channel between the gate oxide and under-layered Si substrate, as shown in Fig.5.3.7. The good crystallinity of ESC layer on blanket wafer was characterized by X-ray diffraction spectrum (XRD) as shown in Fig.5.3.7.
0 5 10 15 20 25
30 40 50 60 70
Si Recess depth, Y, (nm)
SiGe channel, Z, (nm)
0 5 10 15 20 25
30 40 50 60 70
Si Recess depth, Y, (nm)
SiGe channel, Z, (nm)
Figure 5.3.4 The suspending SiGe channel depth, Z versus S/D Si recess depth, Y.
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(111)
(001)
(111)
(001)
A
undoped doped
SiGe SiGe
gate
Si3N4 oxide
gate oxide
(111)
(001)
(111)
(001)
A
undoped doped
(111)
(001)
(111)
(001)
A
undoped doped
SiGe SiGe
gate
Si3N4 oxide
gate oxide
Figure 5.3.5 It shows the profile of embedded SiGe channel and S/D SiGe
Figure 5.3.6 It shows the profile of embedded SiGe channel and S/D SiGe
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The Arsenic (As) pocket implant was conducted after silicon nitride was removed shown as in Fig. 5.3.9 and another silicon nitride was deposited again for silicidation after the ESC formation shown as in Fig.5.3.10. Subsequent processes were carried out to fabricate the 28 nm pMOSFETs. The TEM image of the ESC showed the good crystalline embedded SiGe
SiGe channel SiGe channel
Optimized dopant IMP
Fully Strained SiGe Simulation
SiGe
Si