Wafer Bending with the MSA - 具有源極汲極應變矽鍺與嵌入式矽鍺通道之28奈米和下世代P型金氧半場效電晶體特性之研究

4.1 Introduction

Strain engineering is one of the unavoidable enhancement for deep-submicrometer CMOS, providing the necessary performance enhancement through the increase of the low-field mobility with strain [1-4]. In the case of pFET transistors, the use of the SiGe at source/drain (S/D) regions is a viable method to create uniaxial compressive strain in the channel, resulting in enhancing the hole mobility. The scalability of this method down to the 28 nm node and beyond has been demonstrated, but will require an increase of the Ge content (x, in percent) of the S/D regions to boost device performance and millisecond anneal to sustain a well junction profile with suppression of short channel effect (SCE). As discussed in the last chapter, defect formation and its resultant junction leakage current are unavoidable to appear while relaxed strained-SiGe and MSA were applied to be integrated in 28nm CMOSFET [5-11]. The phenomenon of defect formation induced by SiGe and MSA could exhibit SiGe area dependency that is a key topic we need to investigate and overcome in

volume production of 28nm CMOSFET. Some literature has reported that the SiGe relaxation by a post-SiGe thermal anneal revealed dependent on Ge content and its area size. By forming a SiGe buckling layer on the viscous BPSG (Boron Phosphorus Silica Glass) as shown in Fig.

4.1.1, the compressively strained SiGe layers on the BPSG can relax during the thermal oxidation. Lateral thermal expansion and counterforces caused by the viscous BPSG produce compressive stresses during thermal oxidation at high temperature. Bending out of the nominal plane by viscous flow of the underlying BPSG layers at a temperature can relieve compressive stresses in thin semiconductor films. Therefore, a phenomenon of strained SiGe buckling was investigated with different Ge content and SiGe area size effect as shown in Fig.

4.1.2 and the corresponding higher defect density at large SiGe area size as shown in Fig.

4.1.3 [12-14]. We would also like to investigate the pattern dependency of the interaction of the strained SiGe and MSA for 28 nm PMOSFETs production.

Figure 4.1.1 (a) A SiGe buckling layer on a viscous BPSG layer to see the relaxation of strained SiGe layer by post-SiGe thermal anneal (b) the buckling SiGe layer revealed undulation. (C.Y. Yu, et. al. J. Appl. Phys. 2006)

(a) (b)

Figure 4.1.3. Optical micrograph images of varying dimension of Si0.8Ge0.2 layers on the viscous oxide after thermal oxidation at 960 °C for 6 minutes.

(C.Y. Yu, et. al. J. Appl. Phys. 2006)

Figure 4.1.2 Critical mesa size vs Ge concentration with a SiGe thickness of 100 nm. Solid symbols indicate the buckled films, and open symbols indicate the unbuckled films. (C.Y. Yu, et. al. J. Appl. Phys. 2006)

4.2. Motivation

One concern related with embedded S/D SiGe processing in PFETs is the junction leakage, which is affected by different processing parameters, such as S/D recess etch, pre-surface clean, Ge content and post implant and thermal anneal, combined with MSA that we will investigate in our work. It has been shown recently that leakage current increase exponentially with the Ge content which could increase SiGe dislocation density in the SiGe junction area as shown in Fig. 4.2.1 [15-17]. An implanted P/N junction region in the SiGe layer caused different degree of dislocation density and junction leakage was raised with increment of dislocation density in the SiGe layer. To suppress post-SiGe process induced defect formation and resultant high junction leakage current is very important while S/D SiGe was applied to advanced CMOSFET.

The aim of the research is to investigate in more detail the impact of MSA on the leakage current of embedded SiGe S/D junctions with SiGe area size dependency. Particular emphasis is to come out a well-designed rule of “(1) ratio of total SiGe area to whole wafer area,

(global area effect) (2) the SiGe area size (local area effect)” with MSA process to avoid

wafer large warpage and defect formation. The resultant design rule of active SiGe area can obtain a as low junction leakage as that of non-MSA process or non-SiGe process to volume production of 28nm CMOSFET and beyond.

4.3 Experiments

A series of PMOSFETs with SiON gate oxide (Equivalent Oxide Thickness, EOT=12A and Gate length, Lg=32nm) were fabricated using source/drain 100nm-thick strained-Si1-xGex

(x nearly~0.35) and in-situ Boron doping with different ratio of total SiGe area to whole wafer area on 300mm (001) Si wafers. The ratio of total SiGe area to whole wafer are designed at 2%, 8%, 12%, 20% and 100% (blanket SiGe wafer) as shown in Fig.4.3.1. Then the pocket implant was conducted in SiGe pattern wafers with different area ratio by implantation using Arsenic (As), at energy of approximately 50keV and a dose of 3E13cm^-2 for the short channel effect (SCE) control. Spike rapid thermal annealing (RTA) around 1000°C was carried out to recover the damage induced by implantation and to activate the dopants. Laser MSA

More dislocation

Figure 4.2.1. (a) The structure of implanted SiGe to form P/N junction. (b) high dislocation of SiGe sample caused high junction leakage current. (Geert Eneman, et.al. APL. 2005)

SiGe

annealing at around 1200°C for 500s then performing to enhance dopant activation, was as plotted in Fig. 4.3.2.



STI and Well implant formationSTI and Well implant formation

EOT 12A Gate oxide formationEOT 12A Gate oxide formation

Poly gate patterningPoly gate patterning



Post SiGe implant Post SiGe implant (As 25Kev 3e13cm (As 25Kev 3e13cm--2)2)



RTA (1000C) anneal RTA (1000C) anneal

MSA anneal (1200C, 500us)MSA anneal (1200C, 500us)

Nitride spacer formationNitride spacer formation

S/D SiGe recess and formationS/D SiGe recess and formation (high/low ratio of SiGe area to (high/low ratio of SiGe area to

whole wafer area)