Chapter 1
Introduction
1.1 Historical Perspective
In December of 1947, the first point contact transistor was constructed by John Bardeen and Walter Brattain of Bell Telephone Laboratories [1]. In 1959, Jack S. Kilby of Texas Instrument Incorporate and Robert N. Noyce of Fairchlid Semiconductor Corporation invented the solid integrated circuit [2, 3]. In 1960, a practical metal-oxide-semiconductor field-effect transistor (MOSFET) was first announced [4].
From this moment, the MOS technology speedily grows along the Moore’s law. To understand the emergence and revolution of modern metal gate technology, the historical perspective of gate electrodes is introduced. In 1960s, gate electrodes of MOS transistors were made from aluminum deposited after the source and drain region were doped. The aluminum had to overlap onto the source/drain to insure that a continuous channel from source to drain was formed when the gate was biased to turn on the transistor. The overlap between gate and source/drain regions causes a significant capacitance to slow the circuit speed. To reduce the overlap capacitance, a self-align gate (SAG) process was proposed by Robert Bower in 1966, where the gate electrode was used as the implant mask. Dopants were implanted to form self-aligned source and drain regions with minimum overlap to gate electrodes [5]. This method drastically reduces the overlap capacitance to speed the device turn-on. However, crystalline defects were induced during implantation. A high temperature annealing, higher than
1000ºC, is the only way to repair these defects. However, it is impossible for aluminum to sustain the high temperature annealing. A refractory material for gate electrodes was emerged from the demand of self-align Source/Drain process and was thought to replace aluminum. In 1967, poly-silicon gate was first used to replace the aluminum gates at Bell Labs [6]. Poly-Si with the capability of high temperature allows the integration of complex process, and its work function is easily modulated by the concentration and types of dopant to match the work function of Si substrate, hence, threshold voltage of transistor is significantly lower. The resistance of poly-Si is also lowered due to be heavily doped. The successful integration of poly-Si gate ruled out the refractory metal gate and disclosed the age of silicon gate technology. Although the structure of poly-Si/oxide/Si replaced the structure of metal (aluminum)/oxide/Si, the acronym of MOS is still continued to be used up to date.
In the 1970s, nMOS transistors in integration circuits (ICs) gradually substituted for bipolar transistors and pMOS transistors, based on the successful planar process and the high quality gate oxide (SiO2) [7]. N+ ploy-Si was used as the gate material due to its higher conductivity than p+ poly-Si gate and easier integration in nMOS. Further, improvement and innovation of lithography technology led to vertical and horizontal device scaling access to large scale integration (LSI) from small Scale integration (SSI).
Circuit performance became more and more improved. To ensure growth of very large scale integration (VLSI) circuits, MOS transistors were continuously scaled to improve the performance. Unfortunately, the resistivity of poly-Si, several hundred µΩ-cm, is almost two orders of magnificent higher than that of typical metals. The high resistance became to limit the signal transmission and circuit performance.
In the 1980s, refractory metals and polycides were proposed to solve the issue of high gate electrode resistance. Refractive metals, such as W and Mo, and their silicides
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were the most potential materials to replace poly-Si due to its low resistivity and the highly thermal stability [8-11]. At that time, CMOS integrated circuits gradually superseded nMOS integrated circuits because of its low power consumption. W and Mo have mid-gap work function (mid of silicon energy band) to offer symmetric threshold voltage of nMOS to pMOS, which is a benefit to simplify circuit design. This single metal gate process once was thought to be a good choice. However, the refractory metal gates cannot be passivated by oxidation at high temperature oxidizing ambient.
Interaction occurred at the interface between metal and SiO2, seriously degraded the reliability of SiO2 as SiO2 thickness is decreased with device scaling. These issues retarded the usage of metal gates. On the other hand, polycide consisting of a layer of doped poly-Si covered by a metal silicide combines the advantages of low resistivity of silicide with the well poly-Si/SiO2 interface [12, 13]. Polycide gate MOSFETs perform the same characteristic of conventional MOSFETs, and do not degrade the reliability of SiO2, and subthreshold leakage. In addition, a self-aligned silicide process (salicide process) without an additional mask effectively simplified the fabrication of polycide gate as well as formation of the silicide on source/drain region for improving contact characteristics [14]. Silicide was confined to the exposed window of gate, source, and drain region to dramatically minimize pattern size. This approach not only solves the issue of high resistance of poly-Si gate but also lowers the contact resistance hence poly-Si gate is lasted [15].
In the 1990s, deep submicron CMOSFETs were the most promising devices for the ultra large scale integration (ULSI) circuits. Surface channel device is superior to buried channel device in the short channel characteristics, such as threshold voltage roll-off and subthreshold leakage [16, 17]. It is not easy for surface channel devices to have a suitable threshold voltage by just only controlling the channel doping. The
threshold voltage should be also adjusted by the work function of gate. Dual poly-Si gate was used for CMOS, where an n+ poly-Si gate has a work function near silicon conduction band for nMOS and a p+ poly-Si gate has a work function near the silicon valance band for pMOS [18].
In 2003, MOSFET gate lengths were scaled down to sub-0.1µm (nano dimension regime) while the thickness of gate dielectric was scaled down to thinner than 3nm.
Various issues were encountered by poly-Si gates when attempting to realize high yield and high performance ULSI circuits. These are high gate resistance, poly-Si gate depletion, boron penetration, and interaction between poly-Si gate and high dielectric constant (high-k) gate dielectrics (the next generation gate dielectrics). Poly-Si gate depletion increases the equivalent gate dielectric thickness by about 0.3nm and degrades the capability of channel current drive [19]. High gate resistance increases the resistance-capacitance (RC) delay time to degrade the high frequency performance.
Although silicide technology can reduce the gate resistance, it is difficult to maintain a proper aspect ratio for gate stake and silicidation of fine line poly-Si is critical [20].
Boron penetration from the p+ poly-Si gate induces the issues of threshold voltage control and gate oxide reliability [21]. High-k materials are expected to replace SiO2 as the physical thickness of SiO2 is below 1.5nm, where the direct tunneling current becomes too high to be acceptable. Interface reaction between poly-Si and high-k induced undesirable threshold voltage due to the Fermi-level pinning (FLP) [22]. Metal gate is considered to solve high resistance, poly-Si depletion, boron penetration, and integration issues of high-k dielectric in gate stake simultaneously and to continue CMOS scaling down below the 45nm technology node. The evolution of MOSFET gate electrodes is schematically shown in Fig. 1-1.
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