Effects of Silicidation and Post Annealing on Electrical Characteristics

Characteristics

Ni impurities in silicon can form a deep level energy state of silicon band gap to induce increased leakage current [18]. Bias temperature stress (BTS) was applied to 600^oC-silicided undoped NiSi/SiO2 (10.5 nm)/Si samples to examine the possibility of Ni diffusion from the NiSi gate into SiO2 and the silicon substrate. As shown in Fig. 7-8, the high frequency C-V curves are almost identical after BTS under the typical condition of ±2 MV/cm at 200 °C for 30 min [19]. There are no distortion in the C-V curves and no increase in the capacitance at inversion mode, which is very sensitive to the defects caused by the substitutional impurities in Si substrate. Thus it is presumed that under the BTS condition employed, the SiO2 grown in dry oxygen ambient is a good diffusion barrier to Ni atoms [20-23].

The SiO2/Si interface quality of the NiSi gate was analyzed from the interface state densities. As shown in Fig. 7-9(a), the interface state density is 4×10¹¹ cm^-2 eV^-1 for the 600^oC silicided sample and is 8×10¹⁰ cm^-2 eV^-1 for the 500 °C silicided samples. Figure 7-9(b) shows the relative quasi-static C-V curves. No Vfb-shift occurs, but curve distortion is observed near Vg=-0.5 V. Particularly for the prolonged 500 °C annealed sample, the quasi-static C-V curve is almost identical to the original 500 °C silicidation curve. If Ni diffuses into SiO2, the oxide charge will increase and C-V curve will separate from the low temperature annealed samples. Since C-V curve distortion occurs near inversion, stress-induced interface state is the main reason for damage. Moreover, the distortion tends toward the positive voltage which reflects that the interface states are negative charged. The mechanical stress is confirmed by the measurement of the thin film stress, which indicates that the 600 °C sample has a 0.96 GPa tensile stress while the 500 °C sample has a 0.75 GPa tensile stress.

161

To further investigate the effects of thermal budge, prolonged thermal annealing at 600^oC was performed on the undoped NiSi samples. The Vfb and hystereses are degraded with annealing time, while they are almost unchanged within 15 min annealing, as shown in Fig. 7-10. The negative shift of Vfb is caused by positive charges, which is different from the negative charged surface states caused by thermal mechanical stress.

In addition, the device can sustain thermal stress for 15min. Therefore, it is presumed that degradation is induced not only by the stress but also by Ni diffusion. From the thermal degradation point of view, the temperature of Ni-silicidation process should be at or below 500°C and the prolonged thermal process should be below 500 °C.

7.4 Summaries and Conclusions

We demonstrate a new and useful implant-to-silicide (ITS) method to modulate the effective work function of a NiSi gate after silicidation. Impurities, such as phosphorus and boron, pile up at the silicide/oxide interface after a 600 ^oC annealing. Large work function modulation can be achieved in the FUSI NiSi (50 nm)/SiO2 gate stack by BF2+ and P⁺ species with a implantation dosage of 1×10¹⁵ cm^-2. The work function ranges from 4.36 to 5.14 eV.

Therefore, NiSi FUSI gates are a feasible single metal gate with dual work function candidate for CMOS devices with SiO2 gate dielectrics. However, the work function of the ITS NiSi on HfO2 sample only ranges from 4.44 to 4.62 eV. The small work function range implies that the Fermi-level pinning effect occurred on the FUSI NiSi/HfO2 structure. For the CMOS devices with a HfO2 gate dielectric, a continuous SiO2-like interfacial layer between NiSi and HfO2 can reduce the Fermi-level pinning problem, whereas the increase of effective oxide thickness should be optimized to avoid the scaling limit.

Regarding the thermal stability, although the NiSi on both SiO2 and HfO2 are stable up to

600 °C, thermal stress can degrade the device performance during the silicidation and post-silicide annealing. A silicidation temperature and post silicidation annealing temperature at 500 ^oC only causes a slight increase of interface state of less than 1×10¹¹ cm^-2eV^-1, while the siliciadtion at 600 ^oC will cause interface states higher than 3×10¹¹ cm^-2eV^-1. The thin film stress increases from 0.75 GPa to 0.96GPa as the silicidation temperature increases from 500 ^oC to 600 ^oC. The preferred temperature for Ni-silicidation is suggested at or below 500 °C and the prolonged thermal process should be below 500 °C.

163

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Table 7-1 Some conditions of the FUSI test samples

SiO2 sample HfO2 sample

Dielectric structure Single layer of SiO2 Stack of HfO2/SiO2

Dielectric Thickness (nm)

5.5 10.5

17

2/5.5 2/10.5

2/17

NiSi doping method ITS ITS

Pre-doped Implantation conditions BF2+/1×10¹⁵/10 KeV

P⁺/1×10¹⁵/10 KeV

BF2+/1×10¹⁵/10 KeV P⁺/1×10¹⁵/10 KeV ITS: implant-to-silicide

20 25 30 35 40 45 50 55 60 65 A:300^oC/1hr

B=A+RTA/600^oC/30s C=B+FA/600^oC/4hr

C B A NiSi NiSi

Si Si NiSi

Intensity

Ni₂Si

2θ (deg)

Fig. 7-1 X-ray diffraction patterns of nickel silicide. Curve A is recorded after 300 °C silicidation in a furnace (FA) for 1 hr; curve B is recorded after condition A plus 600

°C RTA for 30 sec; curve C is recorded after condition B plus 600 °C annealing for 4 hr in a furnace.

169

0 50 100 150 200 250

5 6 7 8

Sheet resistance (Ω/sq)

Annealing time (min)

Fig. 7-2 Sheet resistance of NiSi film vs annealing time at 600 °C. The measured NiSi film is on the SiO2 layer.

Fig. 7-3 TEM cross-sectional views of (a) ITS sample and (b) pre-doped sample.

5nm 5nm

(b) (a)

171

544 540 536 532 528

In te n sity

Fig. 7-4 (a) Scheme of detection by X-ray photoelectron spectrometer. Area A is exposed after removing NiSi, and B is exposed after removing the interfacial layer. The electron binding energies of detected areas A and B of (b) Si 2p orbital, (c) O 1s orbital, and (d) Hf 4f orbital are shown.

5nm 5nm

Fig. 7-5 TEM cross-sectional views of (a) as-deposited amorphous Si/ HfO2/SiO2/Si, and (b) sample (P+ poly-Si sample) implanted with BF2 and annealed at 900^oC for 30 sec in N2 atmosphere.

5nm 5nm

(a) (b)

173

4.0 4.2 4.4 4.6 4.8 5.0 5.2

SiO2 HfO2

Work function (eV)

SiO

₂

HfO

₂

E

_c

E

_V

ITS_P

ITS_BF

₂

Pure NiSi

Pre-doped BF

₂

P

⁺

poly Si

Fig. 7-6 Effective work function (Φm,eff) of doped and undoped NiSi FUSI gate on SiO2 and HfO2. Φm,eff of the P⁺ polysilicon gate on HfO2 is also included.

0.0 0.1 0.2

Fig. 7-7 Depth profiles of (a) boron and (b) phosphorous dopants in NiSi FUSI gates detected by secondary ion mass spectrometry.

(a) (b)

175

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0

0.5 1.0

NiSi/SiO₂(10.5nm)/Si Capacitance (C/C o)

V_g (V)

BTS @ 200^oC fresh -2MV/cm +2MV/cm

Fig. 7-8 C-V characteristics of NiSi FUSI gate capacitor with SiO2 gate dielectric after bias-temperature stress of ±2 MV/cm at 200 °C for 30 min.

4.0x10¹¹ 8.0x10¹¹ 1.2x10¹²

Fig. 7-9 (a) Cumulative distribution of interface state density of NiSi FUSI gate capacitors; NiSi gates were formed at 500 or 600 °C. (b) The relative quasi-C-V curves of NiSi FUSI gate capacitance and the high frequency curve of sample C.

(a)

(b)

177

Fig. 7-10 Cumulative distribution of (a) flat-band voltage (Vfb) and (b) hysteresis of NiSi FUSI gate capacitors after prolonged 600 °C annealing.

(a) (b)

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