The demand of high performance integrated circuits (ICs) drives the CMOS device to scale down. As the device scales down, it is important to maintain or improve the switch speed, power consumption, and reliability so that new materials are included. The incorporation of new material in ICs is crucial since it requires consideration of numerous issues: contamination, process integration, thermal stability, performance, and reliability. In order to highlight the issue arising while metal materials are integrated into the advance CMOS, it is helpful to consider the basic design of this device. Figure 1-2 is a schematic cross-section of a sub-45nm metal gate CMOS structure which indicates the area where novel materials and process-integration solutions are necessary. For the aspect of metal gates, candidate metals must have high melting point and high thermal stability on gate dielectrics.
These metals must have high conductivity and must have thermal expansion coefficients close to Si to prevent thermal stress during high temperature processes.
The work function of metal gates must be suitable to obtain low and symmetric threshold voltages on the n- and pMOSFETs. The desired properties of metal gate for CMOS are listed in table 1-1.
1.2.1 Metal Gate Materials
Metal gate materials are generally classified into four categories including elementary metals, metal nitrides, metal silicides, and metallic alloys. In addition, there are some conducting metal oxides, metal carbines and ternary alloys such as In2O3, RuO2, IrO2, ZnO2, ITO, ReO2, TaC, TaTiN, TaAlN, and TaSiN.
i. Elementary metals:
The commonly used metals in IC industry are located in the group B of
periodic table, as shown in Fig. 1-3. The work functions periodically ranges from conduction band (Ec) to valence band (Ev) or Si energy band relative to locations of elements [23, 24]. Elements including Ti, Zr, La, V, Nb and Ta in column IVB and VB have the n-type work function; elements including Mo and W in column VI B have mid-gap work function and elements including Re, Ru, Co, Rh, Ir, Ni, Pd and Pt in VIIB and VIIIB have p-type work function. N-type elements are chemically reactive and are not suitable for the conventional CMOS process due to the interaction with the gate dielectric.
P-type elements are relatively inert and can sustain the high temperature process. However, the chemical inertia reflects difficulty in patterning and poorness in adhesion.
ii. Metallic alloys:
The common metallic alloys are binary alloys consists of an n-type metal and a p-type metal, such as Ta-Pt alloys, Ru-Ta alloys, and Hf-Mo alloys [25-27]. The actual work function is determined by the atomic composition.
Alloys with higher n-type metal content have a lower work function. On contrary, alloys with higher p-type metal content have a higher work function.
iii. Metal nitrides:
Metals react with nitrogen to form metal nitrides which are more chemically stable on dielectrics than pure metals. The commonly considered metal nitrides are tantalum nitride, titanium nitride, tungsten nitride, molybdenum nitride, and hafnium nitride [28-32]. The work function can be adjusted by the nitrogen composition and the nitride phase, but the tunable range is not wide enough to be used for both nMOSFETs and pMOSFETs. In
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addition, an obvious drawback is the high resistivity.
iv. Metal silicides:
Metals react with silicon to form metal silicides. The commonly considered metal silicides are molybdenum silicide, tungaten silicide, nickel silicide, cobalt silicide, titanium silicide, platinum silicide and hafnium silicide. Silicide gate is compatible with conventional CMOS process and its effective work function is adjusted to suit both nMOSFETs and pMOSFETs by the IIIA and VA impurity [33-36]. Therefore, silicides are thought to be the mostly possible materials.
1.2.2 Resistivity
As the devices scale down, the line width, gate length, and contact hole get narrow and small. The resistance contribution to the RC delay increases not only at the metallic interconnects and contacts but also at the gate lines The sheet resistance of gate line should be less than 5-7 Ω/ to prevent offsetting the advantage of device scaling by the interconnect in the gate level. In other words, the resistivity of gate material should be less than 12.5-25 µΩ-cm in 2007. Table II lists the gate electrode thickness and sheet resistance predicted in the International Technology Roadmap for Semiconductor (ITRS) [37].
1.2.3 Work Function
To evaluate the suitable work functions of gate electrodes, the threshold voltage of metal gate MOSFETs are considered. The threshold voltages (Vt) are determined by [38]:
2 4
, where Φms is the work function difference between gate and Si channel, Cox is the capacitance of gate dielectic, Qf is the effective oxide charge, ΨB is the potential energy difference between intrinsic Fermi level and Fermi level of silicon channel, q is the elementary charge, and εSi is silicon permittivity, NA is the substrate dopant concentration. As the gate dielectric thinning, the Cox becomes large enough to neglect the effect of charges in dielectric and channel so that the threshold voltage is determined by theΦms and ΨB relative to the work functions of gate and silicon channel. Figure 1-4 shows the simulated threshold voltage of bulk and SOI MOSFETs [39, 40]. In order to obtain Vt between 0.2-0.4 V (~Vdd/4), the ideal work function is 4.1eV-4.3 eV for bulk nMOSFETs and is 4.9-5.1 eV for pMOSFETs, where the channel concentration is about 1x1018 cm-3 in order to suppress the short channel effect [39]. The ultra-thin body or double-gate SOI MOSFETs with undoped channel require the work function of 4.3-4.5eV for n-type devices and 4.7-4.9eV for p-type devices [40].
1.2.4 Metal-Gate Structures
It is not easy that single metal layer can satisfied all of the above criteria. The most promising gate structure is stack of two metal layers, as shown in Fig. 1-5.
The bottom layer serves as a threshold control layer. It is a thin barrier layer which needs to have proper work function, good adhesion, and chemical stability on gate dielectric. The top layer serves as a conduction layer. It is a thick layer which needs to have low resistivity, low stress, to protect the bottom layer from ion implantation and to passivate the bottom layer against oxidation and chemical solution attack during oxide passivation and clean process, respectively. The
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proper top layer is suggested to be polycide due to its low thermal stress and compatibility with conventional process.