This dissertation focuses on the characterization of alternative metal gates for the sub-45 nm technology node. In this chapter, the history of gate electrode evolution and the key criteria of metal-gate materials have been reviewed. Chapter 2 provides the experimental techniques of metal-film deposition, physical characterization, and electrical characterization. Following is the main materials to evaluate various types of metal gates. Chapter 3, 4, and 5 deeply study the tantalum nitride gate, molybdenum nitride gate, and tungsten nitride gate on SiO2 and HfO2, respectively.
Chapter 6 presents the study of Ta-Pt alloy gates. It is focused on the work function modulation and the effects of II and V column impurities incorporation, as well as the thermal stability. Chapter 7 studies the FUSI gate process integration in CMOS. A
summary and suggestion for future work are present in chapter 8.
15
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Table 1-1 Desired properties of the metal gates for CMOS.
Suitable work function Low resistivity
Stable on gate dielectric, high melting point Easy pattern
Mechanical stability: good adhesion, low stress
Stability throughout processing, including S/D activation, post annealing, silicide contact formation, passivation, metallization,
Surface smooth
Should not contaminate devices, wafers, and working apparatus Should not diffuse into gate oxide
23
Table 1-2 The sheet resistance and thickness of gate electrodes predicted in ITRS roadmap.
Year of performance 2005 2006 2007 2010 2013 2016
Technology node (nm) 80 70 65 45 32 22
Gate electrode thickness (nm) 32-64 30-60 25-50 18-36 13-26 9-18
Gate electrode sheet Rs (Ω/ ) 5 5 5 5 6 7
Table 1-3 Charge neutral level and S parameter for several dielecitrics.
Theory Experiment
EG ε∞ S ECNL-Ev S ECNL-Ev
SiO2 9 2.25 0.86 4.5 0.95 5.04
Si3N4 5.3 3.8 0.56 2.6 0.59 2.79
HfO2 6 4 0.53 3.7 0.52 3.64
ZrO2 5.8 4.8 0.41 3.6 0.52 3.82
25
Application for MOSFET Gate Electrode Technology
Application for MOSFET Gate Electrode Technology
Fig. 1-1 The evolution of MOSFET gate electrodes with the innovation of technologies.
Si-substrate
N-well P-well
High-k dielectric:
High k value, Low leakage Silicide contacts:
Low contact resistance
Channel:
High mobility, Strain Si channel Metal Gate:
Dual work function, Low resistivity
Fig. 1-2 A schematic cross-section of a sub-45 nm metal gate CMOS structure, where the novel materials and process-integration solution are indicated.
27
Fig. 1-3 The common metal elements in periodic table. The elements were marked as p, n, and m according to its work function near the valence band, conduction band, and mid-gap of silicon energy band, respectively.
-1.2
1E+15 1E+16 1E+17 1E+18 1E+19
Concentration (1/cm3)
Fig. 1-4 The threshold voltages of (a) bulk devices and (b) SOI devices versus channel concentrations. The estimation of threshold voltage was evaluated with the simulation of long channel and uniform charnel dopant devices by Avant!
MEDICI. The dependence of oxide thickness or thickness of silicon body was also taken an account.
(a)
(b)
29
Fig. 1-5 A structure of the stack metal-gate electrode. The bottom layer serves as threshold control and dielectric-contact layer; the top layer severs as conduction layer connected with metallic interconnect.
Orientation
Phase
Composition
Impurity
Gate oxide
Structure modification
interface treatment
Fig. 1-6 Schematic methods of work function modulation divided into two categories:
structure modification and interface treatment.
31
Fig. 1-7 The critical Fermi level of metal gate on dielectric. The effective work function of metal on dielectric is the same as in vacuum while the interface is perfect.
The effective work function is fixed to the delectric-charge-neutral level while the interface-state density is high. The interface states are caused by both intrinsic states (MIGS, ViGS) and extrinsic states (defect levels).
Fig. 1-8 Schematic process flows of metal gate MOSFETs including (a) gate-first process; (b) gate-last process, and (c) fully-silicided process.
33