Table 3.1 Comparisons among different types of proposed DCV cells………. 32 Table 3.2 Comparisons with existing DCOs……….. 38 Table 3.3 Resolution of Tbuffer and Tfine……….. 39 Table 3.4 DCO output frequency range for different processes under typical
condition.
39
Table 4.1 Fixed sampling period V.S. locked cycle period……… 55 Table 4.2 Simulations with different input frequencies and multiplication factors 56 Table 5.1 Summary of chip features of cascaded DFC loops………. 76 Table 5.2 Performance comparison of all-digital clock generator……….. 77
Chapter 1
Introduction
1.1 Thesis Background
Traditionally, phase locked loops (PLL) based clock generators for microprocessor are the common way of frequency multiplication from a low-frequency reference clock, typically from quartz oscillator [1-13]. As VLSI technology grows up rapidly, the advance of semiconductor process enables the successful realization of system-on-a-chip (SoC) [14-17,21,23-24]. Modern SoC processors integrate both analog and digital real-time functions, such as a digital signal processor (DSP), digital-to-analog converter (DAC), audio, video, and I/O interface protocols. An off-chip clock costs power to generate and to distribute on the PC-board. In addition, the ability to oscillate at different frequencies reduces costs by eliminating the need for additional oscillators to a system. Such applications often require on-chip clock generation and multiplication to produce several unrelated frequencies for digital signal processing, I/O interfaces, as well as sampled analog sub-systems [18-19].
One solution is to create one PLL-based clock generator running at a high frequency that can then be divided down to obtain all the desired frequencies [20]. The disadvantage of this approach is the high power consumption and stringent jitter requirements. Another approach is to have a dedicated PLL for each clock domain [21]. This solution is very costly in term of power and area.
The diversity of SoC applications has led to diversity in operating frequencies and
multiplication factors required from PLLs. The loop parameters must be adjusted to minimize jitter performance and to insure stability for each PLL output frequency and multiplication factors. Providing ample flexibility for a variety of applications is a big challenge for PLL design. The design of PLL-based clock generator is a trade-off among jitter performance, frequency/phase resolution, lock-in time, power consumption, area-cost, circuit complexity and design time. It often needs to redesign the PLL for target applications. If a wide-range PLL is designed for SoC applications, it can be used in more modules without modify it.
However, this scheme may waste unnecessary area cost and power consumption due to the requirement of wide-range operation. Thus, it is a challenge task to design it based on conventional analog skill.
In addition, most PLL design use mixed signal and full custom design techniques, which can not be fully integrated in digital environment. Due to time-to-market issue, the design cycle remains the same or even shorter. Thus in System-on-a-Chip (SoC) designs [22], each module had better to be reusable and process portable, so that the total design time can be reduced. As a result, how to design a synthesizer clock generator in an efficient way becomes more important.
1.2 Thesis Motivation
The all-digital PLLs have several advantages over their analog counterparts. Firstly, traditional analog loop filter costs a lot of chip areas. Using digital loop filters gives benefits such as robustness against noise, and also the ability to design higher order filters without much extra power consumption and area penalty. Secondly, analog component are vulnerable to DC offset and drift phenomena that are not present in equivalent digital implementations [35]. Furthermore, the loop dynamics of analog PLLs are quite sensitive to process technology scaling, whereas the behavior of digital logic remains unchanged with scaling; this
requires much more significant redesign effort to migrate analog PLLs to a new technology node than is required for all-digital PLLs.
Moreover, power consumption is extreme concern for portable, battery-powered, computing system, as power dissipation relates directly to battery life. As a result, many manufactures are reducing the power supply voltage requirements of the integrated circuits, particularly those that are especially adapted for portable computing system [36]. However, reduction in power supply voltage applied to analog circuitry, such as analog and digital PLLs, does not reduce the power dissipated by these circuits. Additionally, reduction in power supply voltage to analog circuits renders the design of robust circuit much more difficult.
For these reason, PLLs in which digital techniques are used in not only the phase detector, but also in the loop filter and the controllable oscillator, are very attractive to designers. All-digital cell-based approach is preferred for SoC applications [44-50]. It can reduce significantly both design time and design complexity by using Verilog (or VHDL) hardware-description language and the final circuit layout to be generated by using an auto placement and routing (APR) tools.
A production SoC with high-performance audio/video media networking processor as shown in Fig 1.1 has successfully applied four standard cell-based digitally controlled oscillators (DCO) [57] to replace two external analog audio PLLs and two external quartz oscillators [23-24]. By saving two external analog PLLs, 4 I/O pins (2 per PLL) are saved.
Another two I/O pins for connecting quartz oscillators are also reduced. However, due to the limitations of standard cell-based design, it is difficult to achieve a low jitter, low-power, and high resolution all-digital cell-based clock generator [45-50,57]. Thus, how to overcome the limitations of standard cells to build up a high resolution DCO with better linearity and less power consumption, and propose new control algorithm for clock generator are the important design challenges for our research.
Fig. 1.1 SoC Media Networking Processor [24].
1.3 Thesis Contribution
In this dissertation, we address the issue of portable digitally controlled oscillator (DCO) and propose dynamic sampling period algorithm to enhance frequency detection. In addition, a cascade dynamic frequency counting loops for wide multiplication application is developed.
The contributions are listed as follows:
n Portable Digitally Controlled Oscillator with Novel Varactors
In this thesis, we first present a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design.
This novel varactor uses the parasitic capacitances difference of NOR gates under different digital control inputs to establish a digitally controlled varactor. Thus proposed DCO can improve delay resolution 256 times better than a single buffer design. This study also examines different types of NOR/NAND gates (2-input or 3-input) for DCV. The final circuit layout can be generated using an auto placement and routing (APR) tools. A test chip demonstrates that LSB resolution of the DCO can be improved to averaged 1.55 ps with standard 0.35-mm 2P4M CMOS digital cell library. The proposed DCO has good performance in terms of fine resolution, testability, and short design turn-around cycle compared with conventional DCO designs.
n A New Algorithm with Dynamic Frequency Counting Loop
Second, a new algorithm with dynamic frequency counting (DFC) that multiplying input reference frequency by N times is presented. The DFC loop which uses variable time period to estimate and tune the frequency of digitally controlled oscillator (DCO) enhances the resolution of frequency detection. One up counter serves as variable timer and another DCO timing counter acts as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a simple circuit structure. The proposed algorithm was simulated and compared with other method. Then, the performances were measured from 0.35-mm and 0.18-um chips.
n Cascaded DFC Loops for Wide Range Multiplication Applications
Finally, a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications is presented. The loop stability can be retained by cascading two DFC loops when multiplication factor (N) is large. The design complexity is tremendously reduced without using the analog component. The proposed clock generator is fabricated in 0.18-mm CMOS process with core area of 0.16mm2. Experimental results of the
clock generator are given in this chapter.
1.4 Thesis Organization
The organization of this thesis is as follows: In chapter 1, we introduce that different clock domains are required in a SoC chip. Using portable clock generator to replace conventional PLL is feasible. For the rest of this dissertation is organized as follows.
In chapter 2, we give an overview of PLL related techniques for clock generator.
Properties of analog, digital PLL as well as charge-pump PLL are addressed. Then, all-digital PLL with different DCO approaches are discussed. The design trade-off of clock generator with different PLL architecture is also investigated.
In chapter 3, we first introduce the fundamentals of digitally controlled oscillator. We also introduce different approaches to enhance the fine tune solution of DCO. Then, we focus on the operation of digitally controlled varactors with two-input or three-input NOR/NAND gates designs. Then, we apply the DCV as fine tune cell to build high resolution digitally controlled oscillator. A detailed description of the circuits and experimental results are given.
In chapter 4, we describe a dynamic sampling technique to enhance the resolution of frequency detection by using simple structure. Detailed algorithm and structure of the loop are then discussed. Then, the proposed algorithm was verified in 0.35-um and 0.18-um.
In chapter 5, we utilize the dynamic sampling techniques for wide range multiplication applications by cascade loops. The multiplication factors range from 4 to 13888 (224 x 62).
The peak-to-peak jitter is less than 2.8% of output clock period. Then, we talk how to design the DCO in each loop as well as the loop parameters. Finally, we discuss the experiment results and the overflow issue.
In chapter 6, some concluding remarks will be derived from this research. Finally, we describe several design issues that needed to be further explored in the near future.