Overview of Clock Generators with Phase Locked Loop (PLL)
2.2 All-Digital PLL
The all-digital phase lock loop (ADPLL) has gained increased attention in recent years.
All analog building blocks are replaced with digital representations in all-digital PLLs (ADPLL). The term “all-digital PLL” is used for a particular reasons: all signals within this PLL are digital values; no analog level is used. Many different ADPLL are discussed in the literature [69]. In general, there are two types of ADPLL depending on the DCO clock source:
(1) to use fixed high-speed clock as indicated in [2,15,43,57] to form a DCO, (2) to synthesis clock internal based on a DCO circuit as [37-39, 42]. Furthermore, the standard cell-based implementation of DCO will also be discussed because of its popularity [50].
2.2.1 DCO with Fixed High-Speed Clock
Fig. 2.6 shows the proposed ADPLL with fixed high-speed clock and output accumulator in [3].
Register Output
Accumulator fclock
Noffset
X2 fin
N2 N2
Nout
-q
Fig. 2.6. ADPLL with fixed high-speed clock to form DCO in [3].
The input is a binary fin, and the output is to be a number that has an average repetition rate of fin but follows the input with a closeness that depends on the loop parameters. The DCO consists of an accumulator and high speed clock fclock. Its output is a number that changes each clock cycle by an amount equal to its input N2. Each time the output accumulator reaches its capacity Nmax, it recycles to 0. Thus, one cycle is represented by Nmax, and the output phase of the output accumulator is
Φout = (Nout /Nmax) cycles (2.10) The output frequency is
fout = ΔΦout / Δt = (N2 / Nmax)．fclock (2.11) since the output is incremented by N2 each cycle of the output accumulator. The register stores the value of Nout at each cycle of the input signal fin. The register thus functions as a phase detector and zero-order hold. Then, the phase error will be inversed and multiply with 2-q. There are two sampling processes occurring in the simple loop, one in the register at fin
and one in the output accumulator at fclock. The stability of this simple loop can be represented by using z-transform. The closed loop of Fig. 2.6 is
H(z) =
K z
K +
-1 , (2.12)
where
K = 2-q (fclock / fin). (2.13) The open and closed loop poles for this loop are shown Fig. The closed loop pole locus begins at the open loop pole when K=0 and moves along the real axis as K increases. The beset response will be in the center of the unit circle where K=1. The closed loop is unstable when K is larger than 2.
Fig. 2.7. Z-plane representation of the loop [3].
2.2.2 Direct DCO Synthesis Clock
If the high-speed clock is available, such as in SoC, and the target operation’s speed is not very high, then DCO with fixed high-speed clock can be the choice. However, it may consume large power due to high-speed clock operation. The external high-speed clock is not always feasible which require extra pin and another high-speed quartz oscillator when the target application is for on-chip clock multiplication (factor > 1). In recent years, ADPLL of type (2) is more popular and even applied frequency synthesis for RF wireless application [40-41,54]. An ADPLL with high resolution DCO as shown in Fig. 2.8 was first proposed in [37] as clock generator for microprocessor that did not require external fixed high-speed clock as compared with Fig. 2.6.
Figure 2.8. ADPLL with direct DCO synthesis clock [37].
This ADPLL achieved fast locking within 50 reference clock cycles as compared with conventional charge pump PLL-based clock generator. The fast locking time was achieved with modified binary searching algorithm. It separated the frequency acquisition and phase acquisition that did not utilize the three-state PFD and frequency divider. A high-resolution frequency comparator with matching delay line was utilized to achieve frequency accuracy under 0.1% error ratio. A high-resolution ring oscillator with 16-bit control word was implemented to generate the accurate frequency output. The DCO will be turn-on and disable after 30-40 iterations for frequency comparison. An anchor register is needed to store the baseline frequency. After frequency acquisition is completed, the PLL starts to trace the phase of the reference clock. The phase tracking process was performed with a phase control algorithm and a phase detector. It contains phase gain controller and two series-connected, edge-triggered D flip-flops. The phase acquisition process can be finished within 10 reference clock cycles. After the frequency acquisition and phase acquisition, the ADPLL enters phase and frequency tracking process. Many ADPLL variants follow this ADPLL approach, such as [38-39]. However, the cost of this chip area is extremely high due to DCO. Another small area DCO was proposed in [38]. Those DCO designs were required to be with full-custom layout. The specific transistor sizing of DCO comes to be with changes in design specifications.
2.2.3 Standard Cell-Based DCO
A standard cell-based implementation of all-digital clock generator [50] based on structure of digital PLL that can be divided into five main parts: PFD, loop controller, loop filter, DCO, and programmable divider as shown in Fig 2.9. The key issue is that all of the elements are designed form standard cell library without any fully-custom layout.
Fig. 2.9. Functional block of ADPLL in [50].
The function of the programmable divider is simply to slow the DCO output frequency for comparison. The loop controller generates the digital commands to track the DCO output clock based on the results from PFD. Two extra digital pulse amplifier circuits are required to minimize the dead zone of PFD, as indicated in [50]. However, the control code may have small variations due to the following factors: PFD’s dead zone, DCO’s finite resolution. An average loop filter is necessary to filter out the rippling and produce a smoother digital controlled word with less jumping. Additionally, two DCOs are required for low output jitter to reduce the noise and jitter associated with input reference. This requirement leads to a highly complex and expensive design. Therefore, this structure was effectively creating a frequency locked loop. The cell-based ADPLL of Fig. 2.9 can be modeled as shown in Fig. 2.10.
PFD
Fig. 2.10. Signal block diagram of standard cell-based all-digital PLL.
The closed-loop transfer function of Fig. 2.10 is
The stability of the closed loop transfer function depending on KD, KO, N and F(z). Different types of loop filter are discussed in [49].