Dynamic Frequency Counting Loop for All-Digital Clock Generator
4.2 Algorithm and Architecture of Dynamic Frequency Counting Loop
One common problem exists as described in chapter 2 when the loop’s order of PLL or ADPLL is greater than one owing to a phase difference detected in the phase frequency detector. The main reason to this problem is the integral of frequency, which implies that there is a 90 degree shifted response from the DCO control word (DCW). It implies mathematically a pole in the loop response created by the action of measuring phase in the PFD. Thus, it needs a zero to remove the inherent pole to make the loop to be at least second order control system [49,53,55]. This makes the designs to be very complex.
4.2.1 Algorithm of Dynamic Frequency Counting Loop
The dynamic frequency counting loop is a first order system that uses variable time
period to estimate and tune frequency of DCO. Fig. 4.1 shows the loop control algorithm of the proposed DFC loop. The reference timing counter (REF_timing_counter) operates at reference clock rate. The counter initially from zero counts up at every rising-edge of reference clock. Similarly, the DCO timing counter (DCO_timing_counter) operates at the speed of the DCO output clock. The quotient and remainder vectors in the DCO timing counter are compared with the input multiplication factor (N) when the reference timing counter is power-of-2 reference clock cycles.
i=i+1
Fig. 4.2. The loop control algorithm for proposed DFC loop.
The sampling cycle time of the DFC loop control is defined as
Ci = 2i · TREF (4.1) where i represents the i-th DFC sampling state and TREF is the cycle time of the input reference clock (CKref). The sampling cycle time Ci is the timestamp performing the frequency comparison of DCO clock output and M is the maximum number of DFC sampling state, which is shown in Fig. 4.3. If the result of frequency comparison remains unchanged and the maximum number of DFC sampling state is less than M+1, both counters will continue frequency accumulation. Otherwise, the frequency error signal will be asserted to update current DCO control word (DCW) to adjust the DCO output frequency. Meanwhile, both the reference timing counter and DCO timing counter are reset to zero. Therefore, the reset and accumulation of both counters move according to frequency sampling period and frequency comparison result.
Fig. 4.3. Timestamp of frequency comparison.
Fig. 4.4. shows the basic structure of dynamic frequency counting loop. It consists of four main functional units: a reference timing counter, DCO timing counter, DCO and DFC loop controller. The reference timing counter serves as a variable timer for decision unit to estimate and control the DCO. The DCO timing counter performs as a frequency estimator of DCO output frequency. The DFC loop controller performs loop control, frequency error accumulation and gain control based on measured frequency values in DCO timing counter.
The DFC loop is a discrete-time sampled system implemented with all digital components.
Consequently, the z-domain representation is the succinct method instead of using damping factor as indicated in chapter 2 for analog PLL.
Fig. 4.4. Basic structure of dynamic frequency counting loop.
Fig. 4.5 illustrates the signal model of the proposed clock generator with the DFC loop control. The transfer function of Fig. 4.5 is given by
H[z(t)]= 1
Fig. 4.5. Signal model of the proposed dynamic frequency counting loop.
x x
Z-domain Unit circle
K(i)=1 K(i)=0
Fig. 4.6. Pole displacement by gain variation.
From (4.3), it should be noted that K(i) should be placed in the range 0 ~ 2 for loop stability.
Fig. 4.6 illustrates the pole displacement with gain variation, and the maximum value of M is bounded by the loop gain K(i). The DFC loop control is a first-order time varying system. It only accumulates the frequency error thus generally features faster dynamics and greater stability than higher order loop. The digital arithmetic comparator replaces conventional PFD conversion mechanisms. The variable frequency FDCO[j] is determined by counting the number of rising-edge clock transitions of the digitally controlled oscillator. The sampled FDCO[i] is compared with multiplication factor (N) in a digital arithmetic comparator. If the comparison is equal, the comparator outputs 0; otherwise, it outputs +1 (-1) if reference frequency is faster (slower) than the DCO frequency. The result is then multiplied by gain Ki . Then, the DCO’s output frequency is adjusted.
Fig. 4.7 shows the step response of the proposed clock generator with DFC algorithm as compared with the sequential search. The step size of the sequential search is 1/128 (i.e. DCO is 8 bits) and the initial condition is set to 0.5 of normalized frequency to improve visualization. The proposed all-digital clock generator with DFC loop achieves fast locking in less than 10 iterations as illustrated in Fig. 4.7 (a). In contrast, the sequential search requires at least 50 iterations to achieve frequency acquisition as shown in Fig. 4.7 (b). Furthermore, if
the fine resolution of the DCO is inadequate, jitter variations will occur as indicated in Fig.
4.7 (c).
Fig. 4.7. Step response of the proposed clock generator with DFC loop control v.s. sequential search (a). Proposed. (b). Sequential search. (c). Jitter variation.
4.2.2 Structure of reference and DCO timing counters
The structure of reference timing counter is a ripple counter with reset function. The length of reference timing counter is dependent on the maximum DFC state of estimating DCO frequency. The structure of DCO timing counter is also a ripple counter with reset function. Therefore, most bits of the DCO timing counter are working in the low clock rate that can save power consumption. The length of the DCO timing counter is related to the multiplication factor (N) and the length of reference timing counter. If the maximum value of multiplication factor is P, L is formulated as
L =
é
log2Pù
(4.3) whereé ù
X represents the least integer greater than or equal to X. If the length of thereference timing counter is M, which is equal to the maximum number of DFC sampling state, the length of the DCO timing counter equals L+M. Fig. 4.8 shows the block diagram of quotient and remainder vectors in DCO timing counter with (AL+M-1 AL+M-2 ··· A2 A1 A0) bits.
The values of the quotient and remainder vectors in the i-th sampling state are
Qi=( AL+i-1 ··· Ai+1 Ai), (4.4) and
Ri=(Ai-1 ··· A1A0) (4.5) where Ai denotes the i-th bit of DCO timing counter. The measured values of Qi and Ri in the DCO timing counter then can be calculated as follows:
[Qi · 2i + Ri] = ú ú ê ù ê é
DCO i
T
C (4.6)
where TDCO denotes the cycle time of DCO generated frequency.
Fig. 4.8. Structure of quotient and remainder vectors in the DCO timing counter.
4.2.3 Structure of DFC Loop Controller
The structure of the DFC loop controller is shown in Fig. 4.9. The decision unit performs the digital arithmetic comparisons and updates the DCO control word (DCW). The decision unit compares the DCO timing counter based on frequency sampling period with power-of-2 input reference clock cycles as shown in Fig. 4.3. The decision unit also controls the frequency acquisition process and fine-tuning process. During the acquisition, loop gain control with binary search is applied to achieve fast locking. A multiplexer is used to select the DCO control code. Fig. 4.10(a) illustrates the state transition diagram of the DFC loop
Fig. 4.9. Structure of the proposed DFC loop controller.
Figure 4.10(b) illustrates the state transition diagram of the DFC loop controller. Sampling state 0 is the initial state, and both reference timing counter and DCO timing counter are reset in this state. After a sampling period of 21 ´ TREF, the DFC loop controller will switch from sampling state 0 into sampling state 1 for frequency comparison. If the quotient vector in DCO timing counter equals multiplication factor (N) and the frequency error in remainder vector is below the threshold region, state 1 enters into state 2 until 22 ´TREF sampling period and the DCO control word is left unchanged. Otherwise, the DFC loop controller changes the
DCW depending on the frequency comparison result. Then, it also switches back to sampling state 0 and reset both reference and DCO timing counters. The other DFC sampling states also perform similar operation as well except the maximum DFC sampling state. When the DFC loop controller enters the maximum DFC sampling state M, it will automatically switch back to sampling state 0.
Fig. 4.10. State transition of the proposed DFC loop controller (a). State of frequency search. (b). State of sampling period.