Digitally Controlled Oscillator with Novel Varactors
3.3 Structure of the Proposed DCO
3.3.1 Structure of DCO and Design Guide
Fig. 3.17 illustrates the structure of the proposed cell-based DCO with 15 bits binary weighted control (000016 ~ 7FFF16). The proposed DCO structure is separated into two stages:
the coarse-tuning stage and the fine-tuning stage. The higher seven bits of the control code are for coarse-tuning stage, and lower eight bits are for the fine-tuning stage. The coarse-tuning stage uses a 128-to-1 path selector for delay-chain selection. This selector is implemented by multistage tri-state buffers to reduce the loading effects of coarse-tuning buffers. The coarse decoder of the DCO decodes the 7 (=log2(128)) bits control code into 128 control signals.
This architecture has the advantage that operating frequency of DCO can be easily modified according to different specifications. The TPHL + TPLH ( = Tbuffer) of one coarse delay cell is about 385 ps in target 0.35-mm 2P4M CMOS standard cell library.
To increase the frequency resolution of the DCO, the fine-tuning stage is divided into fine1 and fine2 stages which are added after the coarse-tuning stage. The fine1 stage consists of 32
digitally-controlled varactors (DCVs) with capacitance difference ΔC. 32 identical NOR gates with ΔC are used to build one ΔC2 DCV. The total capacitance difference equals to 256 ΔC DCVs. The proposed NOR gate varactors for fine-tuning stage thus can improve delay resolution by 256 times compared to a simple buffer design.
The period of DCO’s output signals equals
Tperiod = Tcoarse + Tfine + Tconstant (3.6) where Tcoarse denotes the propagation delay time of coarse buffers, Tfine represents the fine-tuning delay time, and Tconstant is the constant factor for delay time because of one extra NAND gate, a multi-stage tri-state buffer and the intrinsic delay caused by capacitance (CI) of fine-tuning cells in the DCO ring.
Fig. 3.17. Proposed digitally-controlled oscillator with DCV in the fine-tuning stage.
Equation (3.6) can be rewritten as follows:
Tperiod = M x Tbuffer + N2 x ΔT2 + N1 x ΔT1 + Tconstant (3.7) where M denotes the number of selected coarse buffers. N1 and N2 represent the number that
DCVs are turned on in fine1 and fine2 stages, respectively. Meanwhile, ΔT1 and ΔT2 are variable delay which can be calculated from Eq. (3.5). Therefore, Eq. (3.7) provides an easy method of calculating the timing period of DCO output.
When design a DCO, the target frequency (Tperiod) range will be specified at first. Second, the coarse delay buffer with Tbuffer can be selected from a target standard cell library. Third, the resolution of DCO is defined by DCVs with Tfine based on Eq. (3.5) as discussed in the previous section. In order to simplify the DCO decoder, the relationship of Tfine and Tbuffer has better to be approximately power of 2 (i.e. 2n). This can be achieved by iteration of second and third steps. If the number of fine tune (2n ) is large, then different driving cells and different types of DCVs can be applied to save chip area. Finally, the number of coarse buffer M can be decided.
3.3.2 Design of DCVs
The proposed DCO with novel digitally controlled varactors is applied to all-digital frequency synthesizer design. The test chip is fabricated using a standard 0.35-mm 2P4M CMOS process. The designed DCO consists of two major functional blocks as illustrated in Fig. 3.16, namely the ring structure and decoder. Moreover, the decoder part is described by Verilog-HDL. The ring structure with DCVs is described at the gate-level. A Verilog-HDL model of DCVs is first built from HSPICE simulation results for co-simulation with other digital blocks. Next, source codes are synthesized to gate-level netlists and schematics for further simulation and verifications. Once the functions have been correctly verified, an automatic placement and routing (APR) tool is used to complete the physical layout.
In APR process, the designed DCO must be grouped in a restricted region to minimize the induced capacitance and the ring structure of DCO had to be placed regularly rather than randomly. Furthermore, the post-layout simulation is performed to ensure the monotonic response of DCO and timing resolution. The APR process will be refined until the target
specification is achieved.
3.3.3 Laboratory Test Result
Figure 3.18 is a microphotograph of the all-digital frequency synthesizer. The proposed DCO is located in the upper-left corner of the test chip and occupies 0.04 mm2 of chip area (i.e., 200 um x 200 um). This DCO has been measured for different settings. Initially, the DCO output frequency is directly measured using LeCory LC584A at 3.3V/25 0C, and the measured results demonstrate that the operating frequency of the DCO ranges from 18 to 214 MHz (i.e., 55.555ns to 4.673ns). Moreover, the average step resolution is 1.55ps. In Fig. 3.19, the measured results are compared to linear delay Eq. (3.7). Figure 3.19 also reveals that linear delay Eq. (3.7) can be used to estimate DCO timing period.
Fig. 3.18. Microphotograph of DCO test chip.
Table 3.2 lists the chip measurement results compared with conventional approaches [50,56-57]. The proposed DCO with 15 bits control codes achieves the finest LSB resolution and best portability. Additionally, the proposed DCO also consumes less power as compared with [50,57].
0
0 4096 8192 12288 16384 20480 24576 28672 32768 DCO control code
DCO period [ns]
Measured Equation (3.7)
Fig. 3.19. Chip measured results compared to linear Eq. (3.7) under 3.3V/25 0C.
Table 3.2. Comparison with existing DCOs
Process standard 0.35-mm, 0.18-mm, and 0.13-mm CMOS process. The DCO structure and the netlists are the same for these three processes, only cell name is replaced with according to each library. The control code of fine-tuning stage is 8 bit. The Tbuffer is 140 ps for selection in the 0.18-mm cell library. Similarly, the Tbuffer is 99.5 ps in 0.13-mm cell library. The resolution of DCV with NAND (3-input) gate as varactor is 0.55 ps/LSB and 0.40 ps/LSB in the 0.18-mm
and 0.13-mm CMOS process as shown in table 3.3, respectively.
Table 3.3. Resolution of Tbuffer and Tfine. Tbuffer and Tfine Resolution (unit: ps) (Typical, 25 oC)
0.18 mm (1.8V) 0.13 mm (1.2V) Tbuffer
1.49 0.55 0.40
385 140 99.5
0.35 mm (3.3V)
Tfine Tbuffer Tfine Tbuffer Tfine
Table 3.4. DCO output frequency range for different processes under typical conditions.
Table 3.4 lists the DCO output frequency range for different processes under typical condition. The coarse-bit means the bit width of the coarse-tuning control code. For example, coarse = 7 means there are 128 (=27) paths in the coarse-tuning stage of DCO. The total control word of DCO is 15 bit. The maximum operating frequency is dependent on the gate delay of the cell libraries. And the minimum operating frequency is dependent on how many coarse-tuning delay cells are used in the DCO’s coarse-tuning stage. Figure 3.20 shows the simulation results of different processes under typical condition. The DCO period is linear with the input DCO control code.
0 10 20 30 40 50 60
0 4096 8192 12288 16384 20480 24576 28672 32768 DCO control code
DCO period [ns]
0.35-um 0.18-um 0.13-um
Fig. 3.20. Circuit simulation with DCO 15-bit under different process (typical, 25 0C).
3.4 Summary
In this chapter, basic DCO concept is discussed at first. Then, a portable digitally controlled oscillator using two-input NOR gate as digitally controlled varactor is presented.
Different configurations based on NOR/NAND (2-inputs and 3-inputs) gates have also been investigated using HSPICE circuit simulator. The delay resolution of the proposed DCO can be determined using a simple linear equation, and the design guidelines are also gievn. Test chip measurement results show the average delay resolution of the proposed DCO is 1.55 ps.
The LSB resolution of DCO is enhanced 256 times as compared with single buffer stage.
Therefore, the proposed digitally controlled oscillator reduces the circuit complexity and also improves testability. Compared to conventional approaches, design time can also be reduced significantly by using Verilog hardware-description language and APR CAD tools.
Furthermore, the proposed DCO is suitable for SoC design, and has an excellent chance of first-time silicon success.