In RF transceivers, frequency synthesizer is one of the key components. Modern digital wireless system applications have demands on stringent specification, such as narrow channel spacing, large output power, high sensitivity and low bit error rate.
So, a frequency synthesizer must have several advantages like low phase nose, low spur, fast setting time, lower power consumption and small layout area.
How does to design a high frequency, fast settling time and low phase noise synthesizer? Several import circuit to increase performance for synthesizer be present in this work. For example: a perfect current matching charge pump decrease spur noise, a 5-GHz of quadrature output voltage control oscillator, high speed and small layout area divider and programmable integral N feedback divider. All the blocks have been researched, designed, simulated and testing in this work.
Therefore, this thesis focuses on implementing the new circuit of current-steering charge pump, which incorporates with concept of perfect current matching. The new circuit of charge pump suffers no program of clock feed through and charge sharing, and has the perfect current matching characteristics. It is implemented in 5GHz CMOS frequency synthesizer.
1.5 Main results and organization
This thesis implements a new perfect current match of charge pump circuit in a 1.8V and 5GHz 0.18um CMOS frequency synthesizer. The spurious sidebands at the center of adjacent channels are less than -69.52 dBc. The PLL has a bandwidth of 250 KHz and a phase noise of -107 dBc at 1MHz. The PLL loop settling time is 13.5uS. The total power consumption is 20.8mW based on 1.8V power supply. And the total power consumption is 18.8mW based on 1.8V power supply with 1.4V power supply for PFD, program counter and swallow counter.
The thesis is organized as follows. In chapter 2, the fundamentals of frequency synthesizer include the synthesizer architecture, reason, circuit, simulation results and their advantages and disadvantages are discussed. In chapter 3, presents experimental results, compared the results and discussion. In chapter 4, concludes the thesis with a summary and future work.
CHAPTER 2
CIRCUIT ARCHITECTIRE AND SIMULATION RESULTS
In the previous chapter that propose wideband PLL architecture to implement a high performance frequency synthesizer with noisy on-chip components. In the chapter that also discusses the PLL design fundamentals, optimization of the loop bandwidth and pointed out the optimization of the loop bandwidth depends on the noise spectrum of each individual noise source. The important of the discusser are the structure of the current match charge pump and high speed frequency divider is chosen which has the trade off about power dissipation and layout area.
Anyway, in this chapter the circuit design of each block in a PLL will be discussed. The most important block is the integrated quadrature VCO and perfect current match charge pump. And the phase/frequency detector, loop filter, and frequency divider are also important in realizing a high performance frequency synthesizer. So, architecture of every block will be analysis, design and simulate detail.
2.1 Phase-Locked Loop Design Fundamentals
2.1.1 S-Domain model of PLL
The majority of all PLL design problems can be approached using the Laplace transform technique. All operating conditions are considered and evaluated. The Laplace transform is valid only for positive real time linear parameters; thus, its use must be justified for the PLL which includes both linear and nonlinear functions.
Fig. 2.1 shows the basic block diagram of a PLL. The circuit is called a
“Phase-Locked Loop” because the loop will automatically adjust the phase of the VCO output signal, θout, and synchronize the VCO output signal to the reference signal. After locked at the reference frequency, the signals can be represented as follows:
The frequency divider divides both of the VCO frequency and phase by a factor
Phase
N, thus
The phase detector gives an output voltage proportional to the phase difference between the reference signal and the feedback signal:
vpd( )t =Kpd
(
θref ( )t −θfb( )t)
(2-3)There Kpd is the phase detector gain and its unit is V/rad.
The voltage Vpd(t) is then filtered by the low-pass loop filter whose transfer function is F(s). The noise and the high-frequency components of Vpd(t) are suppressed.
Fig. 2.2 VCO output frequency with control voltage curve.
As shown in Fig. 2.2, the control voltage Vctrl determines the VCO output frequency. The relation between the VCO frequency and the control voltage can be written as
fout
( )
t = fFR( )
t +Kvco ⋅vctrl( )
t (2-4)There fFR is the “free running” frequency which denotes VCO oscillation frequency when Vctrl = 0 and Kvco is the VCO gain in units of Hz/V. Further, fout can
There Vctrl is the VCO control voltage corresponding to the locked frequency Nfref . Because frequency is the derivative of phase, the excess phase θout in equation. (2-1) can be expressed as
Taking the Laplace transform, the following result can be obtained
( ) ( )
The transfer function of the VCO is
( )
An ac linear model of the PLL now can be shown in Fig. 2.3. The phase transfer function of the PLL is
Fig. 2.3 PLL AC linear model
2.1.2 Steady state phase error analysis
Various inputs can be applied to a system. Typically, these include step position, velocity, and acceleration. The response of type 1, 2, and 3 systems will be examined with the various inputs.
In Fig. 2.3 θe represents the phase error that exits in the phase detector between the incoming reference signalθref and the feedback θout. In evaluating a system, θe must be examined in order to determine if the steady state and transient characteristics are optimum and/or satisfactory. The transient response is a function of loop stability and is covered in the next section. The steady state evaluation can be simplified with the use of the final value theorem associated with Laplace. This theorem permits finding the steady state system errorθe resulting from the inputθref
without transforming back to the time domain.
Simply stated
[ ] ( )
t[
s e( )
s]
Lim θ =lim θ (2-10) Where
θe
( )
s =θref( )
s /(1+G( ) ( )
s ⋅H s ) (2-11) The input signal θref is characterized as follows:Step position: θref (t) = Cp , t ≧ 0 Or, in Laplace notation: θref (s) = Cp / s
There Cp is the magnitude of the phase step in radians. This corresponds to shifting the phase of the incoming reference signal by Cp radians:
Step velocity: θref (t) = Cv · t, t ≧ 0 Or, in Laplace notation: θref (s) = Cv / s²
The Cv is the magnitude of the rate of change of phase in radians per second.
This corresponds to inputting a frequency that is different than the feedback portion of the VCO frequency. Thus, Cv is the frequency difference in radians per second seen at the phase detector.
Step velocity: θref (t) = Ca · t², t ≧ 0 Or, in Laplace notation: θref (s) = 2 · Ca / s³
The Ca is the magnitude of the frequency rate of change in radians per seconds per second. This is characterized by a time variant frequency input.
Similarly, applying the three inputs into type 1, 2 and 3 systems and utilizing the final value theorem, the following table 3 can be constructed to show the respective steady state phase errors. So, we chose type 2 and four order system in this work.
Table 3 Steady state phase error for various systems Type 1 Type 2 Type 3
Step position Zero Zero Zero
Step velocity Constant Zero Zero
Step Acceleration Continually Increasing
Constant Zero
2.1.3 PLL noise source
Any noise in the circuit or environment will create phase disturbance. In Fig.
1.4, a non-ideal frequency synthesizer spectrum is show. It is no longer a single frequency tone but rather a smeared version. The energy under the skirt is phase noise. Sometimes the energy is concentrated at frequencies other than the desired frequency, appearing as a spike above the skirt. This energy is due to a spurious tone.
Phase noise and spurious tones are the two key performance parameters of a frequency synthesizer.
The PLL transfer function is easer to define from Fig. 2.3.
T(s) = G(s) / (1 + G(s) · H(s)) (2-12) G(s) = Kpd · Kvco · F(s) / s (2-13) H(s) = 1/N (2-14) Below is table 4 showing various noise sources and the transfer functions that multiply each one.
It should be apparent that the phase detector noise, input reference noise, and N divider noise all contain common factor T(s) in their transfer functions. For
this reason, all of these noise sources will be referred to as in band noise source.
But the VCO noise distribute in high frequency band. That the in band sources dominate within the loop bandwidth and the VCO noise dominates outside of the loop bandwidth. This can be seen in Fig. 2.4. The phase noise measured at an offset that is close to the carrier is basically independent of loop bandwidth, provided that the loop bandwidth is sufficiently wide to eliminate the VCO noise. However, the phase error is more dependent on the loop bandwidth. To theoretically design for the lowest phase error, this means that one needs to design such that VCO noise contribution at loop bandwidth is equal to the total noise contribution from the other source noise at bandwidth. If the VCO is noisily relative to the PLL, than this number would be smaller, and if the PLL is noisily relative to the VCO, than this number would be large.
Fig. 2.4 Phase noise spectral for a PLL
2.2 Circuit realization
A Phase-Locked-Loop-Based frequency synthesizer with narrow loop bandwidth is the most commonly used techniques due to its high performance, namely, low phase noise and low spurious tones. But the need for off chip high-Q components is not amenable to the integration of the synthesizer. We used TSMC 0.18um process to implement the frequency synthesizer that has fast settling time and high Q devices on-chip. And the on-chip components are difficult to increase Q value more than off chip high Q components. So, the VCO’s turning range and gain (frequency over control voltage) curve is hard to control!
First, we must to design a VCO before to design other block of frequency synthesizer. Because many key parameters like “VCO output frequency”, “VCO turning range” and “VCO gain curve (Kvco)” affect the all loop of properties seriously.
And a frequency synthesizer loop characteristic determine from these key parameters.
A “Phase-Locked-Loop” is a loop which locks the output phase or frequency to an accurate reference. In Fig. 2.5 shows the function block diagram of this work. A voltage-controlled oscillator generates an output waveform at a frequency set by the control voltage Vctrl. The Phase/Frequency Detector (PFD) compares the phase and frequency of a divided reference frequency Fref with the divider output phase and frequency. When the loop is locked, the PFD sees two identical waveforms at its inputs and Fout equals to N times of Fref. For some reason Fref > Fb, Vctrl goes up and the VCO output frequency increase. Vice versa, if Fref < Fb, Vctrl goes down and VCO
output decreases. A loop filter (LPF) is used to stabilize the loop by introducing zeros and poles into the loop. In this work include two perfect current match charge pumps to decrease spurious tones power level.
Fig. 2.5 Frequency synthesizer function block of this thesis
A typical PLL-based Frequency synthesizer comprises both high and low frequency blocks. The high frequency blocks, mainly the VCO and first stage of the frequency dividers, are main power consuming blocks, especially in a CMOS implementation. Anyway, several important design considerations about design frequency synthesizer in this these. One, the VCO input control voltage range must to collocate with charge pump output voltage range. In order to decrease spurious noise, charge pump driving and sourcing currents must be equal. So the cascode structure is used in this design to decrease MOS λ effect. The current mode LPF
maybe can be used but buffer input offset must low enough. Two, the high frequency
÷2 divider input signal must to AC couple from VCO output. Three, the quadrature VCO output signals need to add buffer to driver out for easy testing. Five, the signal from program counter feedback to PFD and add some buffer to drive to PAD. Other design considerations will be discussed in this chapter every sub-chapter.
2.2.1 Circuit realization of current-match charge pump
In cellular applications, narrow loop bandwidth is desired in order to minimize the spectral components due to spurious tones in the output spectrum. So, charge pump is a low frequency block and the current of driving and sourcing to low-pass-filter (LPF) equal each other is very important. The spurious tones are generated because different currents of driving and sourcing to drive LPF. In this work has two perfect current matching charge pump circuits be implemented that will be compared at following.
A simple implementation of the charge pump based on the current steering concept is shown in Fig. 2.6. Different UP and DN signals from the phase/frequency detector (PFD) are used to steer the current one way or the other in the differential pair in the charge pump.
Fig. 2.6 Current steering of charge pump
There are several non-idealities resulting in a non-zero static phase error and fref
PFD
creation of spurious tones. The top leakage current may not equal the bottom leakage current at up and down turn on together, resulting a net charge flowing in or out of the loop filter in one comparison period. In the PLL locking condition, the net charge must compensated by a different on-time of the two switches. For example, if Ip leakage is small than In leakage, the UP signal must occur slightly earlier than the DN signal to compensate for the net charge flow out of the loop filter. This means the reference edge should come slightly earlier than VCO edge if we assume the PFD is ideal. The mismatch between the leakages is one form of static mismatch. Another form of the static mismatch is the DC current level difference when both switches are on. The effect is the same as in the case of leakage current mismatch. The switch has different finite switching on or off time is dynamic mismatch. Both dynamic and static mismatch result in net charge flows in or out of the loop filter periodically, at the rate of the comparison frequency. The result, the control voltage has a ripple at the comparison frequency, which modulates the VCO frequency and generates spurious tones at multiples of the comparison frequency away from the carrier. Fig.
2.7 shows the waveforms of the LPF with non-idealities and we can cancel the effect is delay balance in up and down path of PFD layout. And Fig. 2.8 shows the control voltage of VCO at up (UP) and down (DN) current mismatch and we can decrease the effect which use current match charge pump.
Fig. 2.7 Non-idealities waveform of the charge pump switch
Fig. 2.8 Non-idealities waveform of the charge pump current-mismatch
In Fig. 2.9 shows the one of this work about the perfect current match of charge pump circuit [5]. In this structure, a wide input range OP. showing in Fig. 2.10 makes negative feedback to apply the voltage of Vctrl and Vtrac are equal and makes sure Iref, Iup and Idown are equal. This structure has perfect current match characteristic but that still has three problems to make some current mismatch.
(1) Iup and Idown current mirror source is not the same path. Iup is mirrored from M5 and Idown is mirrored from M6. If process has some variations then M5
and M6 drain current are not equal.
(2) Even through the Vctrl and Vtrace will be lock at the same voltage (assume no offset of OP.). The drain voltage of M3 and M7 or M4 and M8 are not equal because Vctrl voltage sometime close to power and sometime close to ground.
The drain voltage of M3 and M1 are not equal, too.
(3) Assume the drain current of M1 with M3 and M2 with M4 are equal. But the structures haven’t guaranteed the voltage of Va with Va1 and Vb with Vb1 are equal. So, the charge pump has current mismatch in Iup and Idown.
Fig. 2.9 perfect current-match of charge pump circuit in this work (charge pump type 1)
Fig. 2.10 Wide input range OP. circuit
One important design technique to decrease the Iup and Idn mismatch about charge pump is in charge pump bias block. Anyway, many ways has to decrease the Iup and Idn mismatch about charge pump at one time, but if we can not let Iup and Idn currents mirrored from equal original only one source, that decrease the Iup and Idn mismatch is insufficient. So, another perfect current match charge pump circuit to add a bias block let Iup and Idn currents mirrored from equal original current showing in Fig. 2.11 to improve those drawbacks in Fig. 2.9.
In order to cancel the parasitical capacitors at terminal drain to source on M2
and M4 to happen charged shelling with loop filter capacitors each other. We added a unit gain buffer connects from point Ve to point Vctrl and it let two point voltages been equal. The unit gain buffer need rail to rail input and rail to rail output, because the voltage of VCO input turning range is wide. Fig. 2.12 shows the rail-to rail unit gain buffer circuit and another function of the buffer is sinking current from M2
when UP is low and sourcing current from M4 when UP is high. In this charge pump, there are three techniques to improve current match.
(1) Ip / In of up/down current are mirrored from the same path is Icp.
(2) OP2 and OP3 make sure the voltage of Va close to Vb and the voltage of Vc
close to Vd.
(3) Cascode devices of M5 and M6 are increasing impedance and decreasing channel length modulation effect.
(4) Use transmission gate switches to increase control range, decrease switch on resistance, decrease clock feed-through and increase speed.
Fig. 2.11 Improve the current-match of charge pump circuit in this work (Charge pump type 2)
Cascode structure of current source can be used to reduce the current mismatch
But the charge pump output swing needs to meet the VCO’s turning range. And minimum length devices can be used as switches to reduce the switching time at switches on/off, hence reduce the dynamic mismatch.
The circuit working principle is two current paths of Ib be generated from a bias circuit show in Fig. 2.13. Those current paths provide M8, M7 (Fig. 2.11) gate terminals voltage and mirror the current to Icp. And the circuit of OP2 and OP3
showing in Fig. 2.14 make sure Va with Vb and Vc with Vd are equal and another avail is to increase current devices impedance about sourcing and sinking. The current Ip
source to low pass filter when UP is high and the current In sink from low pass filter when DN is high. If UP and DN are high together then current of Ip drift into current of In. And the point Vctrl connects to low pass filter. If the charge pump sourcing and sinking current are match then there are not any current to charge or discharge low pass filter. So, the structure of charge pump has perfect current match characteristic.
Fig. 2.12 Rail-to-rail OP circuit in charge pump type 2 (OP1)
Fig. 2.13 Current bias of charge pump in this work
(a) OP2 circuit (b) OP3 circuit Fig. 2.14 OP circuit of charge pump in this work
2.2.2 Low pass filter design
The loop filter in this work is a third-order passive filter that consists of two resistors and three capacitors. The resulting PLL is then a type-2 fourth-order loop
The loop filter in this work is a third-order passive filter that consists of two resistors and three capacitors. The resulting PLL is then a type-2 fourth-order loop