CHAPTER 2 CIRCUIT ARCHITECTURE AND
2.2 CIRCUIT REALIZATION
2.2.1 CIRCUIT REALIZATION OF CURRENT-MATCH CHARGE
In cellular applications, narrow loop bandwidth is desired in order to minimize the spectral components due to spurious tones in the output spectrum. So, charge pump is a low frequency block and the current of driving and sourcing to low-pass-filter (LPF) equal each other is very important. The spurious tones are generated because different currents of driving and sourcing to drive LPF. In this work has two perfect current matching charge pump circuits be implemented that will be compared at following.
A simple implementation of the charge pump based on the current steering concept is shown in Fig. 2.6. Different UP and DN signals from the phase/frequency detector (PFD) are used to steer the current one way or the other in the differential pair in the charge pump.
Fig. 2.6 Current steering of charge pump
There are several non-idealities resulting in a non-zero static phase error and fref
PFD
creation of spurious tones. The top leakage current may not equal the bottom leakage current at up and down turn on together, resulting a net charge flowing in or out of the loop filter in one comparison period. In the PLL locking condition, the net charge must compensated by a different on-time of the two switches. For example, if Ip leakage is small than In leakage, the UP signal must occur slightly earlier than the DN signal to compensate for the net charge flow out of the loop filter. This means the reference edge should come slightly earlier than VCO edge if we assume the PFD is ideal. The mismatch between the leakages is one form of static mismatch. Another form of the static mismatch is the DC current level difference when both switches are on. The effect is the same as in the case of leakage current mismatch. The switch has different finite switching on or off time is dynamic mismatch. Both dynamic and static mismatch result in net charge flows in or out of the loop filter periodically, at the rate of the comparison frequency. The result, the control voltage has a ripple at the comparison frequency, which modulates the VCO frequency and generates spurious tones at multiples of the comparison frequency away from the carrier. Fig.
2.7 shows the waveforms of the LPF with non-idealities and we can cancel the effect is delay balance in up and down path of PFD layout. And Fig. 2.8 shows the control voltage of VCO at up (UP) and down (DN) current mismatch and we can decrease the effect which use current match charge pump.
Fig. 2.7 Non-idealities waveform of the charge pump switch
Fig. 2.8 Non-idealities waveform of the charge pump current-mismatch
In Fig. 2.9 shows the one of this work about the perfect current match of charge pump circuit [5]. In this structure, a wide input range OP. showing in Fig. 2.10 makes negative feedback to apply the voltage of Vctrl and Vtrac are equal and makes sure Iref, Iup and Idown are equal. This structure has perfect current match characteristic but that still has three problems to make some current mismatch.
(1) Iup and Idown current mirror source is not the same path. Iup is mirrored from M5 and Idown is mirrored from M6. If process has some variations then M5
and M6 drain current are not equal.
(2) Even through the Vctrl and Vtrace will be lock at the same voltage (assume no offset of OP.). The drain voltage of M3 and M7 or M4 and M8 are not equal because Vctrl voltage sometime close to power and sometime close to ground.
The drain voltage of M3 and M1 are not equal, too.
(3) Assume the drain current of M1 with M3 and M2 with M4 are equal. But the structures haven’t guaranteed the voltage of Va with Va1 and Vb with Vb1 are equal. So, the charge pump has current mismatch in Iup and Idown.
Fig. 2.9 perfect current-match of charge pump circuit in this work (charge pump type 1)
Fig. 2.10 Wide input range OP. circuit
One important design technique to decrease the Iup and Idn mismatch about charge pump is in charge pump bias block. Anyway, many ways has to decrease the Iup and Idn mismatch about charge pump at one time, but if we can not let Iup and Idn currents mirrored from equal original only one source, that decrease the Iup and Idn mismatch is insufficient. So, another perfect current match charge pump circuit to add a bias block let Iup and Idn currents mirrored from equal original current showing in Fig. 2.11 to improve those drawbacks in Fig. 2.9.
In order to cancel the parasitical capacitors at terminal drain to source on M2
and M4 to happen charged shelling with loop filter capacitors each other. We added a unit gain buffer connects from point Ve to point Vctrl and it let two point voltages been equal. The unit gain buffer need rail to rail input and rail to rail output, because the voltage of VCO input turning range is wide. Fig. 2.12 shows the rail-to rail unit gain buffer circuit and another function of the buffer is sinking current from M2
when UP is low and sourcing current from M4 when UP is high. In this charge pump, there are three techniques to improve current match.
(1) Ip / In of up/down current are mirrored from the same path is Icp.
(2) OP2 and OP3 make sure the voltage of Va close to Vb and the voltage of Vc
close to Vd.
(3) Cascode devices of M5 and M6 are increasing impedance and decreasing channel length modulation effect.
(4) Use transmission gate switches to increase control range, decrease switch on resistance, decrease clock feed-through and increase speed.
Fig. 2.11 Improve the current-match of charge pump circuit in this work (Charge pump type 2)
Cascode structure of current source can be used to reduce the current mismatch
But the charge pump output swing needs to meet the VCO’s turning range. And minimum length devices can be used as switches to reduce the switching time at switches on/off, hence reduce the dynamic mismatch.
The circuit working principle is two current paths of Ib be generated from a bias circuit show in Fig. 2.13. Those current paths provide M8, M7 (Fig. 2.11) gate terminals voltage and mirror the current to Icp. And the circuit of OP2 and OP3
showing in Fig. 2.14 make sure Va with Vb and Vc with Vd are equal and another avail is to increase current devices impedance about sourcing and sinking. The current Ip
source to low pass filter when UP is high and the current In sink from low pass filter when DN is high. If UP and DN are high together then current of Ip drift into current of In. And the point Vctrl connects to low pass filter. If the charge pump sourcing and sinking current are match then there are not any current to charge or discharge low pass filter. So, the structure of charge pump has perfect current match characteristic.
Fig. 2.12 Rail-to-rail OP circuit in charge pump type 2 (OP1)
Fig. 2.13 Current bias of charge pump in this work
(a) OP2 circuit (b) OP3 circuit Fig. 2.14 OP circuit of charge pump in this work
2.2.2 Low pass filter design
The loop filter in this work is a third-order passive filter that consists of two resistors and three capacitors. The resulting PLL is then a type-2 fourth-order loop which provides great noise suppression for the PLL output spurious level. The standard third-order passive loop filter configuration shown in Fig. 2.15 is utilized.
The resisters R1 and capacitors C1, C2 are off chip devices, the resister R3 and capacitor C3 are build in chip. Resistor R1 and C1 in the loop filter generate a pole at the origin and a zero at 1/ (R1C1). Capacitor C2 and combination of R3 and C3 are used to add extra poles at frequency higher than the PLL bandwidth to reduce reference feed-through and decrease the spurious sidebands at harmonics of the reference frequency. The capacitors and resistors of the loop filter should be properly chosen to perform the required filtering function and maintain the stability of the loop without introducing too much noise. The component values in the filter are calculated following the design flow.
(1) The average VCO gain in this work is about 480 MHz/V.
Kvco = 480 MHz/V (2-15) (2) The input reference clock is 10MHz.
Fref = 10 MHz (2-16) (3) A 250 kHz open loop bandwidth is chosen.
K = 250 KHz (2-17) (4) 67°phase margin is chosen. It corresponds to aγof 5. In other words, the zero
ωz is placed a factor 5 below K, and the pole ωp1 is placed a factor 5 above K,
to obtain a phase margin of approximately 67°.
ωz = 2π‧50 kHz (2-18) ωp1 = 2π‧1.25 MHz (2-19) (5) An equivalent charge pump current is 500uA.
Icp = 500 uA (2-20) (6) The average divider is 525. That includes program counter, prescaler divider
(M) and dive-by-2.
(9) An additional attenuation value of the reference spur of 20 dB is chosen, thus MHz
Fig. 2.15 Type 2 third-order low pass filter
However, since discrete resistors and capacitors are only available in standard values, components near the calculated values are used. Table 5 gives the selected component values. C1 and C2 are polyester film capacitor. Although the physical size is larger than the ceramic capacitor, film capacitors do not experience random voltage changes associated with the ceramic type [28]. C3 is chosen somewhat smaller then the calculated value in consideration of the VCO tuning port parasitic capacitance.
Final PLL Parameters In This Work
VCO gain Kvco 480 MHz/V
Open loop gain bandwidth K 250 kHz
Zero frequency ωz 50 kHz
First pole frequency ωp1 1.25 MHz Second pole frequency ωp2 3.33 MHz
Passive elements R1 3.9 kΩ
C1 820 pF
C2 33 pF
R2 24 kΩ
C3 2 pF
Table 5 Final frequency synthesizer parameters
2.2.3 Circuit realization of quadrature VCO
Modern receiver architectures, such as the zero-IF receiver and the low-IF receiver, allow a high degree of integration and are therefore often utilized in wireless transceiver designs. In order to avoid loss of information, these architectures normally have an in-phase and quadrature signal processing path. Usually the receiver signal is split after the LNA and multiplied with a quadrature signal source.
Quadrature signal may also be needed at the transmit side of a wireless transceiver. Base band data streams are multiplied with a quadrature carrier signal, added, and transmitted. Quadrature LC oscillator usually has large layout area, especially on-chip inductors layout area. ‘Optimally Coupled 5-GHz Quadrature LC Oscillator [22]’ and ‘Super harmonic Coupling 5-GHz CMOS Quadrature VCO [23]’
also need four inductors in two close couple stage VCO. This work use two inductors in two close couple stage VCO to decrease layout area and keeps perfect performance, the circuit show in Fig. 2.16. The inductance is about 2.368nH and the varactors are about 2.92pF in ideal conditions.
Anyway, there are basically two types of VCO, tuned and un-tuned. Un-tuned oscillators have inferior spectral purity compared to tuned oscillator for the same power consumption. The performance of a tuned oscillator depends on the quality factor Q of the tuned element. A typical example of an un-tuned oscillator is a ring oscillator. It consists of n inverters in a ring and the end of the ring is 180∘out of phase from the beginning of the ring.
Fig. 2.16 VCO circuit in this work
However, when the VCO is integrated with other circuits, noise can be coupled through the substrate. The supply line might not be as clean as the supply in the stand-along VCO. The power supply rejection ratio becomes very important. If the output is differential, any variation in the control voltage or supply will result in variation in the effective capacitance in the tank. Hence the oscillation frequency will also fluctuate with the control voltage or supply.
And, if the inductors are the main source of noise, maximizing their quality factor would improve the phase noise significantly. However, in multi-GHz VCO’s with short channel transistors, inductors are not the main source of noise and a better design strategy is not maximize the effective parallel impedance of the RLC tank at resonance. This choice increases the oscillation amplitude for a given power
consumption and hence reduces the phase noise caused by the noise injection from the active devices. Since inductors are the main source of loss in the tank, the LQ product should be maximized to maximize the effective parallel impedance of the tank at resonance, where L is the inductance and Q is the quality factor of the spiral inductors. It is important to realize that maximizing Q along does not necessarily maximize the LQ product, and it is the latter that matters here.
In a standard process, metal layers can be used to construct on-chip spiral inductors. Fig. 2.17 shows a square spiral inductor. Several issues associated with the on-chip inductor need to be mentioned. First, there is series resistance in the metal layers which reduces the quality factor of the inductor. Second, there is capacitive coupling from the metal to substrate which reduces the self-resonant frequency of the inductor. Third, there is resistance in the conducting substrate which also reduces the quality factor of the inductor. These non-idealities are modeled in the lumped π model.
Fig. 2.17 On chip spiral inductors layout and equivalent circuit
In a standard process, the N+/Nwell junction can be used as a varactor. Fig. 2.18 shows the RF model about varactor. The distance between the N+ regions is the current path and it should be kept minimum or minimum series resistance associated with the varactor. Sidewall capacitance has a larger Q and less tuning range because of the higher doping profile. Bottom-plate capacitance has a lower Q and larger tuning because of the lower doping profile.
Fig. 2.18 An N+/Nwell junction varactor
The Q of the tank thus is dominated by the Q of inductor rather than Q of varactor. But when the operating frequency is high, the Q of varactor is reduced because the Q of varactor is inversely proportional to the operating frequency. In the mean time, the Q of the inductor is proportional to the operating frequency. This is, at higher frequencies, the Q of the varactor is more important. Fig. 2.19 shows the low Q and high Q structures of LC tank of VCO. That use varactor to replace the capacitor and switch to reach high Q.
Fig. 2.19 High Q structure of LC tank VCO
A general LC-VCO can be symbolized as in Fig. 2.20. The oscillator consists of an inductor L and a capacitor C, building a parallel resonance tank Rtank! We need an active element –Rtank, compensating the losses of the inductor (RtankL) and the losses of the capacitor (RtankC). As the capacitance C is proportional to a tuning input voltage, the circuit results in a VCO with angular center frequency.
Wc = 1 / √LC (2-27)
Fig. 2.20 LC tuned VCO model
The capacitor C in Fig. 20 not only consists of a variable capacitor to tune the oscillator, but it also includes the parasitic or fixed capacitances of the inductor, the active elements, and the load. Anyway, to get the LC tank resistance value was
important before to design the resistance –Rtank value. Fig. 21, (a) show the LC tank simulation circuit of this work and Fig. 21, (b) show the real part and imaginary part about LC tank simulation resistance.
(a) Effect resistance of LC tank (b) Real part of LC tank resistance at 6GHz Fig. 2.21 The resistance simulation of LC tank in tuned VCO
In Fig. 16 shows the schematic of the VCO. Two cross-coupled transistors generate the negative impedance (-Rtank) required to cancel the losses of the negative impedance required to cancel the losses of the RLC tank. On-chip spiral inductors with patterned ground shield are used in this design. The three main requirements for the VCO are low phase noise, low power consumption and small layout area.
To improve the 1/f3 corner of the phase noise it is convenient to have a symmetric tank (gm,n = gm,p)[13][14]. For symmetric tanks, gneg,tank is given by the expression,
gneg,tank = - (gm,n + gm,p) / 2 = - gm,n (2-28)
To make sure this VCO can oscillate normally, the loop gain must at least 3 hence,
gm,n >= A * Gtank, max and A>=3 (2-29) Gtank, max = Rtank = LC tank resistance (2-30) Rtank = Re(Ztank), when Im(Ztank) = 0 (2-31) The VCO, which is another dominant source of PLL power consumption, need to be carefully optimized in terms of dissipation, without degrading tuning range and phase noise performance. The power consumption of an oscillator is inversely proportional to its phase noise level. Therefore, the efficiency of an oscillator topology is typically quantified in terms of the noise power product. The structure had perfect characteristics about low power, low phase noise and high output swing.
The simulation results describe in section 2.3.1.
The selection of VCO gain (Kvco) and VCO input range (Vctrl) are tradeoff in PLL.
Table 6 shows the influences in PLL about the tradeoff of Kvco and Vctrl. The best choices about them are middleman values.
Kvco ↓ and Vctrl ↑ Kvco ↑ and Vctrl ↓
VCO Output Sensitivity Low High
Loop Damping Effect Low High
Low-pass-filter Bandwidth High Bandwidth Narrow Bandwidth
Loop Settling Time Small Large
Low-pass-filter size Small Large
Charge pump output range High Low
Charge pump channel length modulation effect
High Low
Table 6 The influences of Kvco and Vctrl in PLL
2.2.4 Circuit realization of integer-N divider
In the block of integer-N include a divide-by-2 divider and pulse swallow frequency divider. The block most difficult to design is the first ÷2 stage, which should operate at 5.3 GHz or more, and the speed and power consumption be dominated at the block. Fig. 2.22 shows the divide-by-2 divider in this work. The structure has very small layout area and not bad power consumption. This structure worked at differential signals to improve low noise and low power characteristics.
Using Pseudo-NMOS gates enables high-speed operation which providing large output swing. The ÷2 divider input signals come from phase 0∘and phase 180∘of quadrature VCO output which signals AC couple to an inverter whose input and output are tied together to get the correct dc level. The voltage of VB can control the output amplitude and common mode voltage of ÷2 divider.
Fig. 2.22 Pseudo-NMOS divider-by-two circuit (HDIV2) and input ac coupling
The divider structure of SCL was found to work only up to the 4.8 GHz in post-simulation in the process and another the divider structure of TSMP has 25%
duty cycle of the output signals is less convenient for phase switching. This led to our choice of pseudo-NMOS logic despite its high power consumption.
Fig. 2.23 The ÷8/9 prescaler divider (Np = 8)
The pulse swallow frequency divider (÷M) consists of a ÷8/9 prescaler followed by a program and pulse swallow counter. Fig. 2.23 shows the ÷8/9 prescaler divider and the prescaler consists of two dual-modulus divide-by-2/3 and two divide-by-2 frequency divider. The modulus control (MC) input selects between divide-by-8 and diide-by-9. A “÷2–AND” block circuit is a ÷3 stage and the logic diagram is shown in Fig. 2.24 (a). The combination of the AND gate and flip-flop is implemented as shown in Fig. 2.24 (b). The parallel branches implement the AND function.
(a) ÷3 stage logic diagram (b) ÷3 stage circuit implement Fig. 2.24 The structure of divide-by-three stage
Only one CMOS logic ripple counter is used for both program and pulse swallow counters, which are shown in Fig. 2.25.
Total divide value is N, S is swallow counter value and P is program counter value.
M = Np · S + P + 1 (2-32)
M = Np · S + P + 1 (2-32)