CIRCUIT REALIZATION OF QUADRATURE VCO…

Modern receiver architectures, such as the zero-IF receiver and the low-IF receiver, allow a high degree of integration and are therefore often utilized in wireless transceiver designs. In order to avoid loss of information, these architectures normally have an in-phase and quadrature signal processing path. Usually the receiver signal is split after the LNA and multiplied with a quadrature signal source.

Quadrature signal may also be needed at the transmit side of a wireless transceiver. Base band data streams are multiplied with a quadrature carrier signal, added, and transmitted. Quadrature LC oscillator usually has large layout area, especially on-chip inductors layout area. ‘Optimally Coupled 5-GHz Quadrature LC Oscillator [22]’ and ‘Super harmonic Coupling 5-GHz CMOS Quadrature VCO [23]’

also need four inductors in two close couple stage VCO. This work use two inductors in two close couple stage VCO to decrease layout area and keeps perfect performance, the circuit show in Fig. 2.16. The inductance is about 2.368nH and the varactors are about 2.92pF in ideal conditions.

Anyway, there are basically two types of VCO, tuned and un-tuned. Un-tuned oscillators have inferior spectral purity compared to tuned oscillator for the same power consumption. The performance of a tuned oscillator depends on the quality factor Q of the tuned element. A typical example of an un-tuned oscillator is a ring oscillator. It consists of n inverters in a ring and the end of the ring is 180∘out of phase from the beginning of the ring.

Fig. 2.16 VCO circuit in this work

However, when the VCO is integrated with other circuits, noise can be coupled through the substrate. The supply line might not be as clean as the supply in the stand-along VCO. The power supply rejection ratio becomes very important. If the output is differential, any variation in the control voltage or supply will result in variation in the effective capacitance in the tank. Hence the oscillation frequency will also fluctuate with the control voltage or supply.

And, if the inductors are the main source of noise, maximizing their quality factor would improve the phase noise significantly. However, in multi-GHz VCO’s with short channel transistors, inductors are not the main source of noise and a better design strategy is not maximize the effective parallel impedance of the RLC tank at resonance. This choice increases the oscillation amplitude for a given power

consumption and hence reduces the phase noise caused by the noise injection from the active devices. Since inductors are the main source of loss in the tank, the LQ product should be maximized to maximize the effective parallel impedance of the tank at resonance, where L is the inductance and Q is the quality factor of the spiral inductors. It is important to realize that maximizing Q along does not necessarily maximize the LQ product, and it is the latter that matters here.

In a standard process, metal layers can be used to construct on-chip spiral inductors. Fig. 2.17 shows a square spiral inductor. Several issues associated with the on-chip inductor need to be mentioned. First, there is series resistance in the metal layers which reduces the quality factor of the inductor. Second, there is capacitive coupling from the metal to substrate which reduces the self-resonant frequency of the inductor. Third, there is resistance in the conducting substrate which also reduces the quality factor of the inductor. These non-idealities are modeled in the lumped π model.

Fig. 2.17 On chip spiral inductors layout and equivalent circuit

In a standard process, the N+/Nwell junction can be used as a varactor. Fig. 2.18 shows the RF model about varactor. The distance between the N+ regions is the current path and it should be kept minimum or minimum series resistance associated with the varactor. Sidewall capacitance has a larger Q and less tuning range because of the higher doping profile. Bottom-plate capacitance has a lower Q and larger tuning because of the lower doping profile.

Fig. 2.18 An N+/Nwell junction varactor

The Q of the tank thus is dominated by the Q of inductor rather than Q of varactor. But when the operating frequency is high, the Q of varactor is reduced because the Q of varactor is inversely proportional to the operating frequency. In the mean time, the Q of the inductor is proportional to the operating frequency. This is, at higher frequencies, the Q of the varactor is more important. Fig. 2.19 shows the low Q and high Q structures of LC tank of VCO. That use varactor to replace the capacitor and switch to reach high Q.

Fig. 2.19 High Q structure of LC tank VCO

A general LC-VCO can be symbolized as in Fig. 2.20. The oscillator consists of an inductor L and a capacitor C, building a parallel resonance tank Rtank! We need an active element –Rtank, compensating the losses of the inductor (RtankL) and the losses of the capacitor (RtankC). As the capacitance C is proportional to a tuning input voltage, the circuit results in a VCO with angular center frequency.

Wc = 1 / √LC (2-27)

Fig. 2.20 LC tuned VCO model

The capacitor C in Fig. 20 not only consists of a variable capacitor to tune the oscillator, but it also includes the parasitic or fixed capacitances of the inductor, the active elements, and the load. Anyway, to get the LC tank resistance value was

important before to design the resistance –Rtank value. Fig. 21, (a) show the LC tank simulation circuit of this work and Fig. 21, (b) show the real part and imaginary part about LC tank simulation resistance.

(a) Effect resistance of LC tank (b) Real part of LC tank resistance at 6GHz Fig. 2.21 The resistance simulation of LC tank in tuned VCO

In Fig. 16 shows the schematic of the VCO. Two cross-coupled transistors generate the negative impedance (-Rtank) required to cancel the losses of the negative impedance required to cancel the losses of the RLC tank. On-chip spiral inductors with patterned ground shield are used in this design. The three main requirements for the VCO are low phase noise, low power consumption and small layout area.

To improve the 1/f³ corner of the phase noise it is convenient to have a symmetric tank (gm,n = gm,p)[13][14]. For symmetric tanks, gneg,tank is given by the expression,

gneg,tank = - (gm,n + gm,p) / 2 = - gm,n (2-28)

To make sure this VCO can oscillate normally, the loop gain must at least 3 hence,

gm,n >= A * Gtank, max and A>=3 (2-29) Gtank, max = Rtank = LC tank resistance (2-30) Rtank = Re(Ztank), when Im(Ztank) = 0 (2-31) The VCO, which is another dominant source of PLL power consumption, need to be carefully optimized in terms of dissipation, without degrading tuning range and phase noise performance. The power consumption of an oscillator is inversely proportional to its phase noise level. Therefore, the efficiency of an oscillator topology is typically quantified in terms of the noise power product. The structure had perfect characteristics about low power, low phase noise and high output swing.

The simulation results describe in section 2.3.1.

The selection of VCO gain (Kvco) and VCO input range (Vctrl) are tradeoff in PLL.

Table 6 shows the influences in PLL about the tradeoff of Kvco and Vctrl. The best choices about them are middleman values.

Kvco ↓ and Vctrl ↑ Kvco ↑ and Vctrl ↓

VCO Output Sensitivity Low High

Loop Damping Effect Low High

Low-pass-filter Bandwidth High Bandwidth Narrow Bandwidth

Loop Settling Time Small Large

Low-pass-filter size Small Large

Charge pump output range High Low

Charge pump channel length modulation effect

High Low

Table 6 The influences of Kvco and Vctrl in PLL